Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 203166 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 563723 1 T2 2 T4 16 T8 10



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 469934 1 T2 1 T4 12 T8 6
values[0x0] 144669 1 T2 1 T4 23 T8 10
values[0x1] 152286 1 T4 19 T7 2 T8 15



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 154429 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 612460 1 T2 2 T4 20 T8 13



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3282 1 T143 4 T170 1 T171 1
valid_sources[0x01] 2512 1 T5 1 T14 1 T32 1
valid_sources[0x02] 2601 1 T19 2 T166 2 T203 1
valid_sources[0x03] 2941 1 T19 3 T15 2 T43 2
valid_sources[0x04] 3545 1 T169 1 T167 4 T43 6
valid_sources[0x05] 3353 1 T19 1 T204 1 T43 12
valid_sources[0x06] 2714 1 T171 2 T32 1 T159 10
valid_sources[0x07] 3235 1 T158 1 T159 1 T43 2
valid_sources[0x08] 2847 1 T143 1 T43 3 T54 29
valid_sources[0x09] 3151 1 T170 2 T25 5 T43 16
valid_sources[0x0a] 3373 1 T5 3 T163 29 T167 1
valid_sources[0x0b] 2226 1 T17 11 T205 27 T158 1
valid_sources[0x0c] 2953 1 T171 1 T43 4 T54 29
valid_sources[0x0d] 2986 1 T27 1 T43 2 T54 9
valid_sources[0x0e] 2627 1 T138 1 T143 1 T43 7
valid_sources[0x0f] 2795 1 T43 2 T54 6 T56 54
valid_sources[0x10] 2446 1 T138 2 T187 2 T15 1
valid_sources[0x11] 2619 1 T206 1 T43 1 T54 8
valid_sources[0x12] 3235 1 T15 1 T43 5 T54 42
valid_sources[0x13] 2513 1 T171 1 T11 1 T17 1
valid_sources[0x14] 3201 1 T43 9 T54 11 T56 18
valid_sources[0x15] 3088 1 T27 1 T23 1 T43 8
valid_sources[0x16] 2780 1 T19 1 T143 1 T167 3
valid_sources[0x17] 3503 1 T2 1 T10 28 T47 1
valid_sources[0x18] 2896 1 T206 6 T204 1 T43 1
valid_sources[0x19] 2991 1 T23 1 T143 2 T43 8
valid_sources[0x1a] 3103 1 T15 1 T16 24 T43 4
valid_sources[0x1b] 2924 1 T27 1 T158 1 T54 9
valid_sources[0x1c] 3187 1 T27 1 T23 1 T161 7
valid_sources[0x1d] 3084 1 T97 4 T138 1 T162 2
valid_sources[0x1e] 3198 1 T138 2 T43 1 T54 23
valid_sources[0x1f] 2599 1 T162 1 T25 1 T43 2
valid_sources[0x20] 2990 1 T161 3 T143 2 T43 10
valid_sources[0x21] 2820 1 T4 6 T24 1 T167 10
valid_sources[0x22] 3039 1 T46 1 T138 2 T37 2
valid_sources[0x23] 3346 1 T15 1 T207 1 T172 2
valid_sources[0x24] 2503 1 T23 1 T158 1 T43 2
valid_sources[0x25] 2677 1 T4 7 T43 13 T54 10
valid_sources[0x26] 5023 1 T43 3 T54 21 T56 13
valid_sources[0x27] 2790 1 T15 1 T14 2 T164 1
valid_sources[0x28] 2847 1 T27 1 T24 1 T15 1
valid_sources[0x29] 2855 1 T23 1 T43 11 T54 28
valid_sources[0x2a] 2868 1 T4 5 T41 1 T143 1
valid_sources[0x2b] 2650 1 T27 1 T171 1 T14 2
valid_sources[0x2c] 3270 1 T166 3 T54 12 T56 28
valid_sources[0x2d] 2927 1 T19 3 T43 8 T54 20
valid_sources[0x2e] 2784 1 T19 3 T15 1 T170 2
valid_sources[0x2f] 2474 1 T23 1 T9 1 T19 3
valid_sources[0x30] 2935 1 T24 1 T207 11 T206 1
valid_sources[0x31] 2851 1 T43 22 T54 36 T56 35
valid_sources[0x32] 2789 1 T19 1 T162 1 T11 1
valid_sources[0x33] 2608 1 T23 1 T97 2 T143 1
valid_sources[0x34] 3021 1 T19 3 T43 2 T54 21
valid_sources[0x35] 2676 1 T45 1 T97 1 T158 4
valid_sources[0x36] 3265 1 T15 1 T170 1 T167 1
valid_sources[0x37] 2969 1 T43 1 T54 24 T99 4
valid_sources[0x38] 2838 1 T166 1 T208 1 T43 18
valid_sources[0x39] 2829 1 T43 7 T54 19 T56 16
valid_sources[0x3a] 2718 1 T15 1 T209 2 T43 3
valid_sources[0x3b] 2912 1 T143 1 T11 2 T204 1
valid_sources[0x3c] 2891 1 T43 6 T54 23 T56 12
valid_sources[0x3d] 2884 1 T162 1 T167 3 T158 1
valid_sources[0x3e] 2741 1 T11 1 T43 4 T54 10
valid_sources[0x3f] 2568 1 T19 1 T143 1 T206 2
valid_sources[0x40] 2788 1 T166 3 T43 9 T54 27
valid_sources[0x41] 3172 1 T162 1 T54 19 T56 3
valid_sources[0x42] 3322 1 T73 39 T158 1 T43 9
valid_sources[0x43] 4835 1 T45 1 T204 1 T43 2
valid_sources[0x44] 2999 1 T207 1 T32 2 T43 9
valid_sources[0x45] 2882 1 T14 1 T54 61 T56 32
valid_sources[0x46] 2345 1 T54 17 T56 18 T98 2
valid_sources[0x47] 3138 1 T23 1 T32 2 T43 3
valid_sources[0x48] 5403 1 T8 3 T15 1 T204 1
valid_sources[0x49] 2754 1 T138 2 T207 2 T43 1
valid_sources[0x4a] 2643 1 T166 1 T43 12 T54 26
valid_sources[0x4b] 2876 1 T5 1 T43 4 T54 8
valid_sources[0x4c] 2971 1 T9 1 T19 2 T143 1
valid_sources[0x4d] 2600 1 T32 1 T203 1 T43 3
valid_sources[0x4e] 2806 1 T170 1 T167 1 T43 12
valid_sources[0x4f] 3325 1 T162 1 T15 1 T43 4
valid_sources[0x50] 2404 1 T162 3 T168 17 T159 4
valid_sources[0x51] 12174 1 T165 18 T43 6 T54 26
valid_sources[0x52] 2784 1 T8 2 T19 1 T48 1
valid_sources[0x53] 2902 1 T161 5 T43 2 T54 6
valid_sources[0x54] 2527 1 T4 14 T19 1 T166 1
valid_sources[0x55] 3408 1 T23 1 T158 1 T43 11
valid_sources[0x56] 3290 1 T5 1 T19 1 T210 2
valid_sources[0x57] 3012 1 T97 2 T169 1 T43 8
valid_sources[0x58] 3155 1 T5 1 T14 1 T43 3
valid_sources[0x59] 2870 1 T143 1 T169 1 T43 5
valid_sources[0x5a] 3110 1 T37 2 T208 2 T43 9
valid_sources[0x5b] 3122 1 T14 1 T43 3 T54 19
valid_sources[0x5c] 2039 1 T15 1 T43 7 T54 40
valid_sources[0x5d] 2699 1 T143 2 T11 1 T43 5
valid_sources[0x5e] 3369 1 T160 8 T43 2 T54 17
valid_sources[0x5f] 3334 1 T204 1 T54 36 T56 27
valid_sources[0x60] 3009 1 T19 1 T208 2 T43 2
valid_sources[0x61] 2900 1 T138 7 T206 2 T43 1
valid_sources[0x62] 2759 1 T171 1 T167 4 T54 19
valid_sources[0x63] 3114 1 T170 1 T211 1 T206 1
valid_sources[0x64] 2473 1 T171 1 T204 1 T43 11
valid_sources[0x65] 3589 1 T5 1 T43 2 T54 38
valid_sources[0x66] 4345 1 T204 2 T43 22 T54 15
valid_sources[0x67] 2436 1 T204 1 T43 2 T54 17
valid_sources[0x68] 2584 1 T32 1 T43 7 T54 33
valid_sources[0x69] 2271 1 T15 1 T43 1 T54 6
valid_sources[0x6a] 2909 1 T203 1 T43 2 T54 18
valid_sources[0x6b] 2778 1 T169 1 T33 1 T172 3
valid_sources[0x6c] 2778 1 T27 1 T15 2 T32 1
valid_sources[0x6d] 3225 1 T4 1 T158 2 T164 1
valid_sources[0x6e] 3165 1 T5 1 T206 1 T32 1
valid_sources[0x6f] 2400 1 T5 1 T9 1 T14 1
valid_sources[0x70] 3472 1 T15 2 T209 3 T159 1
valid_sources[0x71] 2803 1 T170 6 T164 1 T203 1
valid_sources[0x72] 2693 1 T8 3 T63 20 T43 5
valid_sources[0x73] 3615 1 T159 14 T43 14 T54 9
valid_sources[0x74] 2827 1 T27 1 T15 1 T158 1
valid_sources[0x75] 2726 1 T209 2 T54 15 T56 27
valid_sources[0x76] 2450 1 T169 1 T43 4 T54 16
valid_sources[0x77] 2720 1 T46 7 T35 11 T32 1
valid_sources[0x78] 2748 1 T166 3 T172 4 T32 1
valid_sources[0x79] 2399 1 T167 5 T43 8 T54 33
valid_sources[0x7a] 2878 1 T14 1 T206 1 T32 1
valid_sources[0x7b] 3524 1 T19 1 T143 2 T158 1
valid_sources[0x7c] 2654 1 T23 1 T164 1 T43 2
valid_sources[0x7d] 2820 1 T23 1 T208 1 T43 2
valid_sources[0x7e] 2664 1 T143 2 T204 1 T43 8
valid_sources[0x7f] 2448 1 T8 11 T36 9 T43 8
valid_sources[0x80] 2920 1 T5 1 T138 1 T43 15



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 279286 1 T2 1 T4 5 T8 5
values[0x0] all_enables biggest_size 142397 1 T2 1 T4 9 T8 1
values[0x1] all_enables biggest_size 142040 1 T4 2 T8 4 T5 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5462 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 28535 1 T1 6 T2 1 T3 8



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 12212 1 T43 125 T54 34 T56 34
values[0x0] 10655 1 T1 5 T2 1 T3 4
values[0x1] 11130 1 T1 1 T3 4 T38 4



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4065 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 29932 1 T1 6 T2 1 T3 8



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 113 1 T43 1 T84 1 T92 2
valid_sources[0x01] 113 1 T212 1 T206 1 T43 1
valid_sources[0x02] 128 1 T24 2 T213 1 T91 3
valid_sources[0x03] 120 1 T64 1 T166 1 T43 5
valid_sources[0x04] 94 1 T144 2 T214 4 T43 2
valid_sources[0x05] 173 1 T20 1 T215 1 T90 30
valid_sources[0x06] 891 1 T38 1 T62 1 T43 1
valid_sources[0x07] 110 1 T216 1 T43 4 T54 2
valid_sources[0x08] 108 1 T217 1 T181 1 T43 3
valid_sources[0x09] 116 1 T64 1 T73 1 T43 4
valid_sources[0x0a] 147 1 T218 1 T62 1 T219 5
valid_sources[0x0b] 125 1 T72 5 T220 1 T221 1
valid_sources[0x0c] 212 1 T38 1 T222 1 T43 4
valid_sources[0x0d] 127 1 T223 2 T16 1 T43 1
valid_sources[0x0e] 124 1 T38 1 T36 1 T43 1
valid_sources[0x0f] 137 1 T224 1 T16 1 T100 2
valid_sources[0x10] 109 1 T208 2 T43 4 T92 1
valid_sources[0x11] 126 1 T43 1 T91 1 T44 2
valid_sources[0x12] 84 1 T225 1 T43 3 T44 2
valid_sources[0x13] 115 1 T18 1 T64 1 T54 4
valid_sources[0x14] 120 1 T138 2 T225 2 T43 4
valid_sources[0x15] 106 1 T226 6 T214 2 T102 1
valid_sources[0x16] 96 1 T182 1 T92 1 T103 2
valid_sources[0x17] 88 1 T27 1 T227 1 T37 1
valid_sources[0x18] 114 1 T43 5 T90 18 T91 1
valid_sources[0x19] 120 1 T46 1 T42 1 T203 1
valid_sources[0x1a] 111 1 T93 1 T44 3 T105 1
valid_sources[0x1b] 120 1 T84 1 T91 2 T92 1
valid_sources[0x1c] 91 1 T228 2 T92 1 T44 7
valid_sources[0x1d] 117 1 T49 1 T229 1 T207 1
valid_sources[0x1e] 152 1 T230 1 T231 1 T54 1
valid_sources[0x1f] 140 1 T218 1 T17 6 T43 3
valid_sources[0x20] 126 1 T146 1 T54 1 T56 6
valid_sources[0x21] 108 1 T232 2 T233 1 T227 2
valid_sources[0x22] 124 1 T218 1 T146 1 T163 3
valid_sources[0x23] 122 1 T182 1 T43 2 T92 1
valid_sources[0x24] 87 1 T234 1 T43 1 T44 6
valid_sources[0x25] 102 1 T8 5 T235 1 T236 1
valid_sources[0x26] 166 1 T24 1 T213 1 T228 2
valid_sources[0x27] 84 1 T237 1 T238 1 T43 6
valid_sources[0x28] 161 1 T221 1 T14 1 T43 1
valid_sources[0x29] 124 1 T24 1 T161 8 T138 1
valid_sources[0x2a] 128 1 T75 1 T92 1 T102 3
valid_sources[0x2b] 104 1 T213 1 T14 1 T184 4
valid_sources[0x2c] 270 1 T44 1 T239 4 T140 4
valid_sources[0x2d] 122 1 T213 1 T158 2 T43 1
valid_sources[0x2e] 115 1 T154 1 T70 1 T11 1
valid_sources[0x2f] 125 1 T23 7 T41 1 T43 6
valid_sources[0x30] 100 1 T227 1 T158 1 T238 1
valid_sources[0x31] 107 1 T44 7 T240 1 T140 3
valid_sources[0x32] 118 1 T46 1 T213 2 T221 1
valid_sources[0x33] 117 1 T218 1 T43 1 T92 3
valid_sources[0x34] 138 1 T241 1 T92 1 T44 3
valid_sources[0x35] 154 1 T77 1 T238 1 T43 1
valid_sources[0x36] 114 1 T24 1 T213 1 T182 1
valid_sources[0x37] 262 1 T41 1 T218 1 T242 1
valid_sources[0x38] 122 1 T64 1 T43 2 T92 2
valid_sources[0x39] 127 1 T73 1 T243 1 T43 3
valid_sources[0x3a] 105 1 T11 1 T172 7 T238 1
valid_sources[0x3b] 143 1 T49 1 T43 3 T99 1
valid_sources[0x3c] 225 1 T46 1 T234 1 T43 3
valid_sources[0x3d] 94 1 T43 3 T54 1 T92 1
valid_sources[0x3e] 81 1 T204 1 T92 2 T44 1
valid_sources[0x3f] 119 1 T244 3 T14 1 T231 1
valid_sources[0x40] 201 1 T146 1 T11 1 T245 2
valid_sources[0x41] 137 1 T246 2 T242 1 T25 1
valid_sources[0x42] 120 1 T227 1 T247 1 T43 2
valid_sources[0x43] 95 1 T163 4 T11 3 T43 2
valid_sources[0x44] 110 1 T188 1 T242 1 T158 2
valid_sources[0x45] 291 1 T153 1 T246 1 T43 2
valid_sources[0x46] 99 1 T38 1 T227 1 T43 1
valid_sources[0x47] 215 1 T38 1 T16 1 T14 1
valid_sources[0x48] 107 1 T248 1 T231 1 T43 2
valid_sources[0x49] 85 1 T218 1 T190 1 T204 1
valid_sources[0x4a] 119 1 T41 1 T138 2 T171 1
valid_sources[0x4b] 119 1 T57 1 T170 1 T249 1
valid_sources[0x4c] 89 1 T250 4 T43 2 T91 1
valid_sources[0x4d] 126 1 T5 3 T78 1 T246 1
valid_sources[0x4e] 263 1 T38 1 T80 1 T251 2
valid_sources[0x4f] 132 1 T152 1 T28 1 T43 2
valid_sources[0x50] 119 1 T223 1 T232 1 T43 2
valid_sources[0x51] 87 1 T252 3 T92 3 T44 2
valid_sources[0x52] 128 1 T253 1 T43 1 T85 3
valid_sources[0x53] 150 1 T49 3 T88 1 T93 3
valid_sources[0x54] 108 1 T254 3 T54 2 T91 1
valid_sources[0x55] 121 1 T86 3 T91 3 T92 1
valid_sources[0x56] 99 1 T168 1 T43 1 T92 3
valid_sources[0x57] 113 1 T89 1 T34 1 T43 1
valid_sources[0x58] 206 1 T46 3 T43 4 T84 1
valid_sources[0x59] 103 1 T96 6 T21 1 T243 1
valid_sources[0x5a] 106 1 T255 4 T43 1 T99 1
valid_sources[0x5b] 217 1 T16 1 T203 1 T43 2
valid_sources[0x5c] 82 1 T230 1 T169 6 T220 1
valid_sources[0x5d] 106 1 T5 2 T175 1 T204 1
valid_sources[0x5e] 107 1 T43 4 T92 1 T93 1
valid_sources[0x5f] 145 1 T224 1 T43 7 T44 7
valid_sources[0x60] 123 1 T244 4 T150 1 T243 1
valid_sources[0x61] 135 1 T45 5 T24 1 T87 1
valid_sources[0x62] 133 1 T229 1 T43 1 T91 1
valid_sources[0x63] 144 1 T182 1 T187 1 T166 1
valid_sources[0x64] 84 1 T69 1 T144 1 T207 1
valid_sources[0x65] 121 1 T138 1 T210 1 T25 1
valid_sources[0x66] 105 1 T43 4 T92 4 T44 3
valid_sources[0x67] 100 1 T244 1 T43 4 T92 2
valid_sources[0x68] 113 1 T43 2 T54 1 T92 2
valid_sources[0x69] 88 1 T218 1 T73 1 T244 2
valid_sources[0x6a] 93 1 T73 1 T43 4 T54 1
valid_sources[0x6b] 113 1 T27 1 T92 2 T44 2
valid_sources[0x6c] 146 1 T24 1 T43 5 T44 4
valid_sources[0x6d] 88 1 T43 5 T84 5 T85 3
valid_sources[0x6e] 129 1 T6 6 T242 1 T54 1
valid_sources[0x6f] 192 1 T18 1 T64 1 T256 4
valid_sources[0x70] 132 1 T224 2 T217 2 T257 9
valid_sources[0x71] 81 1 T223 1 T251 1 T43 4
valid_sources[0x72] 146 1 T238 1 T43 2 T44 3
valid_sources[0x73] 96 1 T166 5 T43 4 T91 2
valid_sources[0x74] 157 1 T27 1 T223 1 T146 1
valid_sources[0x75] 154 1 T92 2 T44 4 T108 70
valid_sources[0x76] 103 1 T238 2 T99 1 T92 4
valid_sources[0x77] 87 1 T242 1 T185 1 T171 2
valid_sources[0x78] 120 1 T43 2 T91 1 T44 4
valid_sources[0x79] 94 1 T5 4 T223 1 T215 1
valid_sources[0x7a] 123 1 T230 1 T160 7 T255 1
valid_sources[0x7b] 90 1 T158 1 T236 1 T43 2
valid_sources[0x7c] 139 1 T213 1 T238 1 T90 14
valid_sources[0x7d] 119 1 T258 5 T43 4 T54 1
valid_sources[0x7e] 137 1 T27 1 T65 17 T259 8
valid_sources[0x7f] 98 1 T171 2 T179 1 T91 1
valid_sources[0x80] 113 1 T1 6 T43 6 T92 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 8882 1 T43 115 T54 11 T56 34
values[0x0] all_enables biggest_size 9877 1 T1 5 T2 1 T3 4
values[0x1] all_enables biggest_size 9776 1 T1 1 T3 4 T4 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%