SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 801770 | 1 | T2 | 2 | T4 | 54 | T7 | 2 | |||
auto[1] | 31873 | 1 | T31 | 80 | T32 | 80 | T43 | 307 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 833469 | 1 | T2 | 2 | T4 | 54 | T7 | 2 | |||
values[1] | 18 | 1 | T85 | 1 | T91 | 1 | T93 | 1 | |||
values[2] | 3 | 1 | T93 | 1 | T194 | 1 | T195 | 1 | |||
values[3] | 90 | 1 | T54 | 3 | T85 | 6 | T86 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 833453 | 1 | T2 | 2 | T4 | 54 | T7 | 2 | |||
values[1] | 22 | 1 | T86 | 1 | T93 | 4 | T196 | 1 | |||
values[2] | 10 | 1 | T85 | 2 | T91 | 1 | T93 | 1 | |||
values[3] | 95 | 1 | T54 | 4 | T85 | 1 | T86 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 833363 | 1 | T2 | 2 | T4 | 54 | T7 | 2 | |||
auto[TlIntgErrCmd] | 90 | 1 | T54 | 4 | T85 | 3 | T86 | 4 | |||
auto[TlIntgErrData] | 106 | 1 | T54 | 3 | T85 | 1 | T86 | 4 | |||
auto[TlIntgErrBoth] | 84 | 1 | T54 | 3 | T85 | 6 | T86 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 63101 | 0 | T1 | 6 | T2 | 1 | T3 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 62913 | 1 | T1 | 6 | T2 | 1 | T3 | 8 | |||
values[1] | 16 | 1 | T54 | 1 | T91 | 1 | T93 | 2 | |||
values[2] | 2 | 1 | T141 | 1 | T197 | 1 | - | - | |||
values[3] | 106 | 1 | T54 | 5 | T85 | 6 | T86 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 62923 | 1 | T1 | 6 | T2 | 1 | T3 | 8 | |||
values[1] | 23 | 1 | T85 | 3 | T86 | 1 | T93 | 3 | |||
values[2] | 9 | 1 | T85 | 1 | T86 | 1 | T91 | 1 | |||
values[3] | 73 | 1 | T54 | 3 | T85 | 2 | T86 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 62821 | 1 | T1 | 6 | T2 | 1 | T3 | 8 | |||
auto[TlIntgErrCmd] | 102 | 1 | T54 | 7 | T85 | 4 | T86 | 2 | |||
auto[TlIntgErrData] | 92 | 1 | T85 | 2 | T86 | 6 | T91 | 7 | |||
auto[TlIntgErrBoth] | 86 | 1 | T54 | 3 | T85 | 4 | T86 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |