Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	267231	1		T4	38		T7	2		T8	21
full_word	566412	1		T2	2		T4	16		T8	10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	833363	1		T2	2		T4	54		T7	2
auto[TlIntgErrCmd]	90	1		T54	4		T85	3		T86	4
auto[TlIntgErrData]	106	1		T54	3		T85	1		T86	4
auto[TlIntgErrBoth]	84	1		T54	3		T85	6		T86	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	473204	1		T2	1		T4	12		T8	6
auto[1]	360439	1		T2	1		T4	42		T7	2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	193414	1		T4	7		T8	1		T5	1
auto[TlIntgErrNone]	partial	auto[1]	73560	1		T4	31		T7	2		T8	20
auto[TlIntgErrNone]	full_word	auto[0]	279658	1		T2	1		T4	5		T8	5
auto[TlIntgErrNone]	full_word	auto[1]	286731	1		T2	1		T4	11		T8	5
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T54	2		T85	1		T86	2
auto[TlIntgErrCmd]	partial	auto[1]	40	1		T54	2		T85	2		T86	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T86	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T91	1		T194	1		T198	1
auto[TlIntgErrData]	partial	auto[0]	49	1		T86	2		T91	4		T93	1
auto[TlIntgErrData]	partial	auto[1]	49	1		T54	3		T85	1		T86	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T196	1		T199	1		T197	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T200	2		T201	1		T202	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T54	1		T85	2		T86	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1		T54	2		T85	2		T91	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T85	1		T86	1		T200	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T85	1		T93	1		T141	1