Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	108663320	23598	0	0
late_debug_enable_rd_A	108663320	3399	0	0
late_debug_enable_regwen_rd_A	108663320	3143	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108663320	23598	0	0
T43	322434	194	0	0
T54	56885	4	0	0
T55	35086	44	0	0
T84	209755	217	0	0
T85	61650	3	0	0
T86	18075	1	0	0
T90	3105	273	0	0
T91	148294	3	0	0
T92	11975	209	0	0
T93	95301	3	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108663320	3399	0	0
T85	61650	56	0	0
T93	95301	79	0	0
T101	10764	6	0	0
T104	41974	43	0	0
T105	28710	43	0	0
T107	338905	16	0	0
T139	4518	1	0	0
T140	236737	600	0	0
T141	87201	36	0	0
T142	10222	113	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108663320	3143	0	0
T85	61650	41	0	0
T93	95301	83	0	0
T101	10764	3	0	0
T104	41974	48	0	0
T105	28710	16	0	0
T107	338905	15	0	0
T139	4518	1	0	0
T140	236737	394	0	0
T141	87201	47	0	0
T142	10222	104	0	0