Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	87.50	100.00					75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm_enable_checker

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
36	1	1

---

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	40012853	6677216	0	0
MemTLResponseWithoutDebugIsError_A	40012853	10	0	0
NdmResetAckNeedsDebug_A	40012853	0	0	0
SbaTLRequestNeedsDebug_A	40012853	10208	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40012853	6677216	0	0
T4	185595	103502	0	0
T5	236518	49782	0	0
T6	657539	256574	0	0
T7	34660	10455	0	0
T8	160687	32503	0	0
T9	0	10756	0	0
T23	0	61872	0	0
T26	328978	0	0	0
T27	0	156680	0	0
T28	0	8723	0	0
T39	1280	0	0	0
T40	230222	0	0	0
T41	0	62812	0	0
T49	1568	0	0	0
T57	2172	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40012853	10	0	0
T47	3201	2	0	0
T48	0	8	0	0
T68	207304	0	0	0
T69	882447	0	0	0
T70	284774	0	0	0
T71	100549	0	0	0
T72	94557	0	0	0
T73	603682	0	0	0
T74	1883	0	0	0
T75	28925	0	0	0
T76	19575	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40012853	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40012853	10208	0	0
T1	250068	743	0	0
T2	13723	0	0	0
T3	115283	170	0	0
T4	185595	0	0	0
T7	34660	0	0	0
T8	160687	0	0	0
T13	51050	77	0	0
T26	0	181	0	0
T38	3463	0	0	0
T39	1280	0	0	0
T40	230222	16	0	0
T53	0	12	0	0
T77	0	39	0	0
T78	0	46	0	0
T79	0	75	0	0
T80	0	56	0	0