Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8683074 8681722 0 0
selKnown1 46293707 46292355 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8683074 8681722 0 0
T1 158644 158640 0 0
T2 1548 1544 0 0
T3 32659 32655 0 0
T4 34218 34214 0 0
T5 0 22 0 0
T6 0 26 0 0
T7 1754 1750 0 0
T8 57861 57857 0 0
T13 19680 19676 0 0
T23 0 31 0 0
T27 0 27 0 0
T38 429 425 0 0
T39 1088 1084 0 0
T40 18605 18601 0 0
T41 0 67 0 0
T53 0 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 46293707 46292355 0 0
T1 329396 329393 0 0
T2 14498 14494 0 0
T3 131620 131616 0 0
T4 202710 202706 0 0
T5 0 8 0 0
T6 0 6 0 0
T7 35538 35534 0 0
T8 189597 189593 0 0
T13 60891 60887 0 0
T23 0 10 0 0
T27 0 8 0 0
T38 3678 3674 0 0
T39 1825 1821 0 0
T40 239525 239521 0 0
T41 0 8 0 0
T53 0 10 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2401424 2401196 0 0
selKnown1 40012853 40012625 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2401424 2401196 0 0
T1 79316 79315 0 0
T2 773 772 0 0
T3 16321 16320 0 0
T4 17103 17102 0 0
T7 876 875 0 0
T8 28896 28895 0 0
T13 9839 9838 0 0
T38 213 212 0 0
T39 543 542 0 0
T40 9301 9300 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 40012853 40012625 0 0
T1 250068 250068 0 0
T2 13723 13722 0 0
T3 115283 115282 0 0
T4 185595 185594 0 0
T7 34660 34659 0 0
T8 160687 160686 0 0
T13 51050 51049 0 0
T38 3463 3462 0 0
T39 1280 1279 0 0
T40 230222 230221 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 799 571 0 0
selKnown1 616 388 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 799 571 0 0
T1 6 5 0 0
T2 1 0 0 0
T3 8 7 0 0
T4 6 5 0 0
T5 0 11 0 0
T6 0 13 0 0
T7 1 0 0 0
T8 34 33 0 0
T13 1 0 0 0
T23 0 14 0 0
T27 0 9 0 0
T38 1 0 0 0
T39 1 0 0 0
T40 1 0 0 0
T41 0 28 0 0
T53 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 616 388 0 0
T1 6 5 0 0
T2 1 0 0 0
T3 8 7 0 0
T4 6 5 0 0
T5 0 4 0 0
T6 0 3 0 0
T7 1 0 0 0
T8 7 6 0 0
T13 1 0 0 0
T23 0 5 0 0
T27 0 4 0 0
T38 1 0 0 0
T39 1 0 0 0
T40 1 0 0 0
T41 0 4 0 0
T53 0 5 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6278776 6278328 0 0
selKnown1 6278563 6278115 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6278776 6278328 0 0
T1 79316 79315 0 0
T2 773 772 0 0
T3 16322 16321 0 0
T4 17103 17102 0 0
T7 876 875 0 0
T8 28897 28896 0 0
T13 9839 9838 0 0
T38 214 213 0 0
T39 543 542 0 0
T40 9302 9301 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6278563 6278115 0 0
T1 79316 79315 0 0
T2 773 772 0 0
T3 16321 16320 0 0
T4 17103 17102 0 0
T7 876 875 0 0
T8 28896 28895 0 0
T13 9839 9838 0 0
T38 213 212 0 0
T39 543 542 0 0
T40 9301 9300 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2075 1627 0 0
selKnown1 1675 1227 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2075 1627 0 0
T1 6 5 0 0
T2 1 0 0 0
T3 8 7 0 0
T4 6 5 0 0
T5 0 11 0 0
T6 0 13 0 0
T7 1 0 0 0
T8 34 33 0 0
T13 1 0 0 0
T23 0 17 0 0
T27 0 18 0 0
T38 1 0 0 0
T39 1 0 0 0
T40 1 0 0 0
T41 0 39 0 0
T53 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1675 1227 0 0
T1 6 5 0 0
T2 1 0 0 0
T3 8 7 0 0
T4 6 5 0 0
T5 0 4 0 0
T6 0 3 0 0
T7 1 0 0 0
T8 7 6 0 0
T13 1 0 0 0
T23 0 5 0 0
T27 0 4 0 0
T38 1 0 0 0
T39 1 0 0 0
T40 1 0 0 0
T41 0 4 0 0
T53 0 5 0 0

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