Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	215880	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	598039	1		T9	2		T30	2		T7	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	507590	1		T9	1		T7	10		T31	1
values[0x0]	150365	1		T30	1		T7	1		T8	3
values[0x1]	155964	1		T9	1		T30	1		T8	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	164512	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	649407	1		T9	2		T30	2		T7	8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2997	1		T39	2		T60	81		T61	5
valid_sources[0x01]	2882	1		T60	57		T61	3		T63	13
valid_sources[0x02]	4056	1		T26	1		T39	1		T60	36
valid_sources[0x03]	2750	1		T187	1		T26	1		T148	1
valid_sources[0x04]	2781	1		T136	1		T188	1		T189	1
valid_sources[0x05]	3046	1		T190	13		T28	2		T60	35
valid_sources[0x06]	3376	1		T18	2		T60	31		T61	7
valid_sources[0x07]	3333	1		T136	1		T18	1		T138	2
valid_sources[0x08]	3106	1		T26	1		T145	1		T60	31
valid_sources[0x09]	3403	1		T60	54		T61	6		T63	21
valid_sources[0x0a]	2985	1		T26	1		T60	17		T61	11
valid_sources[0x0b]	2963	1		T39	1		T60	42		T61	8
valid_sources[0x0c]	3362	1		T191	1		T60	44		T61	3
valid_sources[0x0d]	2967	1		T42	2		T136	2		T39	1
valid_sources[0x0e]	2716	1		T15	19		T189	1		T60	52
valid_sources[0x0f]	3521	1		T39	1		T60	45		T61	10
valid_sources[0x10]	3799	1		T136	1		T28	2		T145	1
valid_sources[0x11]	3118	1		T26	1		T60	45		T61	15
valid_sources[0x12]	4094	1		T39	1		T60	29		T61	7
valid_sources[0x13]	2600	1		T43	3		T60	34		T61	8
valid_sources[0x14]	3365	1		T43	1		T192	1		T60	30
valid_sources[0x15]	3271	1		T60	32		T61	9		T63	37
valid_sources[0x16]	3168	1		T39	1		T60	51		T61	4
valid_sources[0x17]	5696	1		T18	1		T153	1		T140	2
valid_sources[0x18]	3443	1		T43	1		T26	1		T39	1
valid_sources[0x19]	3523	1		T140	1		T138	1		T193	1
valid_sources[0x1a]	2731	1		T43	1		T60	29		T61	6
valid_sources[0x1b]	3295	1		T139	3		T141	2		T60	39
valid_sources[0x1c]	3748	1		T23	1		T140	1		T138	1
valid_sources[0x1d]	3382	1		T146	1		T23	1		T60	31
valid_sources[0x1e]	3999	1		T60	53		T61	6		T63	25
valid_sources[0x1f]	3158	1		T138	1		T60	71		T61	7
valid_sources[0x20]	2825	1		T39	2		T140	1		T60	28
valid_sources[0x21]	2966	1		T148	1		T138	1		T60	47
valid_sources[0x22]	3311	1		T43	1		T148	1		T25	1
valid_sources[0x23]	2938	1		T142	2		T189	1		T60	20
valid_sources[0x24]	2696	1		T147	3		T60	42		T61	9
valid_sources[0x25]	3423	1		T136	1		T194	31		T60	34
valid_sources[0x26]	2959	1		T39	2		T142	1		T195	1
valid_sources[0x27]	3282	1		T39	4		T60	10		T61	5
valid_sources[0x28]	3269	1		T39	2		T60	58		T61	3
valid_sources[0x29]	2940	1		T138	1		T25	3		T60	47
valid_sources[0x2a]	3611	1		T26	1		T134	8		T25	1
valid_sources[0x2b]	2829	1		T130	16		T25	2		T60	55
valid_sources[0x2c]	3143	1		T188	1		T60	32		T61	7
valid_sources[0x2d]	3260	1		T5	1		T136	1		T23	1
valid_sources[0x2e]	2773	1		T28	5		T60	35		T61	5
valid_sources[0x2f]	3124	1		T26	1		T188	1		T138	2
valid_sources[0x30]	3041	1		T16	45		T26	1		T138	1
valid_sources[0x31]	2916	1		T43	1		T191	1		T60	64
valid_sources[0x32]	3189	1		T39	1		T153	1		T142	2
valid_sources[0x33]	3536	1		T146	1		T39	1		T188	2
valid_sources[0x34]	2774	1		T23	1		T141	1		T60	29
valid_sources[0x35]	2704	1		T39	1		T192	2		T60	62
valid_sources[0x36]	3272	1		T138	3		T60	72		T61	4
valid_sources[0x37]	2616	1		T43	1		T51	1		T148	1
valid_sources[0x38]	3157	1		T31	2		T136	1		T145	1
valid_sources[0x39]	2921	1		T17	9		T138	1		T60	58
valid_sources[0x3a]	3835	1		T140	1		T142	2		T147	1
valid_sources[0x3b]	3862	1		T60	51		T61	9		T63	23
valid_sources[0x3c]	3132	1		T196	1		T138	1		T60	38
valid_sources[0x3d]	3177	1		T43	1		T145	1		T60	49
valid_sources[0x3e]	4189	1		T7	2		T188	1		T60	70
valid_sources[0x3f]	3253	1		T197	1		T60	49		T61	8
valid_sources[0x40]	3120	1		T43	1		T136	1		T146	2
valid_sources[0x41]	3031	1		T136	2		T190	9		T60	59
valid_sources[0x42]	3148	1		T7	1		T28	3		T142	1
valid_sources[0x43]	2929	1		T39	1		T60	59		T61	7
valid_sources[0x44]	4146	1		T190	1		T26	1		T140	2
valid_sources[0x45]	2984	1		T5	1		T39	1		T60	20
valid_sources[0x46]	2515	1		T140	1		T60	37		T61	7
valid_sources[0x47]	3572	1		T43	1		T18	1		T142	1
valid_sources[0x48]	3473	1		T39	2		T60	72		T61	8
valid_sources[0x49]	2555	1		T60	23		T61	6		T63	27
valid_sources[0x4a]	3310	1		T21	10		T188	3		T60	52
valid_sources[0x4b]	3188	1		T26	1		T139	1		T138	1
valid_sources[0x4c]	3249	1		T137	2		T197	4		T60	40
valid_sources[0x4d]	2771	1		T198	2		T60	33		T61	6
valid_sources[0x4e]	3581	1		T39	2		T148	2		T140	1
valid_sources[0x4f]	3606	1		T18	1		T39	1		T60	57
valid_sources[0x50]	3101	1		T141	1		T60	83		T61	6
valid_sources[0x51]	3810	1		T136	1		T142	2		T143	14
valid_sources[0x52]	2538	1		T136	2		T39	1		T138	1
valid_sources[0x53]	3209	1		T5	1		T140	3		T60	55
valid_sources[0x54]	2989	1		T196	2		T195	1		T60	26
valid_sources[0x55]	2893	1		T42	2		T148	1		T145	1
valid_sources[0x56]	2912	1		T5	1		T60	23		T61	3
valid_sources[0x57]	3792	1		T153	1		T192	1		T60	29
valid_sources[0x58]	3363	1		T14	3		T60	28		T61	8
valid_sources[0x59]	3188	1		T5	1		T138	2		T193	1
valid_sources[0x5a]	3457	1		T153	1		T147	1		T60	19
valid_sources[0x5b]	3191	1		T60	40		T61	6		T63	26
valid_sources[0x5c]	2979	1		T25	1		T60	63		T61	8
valid_sources[0x5d]	2886	1		T43	1		T188	1		T142	1
valid_sources[0x5e]	2788	1		T138	1		T60	17		T61	8
valid_sources[0x5f]	3802	1		T136	3		T26	2		T148	1
valid_sources[0x60]	3304	1		T189	1		T60	34		T61	6
valid_sources[0x61]	3369	1		T24	25		T136	1		T190	3
valid_sources[0x62]	3383	1		T26	1		T60	50		T61	6
valid_sources[0x63]	3863	1		T188	1		T28	2		T147	1
valid_sources[0x64]	3139	1		T189	1		T60	48		T61	4
valid_sources[0x65]	2882	1		T142	2		T60	22		T61	4
valid_sources[0x66]	3145	1		T7	3		T6	2		T15	5
valid_sources[0x67]	3416	1		T5	1		T136	1		T39	1
valid_sources[0x68]	2844	1		T192	2		T60	40		T61	7
valid_sources[0x69]	2941	1		T18	1		T188	1		T192	1
valid_sources[0x6a]	3178	1		T142	1		T60	16		T61	4
valid_sources[0x6b]	2948	1		T39	2		T138	1		T60	27
valid_sources[0x6c]	3038	1		T39	3		T60	45		T61	4
valid_sources[0x6d]	3666	1		T146	1		T60	35		T61	2
valid_sources[0x6e]	2973	1		T145	1		T60	60		T61	6
valid_sources[0x6f]	2642	1		T60	31		T61	8		T63	27
valid_sources[0x70]	2857	1		T45	9		T39	1		T139	12
valid_sources[0x71]	3021	1		T5	1		T6	3		T40	1
valid_sources[0x72]	4979	1		T187	1		T138	3		T60	43
valid_sources[0x73]	2981	1		T8	6		T39	1		T60	67
valid_sources[0x74]	3537	1		T14	1		T39	3		T138	1
valid_sources[0x75]	2882	1		T39	1		T153	1		T60	41
valid_sources[0x76]	3410	1		T136	1		T26	1		T39	1
valid_sources[0x77]	2754	1		T138	1		T142	1		T60	46
valid_sources[0x78]	3464	1		T142	2		T60	38		T61	3
valid_sources[0x79]	3238	1		T43	1		T28	1		T60	40
valid_sources[0x7a]	3067	1		T30	1		T4	17		T26	1
valid_sources[0x7b]	2760	1		T40	1		T13	19		T138	1
valid_sources[0x7c]	2991	1		T44	9		T136	2		T60	50
valid_sources[0x7d]	2932	1		T40	1		T60	18		T61	9
valid_sources[0x7e]	2983	1		T39	1		T60	34		T61	6
valid_sources[0x7f]	2807	1		T138	1		T60	51		T61	3
valid_sources[0x80]	4093	1		T6	1		T138	3		T142	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

301524

1

T9

1

T7

5

T31

1

values[0x0]

all_enables

biggest_size

148362

1

T30

1

T31

1

T4

2

values[0x1]

all_enables

biggest_size

148153

1

T9

1

T30

1

T8

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4873	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	21466	1		T1	8		T2	2		T3	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9678	1		T60	66		T61	32		T63	22
values[0x0]	8199	1		T1	4		T2	4		T3	4
values[0x1]	8462	1		T1	4		T2	3		T9	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3712	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	22627	1		T1	8		T2	3		T3	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	87	1		T16	1		T199	3		T25	1
valid_sources[0x01]	142	1		T53	1		T33	1		T73	2
valid_sources[0x02]	79	1		T69	1		T148	1		T47	4
valid_sources[0x03]	127	1		T53	1		T36	1		T153	1
valid_sources[0x04]	113	1		T200	1		T201	1		T61	3
valid_sources[0x05]	73	1		T31	6		T124	1		T17	1
valid_sources[0x06]	60	1		T63	1		T47	2		T93	1
valid_sources[0x07]	89	1		T57	1		T202	1		T47	3
valid_sources[0x08]	103	1		T203	6		T204	1		T92	3
valid_sources[0x09]	55	1		T53	1		T205	2		T206	1
valid_sources[0x0a]	67	1		T53	1		T202	1		T154	1
valid_sources[0x0b]	183	1		T21	2		T207	1		T138	1
valid_sources[0x0c]	80	1		T9	1		T24	1		T208	1
valid_sources[0x0d]	114	1		T153	1		T143	1		T47	4
valid_sources[0x0e]	82	1		T53	1		T52	1		T84	2
valid_sources[0x0f]	96	1		T33	1		T209	1		T210	2
valid_sources[0x10]	75	1		T124	1		T208	1		T142	1
valid_sources[0x11]	86	1		T24	1		T150	2		T62	6
valid_sources[0x12]	79	1		T2	6		T211	1		T206	1
valid_sources[0x13]	95	1		T3	1		T212	1		T60	3
valid_sources[0x14]	71	1		T47	9		T84	1		T95	1
valid_sources[0x15]	177	1		T61	1		T63	1		T47	4
valid_sources[0x16]	130	1		T13	1		T209	1		T61	2
valid_sources[0x17]	83	1		T213	3		T214	1		T194	1
valid_sources[0x18]	58	1		T198	1		T47	3		T49	2
valid_sources[0x19]	106	1		T9	2		T79	1		T47	1
valid_sources[0x1a]	193	1		T188	1		T215	1		T62	7
valid_sources[0x1b]	86	1		T209	2		T47	3		T49	3
valid_sources[0x1c]	109	1		T57	1		T15	2		T210	1
valid_sources[0x1d]	80	1		T190	2		T35	1		T61	1
valid_sources[0x1e]	69	1		T216	1		T62	5		T47	5
valid_sources[0x1f]	114	1		T144	1		T206	1		T61	1
valid_sources[0x20]	109	1		T75	1		T217	15		T208	1
valid_sources[0x21]	83	1		T218	1		T219	1		T142	1
valid_sources[0x22]	105	1		T146	1		T200	1		T62	14
valid_sources[0x23]	63	1		T220	1		T28	1		T47	5
valid_sources[0x24]	120	1		T14	4		T28	3		T47	3
valid_sources[0x25]	85	1		T124	1		T63	2		T62	8
valid_sources[0x26]	119	1		T14	2		T73	1		T210	4
valid_sources[0x27]	60	1		T221	1		T47	3		T84	1
valid_sources[0x28]	87	1		T213	3		T222	1		T151	8
valid_sources[0x29]	92	1		T85	1		T202	1		T28	1
valid_sources[0x2a]	80	1		T45	1		T223	1		T47	1
valid_sources[0x2b]	86	1		T61	2		T62	5		T47	4
valid_sources[0x2c]	81	1		T210	1		T224	1		T225	1
valid_sources[0x2d]	82	1		T5	1		T156	1		T47	2
valid_sources[0x2e]	101	1		T226	1		T73	1		T192	1
valid_sources[0x2f]	167	1		T124	1		T17	1		T155	1
valid_sources[0x30]	81	1		T16	1		T152	1		T227	2
valid_sources[0x31]	88	1		T124	1		T220	1		T138	1
valid_sources[0x32]	63	1		T220	1		T148	1		T142	1
valid_sources[0x33]	101	1		T228	8		T229	1		T146	1
valid_sources[0x34]	88	1		T30	1		T230	2		T210	2
valid_sources[0x35]	67	1		T8	1		T231	1		T222	1
valid_sources[0x36]	48	1		T12	1		T70	2		T76	2
valid_sources[0x37]	71	1		T232	1		T133	1		T233	2
valid_sources[0x38]	71	1		T153	1		T164	1		T234	1
valid_sources[0x39]	70	1		T124	1		T235	1		T62	3
valid_sources[0x3a]	111	1		T16	1		T77	2		T62	2
valid_sources[0x3b]	112	1		T187	1		T47	3		T88	1
valid_sources[0x3c]	83	1		T60	3		T63	1		T47	4
valid_sources[0x3d]	67	1		T75	6		T213	2		T47	6
valid_sources[0x3e]	490	1		T220	1		T213	1		T63	1
valid_sources[0x3f]	67	1		T153	1		T225	1		T236	1
valid_sources[0x40]	181	1		T130	1		T17	1		T221	1
valid_sources[0x41]	71	1		T124	1		T200	1		T195	1
valid_sources[0x42]	127	1		T220	1		T153	1		T91	1
valid_sources[0x43]	85	1		T168	1		T60	3		T62	9
valid_sources[0x44]	61	1		T130	1		T47	2		T84	1
valid_sources[0x45]	218	1		T46	1		T36	3		T17	1
valid_sources[0x46]	86	1		T237	1		T61	4		T62	1
valid_sources[0x47]	202	1		T47	1		T84	1		T100	1
valid_sources[0x48]	79	1		T159	1		T61	2		T62	7
valid_sources[0x49]	192	1		T53	1		T208	1		T189	1
valid_sources[0x4a]	144	1		T67	1		T190	1		T238	1
valid_sources[0x4b]	53	1		T5	3		T26	1		T239	2
valid_sources[0x4c]	99	1		T137	2		T142	1		T84	1
valid_sources[0x4d]	65	1		T68	1		T23	1		T150	2
valid_sources[0x4e]	102	1		T190	1		T142	1		T189	1
valid_sources[0x4f]	131	1		T210	1		T200	1		T47	3
valid_sources[0x50]	117	1		T203	2		T202	1		T143	1
valid_sources[0x51]	251	1		T124	2		T139	3		T204	1
valid_sources[0x52]	83	1		T190	1		T142	1		T27	1
valid_sources[0x53]	46	1		T208	1		T61	1		T47	3
valid_sources[0x54]	77	1		T124	1		T146	1		T235	1
valid_sources[0x55]	89	1		T129	5		T142	1		T231	1
valid_sources[0x56]	90	1		T227	1		T47	3		T49	2
valid_sources[0x57]	48	1		T53	1		T137	1		T194	1
valid_sources[0x58]	67	1		T43	1		T61	4		T47	3
valid_sources[0x59]	74	1		T190	1		T61	1		T62	1
valid_sources[0x5a]	132	1		T29	4		T33	1		T73	1
valid_sources[0x5b]	78	1		T239	1		T227	1		T47	1
valid_sources[0x5c]	94	1		T203	3		T240	1		T204	1
valid_sources[0x5d]	128	1		T24	1		T241	2		T62	14
valid_sources[0x5e]	88	1		T220	1		T231	1		T236	1
valid_sources[0x5f]	111	1		T73	1		T229	3		T224	1
valid_sources[0x60]	77	1		T189	1		T204	1		T141	8
valid_sources[0x61]	62	1		T242	1		T60	3		T47	3
valid_sources[0x62]	151	1		T10	1		T13	1		T201	1
valid_sources[0x63]	82	1		T133	3		T225	1		T62	5
valid_sources[0x64]	115	1		T1	4		T13	2		T25	1
valid_sources[0x65]	103	1		T38	1		T243	2		T60	27
valid_sources[0x66]	99	1		T21	4		T61	1		T63	1
valid_sources[0x67]	471	1		T66	2		T149	1		T62	12
valid_sources[0x68]	66	1		T194	1		T62	3		T47	1
valid_sources[0x69]	86	1		T188	1		T244	2		T206	2
valid_sources[0x6a]	88	1		T208	1		T245	6		T235	1
valid_sources[0x6b]	114	1		T79	1		T136	8		T223	1
valid_sources[0x6c]	96	1		T76	3		T201	1		T61	2
valid_sources[0x6d]	59	1		T194	1		T62	6		T47	3
valid_sources[0x6e]	96	1		T153	1		T47	4		T84	1
valid_sources[0x6f]	155	1		T61	1		T47	3		T84	1
valid_sources[0x70]	67	1		T84	1		T49	2		T90	1
valid_sources[0x71]	90	1		T244	2		T61	1		T47	2
valid_sources[0x72]	93	1		T27	1		T61	1		T47	3
valid_sources[0x73]	54	1		T24	1		T153	1		T231	1
valid_sources[0x74]	56	1		T9	2		T57	1		T16	1
valid_sources[0x75]	68	1		T80	1		T190	1		T47	9
valid_sources[0x76]	79	1		T13	1		T166	1		T62	4
valid_sources[0x77]	163	1		T130	1		T37	1		T146	1
valid_sources[0x78]	69	1		T246	3		T163	1		T61	1
valid_sources[0x79]	63	1		T212	3		T133	1		T28	1
valid_sources[0x7a]	117	1		T153	1		T215	1		T60	53
valid_sources[0x7b]	65	1		T247	5		T235	1		T188	1
valid_sources[0x7c]	60	1		T73	2		T60	2		T61	1
valid_sources[0x7d]	52	1		T192	1		T63	1		T47	4
valid_sources[0x7e]	84	1		T130	1		T17	1		T70	2
valid_sources[0x7f]	97	1		T138	1		T225	1		T62	1
valid_sources[0x80]	135	1		T146	1		T63	1		T62	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6936

1

T60

24

T61

25

T63

22

values[0x0]

all_enables

biggest_size

7331

1

T1

4

T2

2

T3

2

values[0x1]

all_enables

biggest_size

7199

1

T1

4

T9

2

T7

1