Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 261033 1 T7 6 T8 5 T4 11
full_word 599897 1 T9 2 T30 2 T7 5



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 860610 1 T9 2 T30 2 T7 11
auto[TlIntgErrCmd] 112 1 T60 5 T84 11 T128 5
auto[TlIntgErrData] 106 1 T60 9 T84 5 T128 9
auto[TlIntgErrBoth] 102 1 T60 6 T84 4 T128 6



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 509877 1 T9 1 T7 10 T31 1
auto[1] 351053 1 T9 1 T30 2 T7 1



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 207987 1 T7 5 T4 3 T40 3
auto[TlIntgErrNone] partial auto[1] 52753 1 T7 1 T8 5 T4 8
auto[TlIntgErrNone] full_word auto[0] 301744 1 T9 1 T7 5 T31 1
auto[TlIntgErrNone] full_word auto[1] 298126 1 T9 1 T30 2 T8 1
auto[TlIntgErrCmd] partial auto[0] 50 1 T60 1 T84 6 T128 2
auto[TlIntgErrCmd] partial auto[1] 55 1 T60 4 T84 5 T128 2
auto[TlIntgErrCmd] full_word auto[0] 6 1 T128 1 T177 1 T181 1
auto[TlIntgErrCmd] full_word auto[1] 1 1 T182 1 - - - -
auto[TlIntgErrData] partial auto[0] 41 1 T60 4 T84 3 T128 4
auto[TlIntgErrData] partial auto[1] 55 1 T60 4 T84 2 T128 5
auto[TlIntgErrData] full_word auto[0] 5 1 T183 1 T178 1 T184 1
auto[TlIntgErrData] full_word auto[1] 5 1 T60 1 T180 1 T185 1
auto[TlIntgErrBoth] partial auto[0] 38 1 T60 5 T84 2 T128 2
auto[TlIntgErrBoth] partial auto[1] 54 1 T60 1 T84 2 T128 4
auto[TlIntgErrBoth] full_word auto[0] 6 1 T180 1 T181 2 T176 1
auto[TlIntgErrBoth] full_word auto[1] 4 1 T176 1 T183 1 T184 1

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