Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	156667015	16095	0	0
late_debug_enable_rd_A	156667015	5143	0	0
late_debug_enable_regwen_rd_A	156667015	4038	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156667015	16095	0	0
T47	189611	578	0	0
T48	124341	346	0	0
T49	699968	236	0	0
T60	89875	4	0	0
T61	105600	47	0	0
T62	26567	307	0	0
T84	101690	4	0	0
T87	23408	423	0	0
T88	10540	28	0	0
T89	6585	61	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156667015	5143	0	0
T47	189611	367	0	0
T60	89875	66	0	0
T61	105600	40	0	0
T92	9901	1	0	0
T100	18626	157	0	0
T110	321321	234	0	0
T119	21073	24	0	0
T120	40107	4	0	0
T125	819424	99	0	0
T126	7334	4	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156667015	4038	0	0
T47	189611	354	0	0
T60	89875	34	0	0
T61	105600	40	0	0
T100	18626	145	0	0
T110	321321	216	0	0
T119	21073	73	0	0
T120	40107	30	0	0
T125	819424	90	0	0
T126	7334	1	0	0
T127	8439	3	0	0