Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
61644094 |
5547036 |
0 |
0 |
T4 |
0 |
38676 |
0 |
0 |
T5 |
0 |
129978 |
0 |
0 |
T6 |
0 |
91665 |
0 |
0 |
T7 |
54707 |
26186 |
0 |
0 |
T8 |
27713 |
8923 |
0 |
0 |
T11 |
84721 |
0 |
0 |
0 |
T13 |
0 |
308306 |
0 |
0 |
T31 |
189176 |
71880 |
0 |
0 |
T34 |
0 |
3422 |
0 |
0 |
T40 |
0 |
2191 |
0 |
0 |
T44 |
0 |
8667 |
0 |
0 |
T53 |
1617 |
0 |
0 |
0 |
T57 |
10444 |
0 |
0 |
0 |
T58 |
9158 |
0 |
0 |
0 |
T59 |
275763 |
0 |
0 |
0 |
T74 |
49983 |
0 |
0 |
0 |
T75 |
8096 |
0 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
61644094 |
15 |
0 |
0 |
T45 |
48248 |
0 |
0 |
0 |
T51 |
6525 |
14 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T70 |
126851 |
0 |
0 |
0 |
T71 |
86532 |
0 |
0 |
0 |
T72 |
5107 |
0 |
0 |
0 |
T73 |
128179 |
0 |
0 |
0 |
T76 |
71697 |
0 |
0 |
0 |
T77 |
3973 |
0 |
0 |
0 |
T78 |
31259 |
0 |
0 |
0 |
T79 |
3893 |
0 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
61644094 |
0 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
61644094 |
11865 |
0 |
0 |
T1 |
123203 |
20 |
0 |
0 |
T2 |
4467 |
0 |
0 |
0 |
T3 |
4256 |
0 |
0 |
0 |
T7 |
54707 |
0 |
0 |
0 |
T9 |
22971 |
0 |
0 |
0 |
T10 |
5329 |
0 |
0 |
0 |
T12 |
144252 |
68 |
0 |
0 |
T19 |
419920 |
682 |
0 |
0 |
T29 |
0 |
11 |
0 |
0 |
T30 |
2747 |
0 |
0 |
0 |
T32 |
0 |
1395 |
0 |
0 |
T33 |
0 |
22 |
0 |
0 |
T46 |
185729 |
121 |
0 |
0 |
T59 |
0 |
139 |
0 |
0 |
T74 |
0 |
31 |
0 |
0 |
T80 |
0 |
49 |
0 |
0 |