Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9625549 9624211 0 0
selKnown1 68492388 68491050 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9625549 9624211 0 0
T1 35474 35470 0 0
T2 347 343 0 0
T3 326 322 0 0
T4 0 6 0 0
T5 0 22 0 0
T7 1186 1182 0 0
T9 47266 47262 0 0
T10 2447 2443 0 0
T12 15153 15149 0 0
T13 0 8 0 0
T14 0 32 0 0
T19 94865 94861 0 0
T29 0 6 0 0
T30 1641 1637 0 0
T31 0 16 0 0
T32 0 10 0 0
T33 0 12 0 0
T46 30741 30737 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 68492388 68491050 0 0
T1 140948 140945 0 0
T2 4641 4637 0 0
T3 4420 4416 0 0
T4 0 6 0 0
T5 0 12 0 0
T7 55301 55297 0 0
T9 46596 46592 0 0
T10 6553 6549 0 0
T12 151829 151825 0 0
T13 0 8 0 0
T14 0 8 0 0
T19 467353 467350 0 0
T29 0 6 0 0
T30 3568 3564 0 0
T31 0 4 0 0
T32 0 10 0 0
T33 0 12 0 0
T46 201100 201096 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2776443 2776217 0 0
selKnown1 61644094 61643868 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2776443 2776217 0 0
T1 17729 17728 0 0
T2 172 171 0 0
T3 162 161 0 0
T7 592 591 0 0
T9 23617 23616 0 0
T10 1222 1221 0 0
T12 7575 7574 0 0
T19 47431 47430 0 0
T30 819 818 0 0
T46 15369 15368 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 61644094 61643868 0 0
T1 123203 123203 0 0
T2 4467 4466 0 0
T3 4256 4255 0 0
T7 54707 54706 0 0
T9 22971 22970 0 0
T10 5329 5328 0 0
T12 144252 144251 0 0
T19 419920 419920 0 0
T30 2747 2746 0 0
T46 185729 185728 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 796 570 0 0
selKnown1 630 404 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 796 570 0 0
T1 8 7 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 0 3 0 0
T5 0 6 0 0
T7 1 0 0 0
T9 13 12 0 0
T10 1 0 0 0
T12 1 0 0 0
T13 0 4 0 0
T14 0 16 0 0
T19 1 0 0 0
T29 0 3 0 0
T30 1 0 0 0
T31 0 8 0 0
T32 0 5 0 0
T33 0 6 0 0
T46 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 630 404 0 0
T1 8 7 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 0 3 0 0
T5 0 6 0 0
T7 1 0 0 0
T9 4 3 0 0
T10 1 0 0 0
T12 1 0 0 0
T13 0 4 0 0
T14 0 4 0 0
T19 1 0 0 0
T29 0 3 0 0
T30 1 0 0 0
T31 0 2 0 0
T32 0 5 0 0
T33 0 6 0 0
T46 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6846138 6845695 0 0
selKnown1 6845931 6845488 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6846138 6845695 0 0
T1 17729 17728 0 0
T2 173 172 0 0
T3 162 161 0 0
T7 592 591 0 0
T9 23618 23617 0 0
T10 1223 1222 0 0
T12 7576 7575 0 0
T19 47432 47431 0 0
T30 820 819 0 0
T46 15370 15369 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6845931 6845488 0 0
T1 17729 17728 0 0
T2 172 171 0 0
T3 162 161 0 0
T7 592 591 0 0
T9 23617 23616 0 0
T10 1222 1221 0 0
T12 7575 7574 0 0
T19 47431 47430 0 0
T30 819 818 0 0
T46 15369 15368 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2172 1729 0 0
selKnown1 1733 1290 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2172 1729 0 0
T1 8 7 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 0 3 0 0
T5 0 16 0 0
T7 1 0 0 0
T9 18 17 0 0
T10 1 0 0 0
T12 1 0 0 0
T13 0 4 0 0
T14 0 16 0 0
T19 1 0 0 0
T29 0 3 0 0
T30 1 0 0 0
T31 0 8 0 0
T32 0 5 0 0
T33 0 6 0 0
T46 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1733 1290 0 0
T1 8 7 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 0 3 0 0
T5 0 6 0 0
T7 1 0 0 0
T9 4 3 0 0
T10 1 0 0 0
T12 1 0 0 0
T13 0 4 0 0
T14 0 4 0 0
T19 1 0 0 0
T29 0 3 0 0
T30 1 0 0 0
T31 0 2 0 0
T32 0 5 0 0
T33 0 6 0 0
T46 1 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%