SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.12 | 96.97 | 59.57 | 91.58 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 226 | 226 | 0 | 0 |
OutputsKnown_A | 61644094 | 61602121 | 0 | 0 |
gen_no_flops.OutputDelay_A | 61644094 | 61602121 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 226 | 226 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 61644094 | 61602121 | 0 | 0 |
T1 | 123203 | 123151 | 0 | 0 |
T2 | 4467 | 4398 | 0 | 0 |
T3 | 4256 | 4203 | 0 | 0 |
T7 | 54707 | 54649 | 0 | 0 |
T9 | 22971 | 22705 | 0 | 0 |
T10 | 5329 | 5278 | 0 | 0 |
T12 | 144252 | 144182 | 0 | 0 |
T19 | 419920 | 419914 | 0 | 0 |
T30 | 2747 | 2683 | 0 | 0 |
T46 | 185729 | 185673 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 61644094 | 61602121 | 0 | 0 |
T1 | 123203 | 123151 | 0 | 0 |
T2 | 4467 | 4398 | 0 | 0 |
T3 | 4256 | 4203 | 0 | 0 |
T7 | 54707 | 54649 | 0 | 0 |
T9 | 22971 | 22705 | 0 | 0 |
T10 | 5329 | 5278 | 0 | 0 |
T12 | 144252 | 144182 | 0 | 0 |
T19 | 419920 | 419914 | 0 | 0 |
T30 | 2747 | 2683 | 0 | 0 |
T46 | 185729 | 185673 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |