SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
82.11 | 95.67 | 80.41 | 89.75 | 73.08 | 86.17 | 98.42 | 51.29 |
T306 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.684785035 | Jul 12 04:34:32 PM PDT 24 | Jul 12 04:34:40 PM PDT 24 | 1997532281 ps | ||
T100 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2586258917 | Jul 12 04:34:07 PM PDT 24 | Jul 12 04:34:11 PM PDT 24 | 241294081 ps | ||
T307 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.611075613 | Jul 12 04:34:24 PM PDT 24 | Jul 12 04:34:26 PM PDT 24 | 131721380 ps | ||
T90 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1297165753 | Jul 12 04:34:00 PM PDT 24 | Jul 12 04:34:10 PM PDT 24 | 6393378769 ps | ||
T101 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.416259489 | Jul 12 04:34:48 PM PDT 24 | Jul 12 04:34:55 PM PDT 24 | 3949052600 ps | ||
T102 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.392775796 | Jul 12 04:34:38 PM PDT 24 | Jul 12 04:34:45 PM PDT 24 | 69627037 ps | ||
T308 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2853698211 | Jul 12 04:34:04 PM PDT 24 | Jul 12 04:34:05 PM PDT 24 | 486044399 ps | ||
T107 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.236011241 | Jul 12 04:34:37 PM PDT 24 | Jul 12 04:34:53 PM PDT 24 | 1515527844 ps | ||
T91 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3339588922 | Jul 12 04:34:40 PM PDT 24 | Jul 12 04:34:54 PM PDT 24 | 3529707441 ps | ||
T103 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1310270477 | Jul 12 04:34:25 PM PDT 24 | Jul 12 04:35:43 PM PDT 24 | 3385829530 ps | ||
T309 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.702326353 | Jul 12 04:34:26 PM PDT 24 | Jul 12 04:35:24 PM PDT 24 | 18108736288 ps | ||
T92 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1800952391 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:56 PM PDT 24 | 5607107824 ps | ||
T104 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1054926374 | Jul 12 04:34:41 PM PDT 24 | Jul 12 04:34:47 PM PDT 24 | 76396259 ps | ||
T310 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3726289263 | Jul 12 04:34:36 PM PDT 24 | Jul 12 04:34:48 PM PDT 24 | 7150735736 ps | ||
T311 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1092352600 | Jul 12 04:34:44 PM PDT 24 | Jul 12 04:36:43 PM PDT 24 | 85474400167 ps | ||
T312 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2471974964 | Jul 12 04:34:50 PM PDT 24 | Jul 12 04:34:53 PM PDT 24 | 607538590 ps | ||
T313 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3210908088 | Jul 12 04:33:48 PM PDT 24 | Jul 12 04:34:04 PM PDT 24 | 6457027241 ps | ||
T131 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.895860387 | Jul 12 04:34:26 PM PDT 24 | Jul 12 04:34:32 PM PDT 24 | 159795473 ps | ||
T314 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2511528260 | Jul 12 04:34:37 PM PDT 24 | Jul 12 04:34:45 PM PDT 24 | 894958451 ps | ||
T315 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3807683164 | Jul 12 04:33:53 PM PDT 24 | Jul 12 04:33:56 PM PDT 24 | 578990171 ps | ||
T316 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1177764815 | Jul 12 04:34:13 PM PDT 24 | Jul 12 04:34:16 PM PDT 24 | 1442857718 ps | ||
T111 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2335668055 | Jul 12 04:34:44 PM PDT 24 | Jul 12 04:34:51 PM PDT 24 | 406151610 ps | ||
T112 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3206615824 | Jul 12 04:34:06 PM PDT 24 | Jul 12 04:34:13 PM PDT 24 | 262880406 ps | ||
T113 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.589651077 | Jul 12 04:34:37 PM PDT 24 | Jul 12 04:34:46 PM PDT 24 | 214127526 ps | ||
T93 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3888871208 | Jul 12 04:34:32 PM PDT 24 | Jul 12 04:34:42 PM PDT 24 | 2972971503 ps | ||
T128 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3950345078 | Jul 12 04:34:34 PM PDT 24 | Jul 12 04:34:46 PM PDT 24 | 4082220022 ps | ||
T317 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3431908852 | Jul 12 04:34:13 PM PDT 24 | Jul 12 04:34:14 PM PDT 24 | 133633329 ps | ||
T114 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3639167114 | Jul 12 04:34:41 PM PDT 24 | Jul 12 04:34:54 PM PDT 24 | 726660403 ps | ||
T94 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2596919191 | Jul 12 04:33:52 PM PDT 24 | Jul 12 04:33:56 PM PDT 24 | 175657549 ps | ||
T318 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2771003253 | Jul 12 04:33:55 PM PDT 24 | Jul 12 04:33:58 PM PDT 24 | 1139488835 ps | ||
T319 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2461768684 | Jul 12 04:34:29 PM PDT 24 | Jul 12 04:34:47 PM PDT 24 | 5541285256 ps | ||
T320 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2304305442 | Jul 12 04:34:32 PM PDT 24 | Jul 12 04:35:10 PM PDT 24 | 25900723802 ps | ||
T95 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4261114902 | Jul 12 04:34:25 PM PDT 24 | Jul 12 04:34:30 PM PDT 24 | 522375376 ps | ||
T96 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.364379647 | Jul 12 04:34:37 PM PDT 24 | Jul 12 04:34:54 PM PDT 24 | 3287569409 ps | ||
T321 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.844881292 | Jul 12 04:34:26 PM PDT 24 | Jul 12 04:34:31 PM PDT 24 | 36465008 ps | ||
T322 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.600878700 | Jul 12 04:34:35 PM PDT 24 | Jul 12 04:34:43 PM PDT 24 | 1480835409 ps | ||
T105 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3336800985 | Jul 12 04:34:07 PM PDT 24 | Jul 12 04:34:13 PM PDT 24 | 4184151346 ps | ||
T106 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3246573532 | Jul 12 04:34:12 PM PDT 24 | Jul 12 04:34:15 PM PDT 24 | 317817261 ps | ||
T323 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3243518016 | Jul 12 04:34:16 PM PDT 24 | Jul 12 04:35:07 PM PDT 24 | 52294899675 ps | ||
T324 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.284932110 | Jul 12 04:34:33 PM PDT 24 | Jul 12 04:36:18 PM PDT 24 | 36010422910 ps | ||
T119 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3858222061 | Jul 12 04:34:31 PM PDT 24 | Jul 12 04:34:39 PM PDT 24 | 114909001 ps | ||
T129 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.421962071 | Jul 12 04:34:31 PM PDT 24 | Jul 12 04:34:46 PM PDT 24 | 6360926012 ps | ||
T325 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2683678041 | Jul 12 04:34:26 PM PDT 24 | Jul 12 04:34:33 PM PDT 24 | 78829078 ps | ||
T130 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2692643578 | Jul 12 04:34:38 PM PDT 24 | Jul 12 04:34:48 PM PDT 24 | 203766060 ps | ||
T326 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1186369443 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:36 PM PDT 24 | 272134567 ps | ||
T327 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1568309208 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:37 PM PDT 24 | 341943419 ps | ||
T328 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1610944292 | Jul 12 04:34:15 PM PDT 24 | Jul 12 04:34:18 PM PDT 24 | 155392954 ps | ||
T329 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4108460931 | Jul 12 04:34:35 PM PDT 24 | Jul 12 04:34:43 PM PDT 24 | 186667760 ps | ||
T330 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1790207581 | Jul 12 04:34:28 PM PDT 24 | Jul 12 04:34:36 PM PDT 24 | 245734407 ps | ||
T331 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3295725247 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:59 PM PDT 24 | 23003576799 ps | ||
T243 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3186689679 | Jul 12 04:34:28 PM PDT 24 | Jul 12 04:34:36 PM PDT 24 | 240941887 ps | ||
T173 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1014279209 | Jul 12 04:34:27 PM PDT 24 | Jul 12 04:34:50 PM PDT 24 | 4105347193 ps | ||
T109 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3658476548 | Jul 12 04:34:27 PM PDT 24 | Jul 12 04:34:38 PM PDT 24 | 2014225626 ps | ||
T332 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3564522997 | Jul 12 04:34:22 PM PDT 24 | Jul 12 04:34:24 PM PDT 24 | 86057377 ps | ||
T133 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3183742179 | Jul 12 04:34:38 PM PDT 24 | Jul 12 04:34:50 PM PDT 24 | 1922561717 ps | ||
T333 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3206591062 | Jul 12 04:34:05 PM PDT 24 | Jul 12 04:34:46 PM PDT 24 | 15689390497 ps | ||
T334 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3555373473 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:39 PM PDT 24 | 3336613389 ps | ||
T335 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3198121083 | Jul 12 04:34:34 PM PDT 24 | Jul 12 04:34:43 PM PDT 24 | 156150764 ps | ||
T120 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1340913861 | Jul 12 04:34:35 PM PDT 24 | Jul 12 04:34:43 PM PDT 24 | 77030454 ps | ||
T121 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.674828487 | Jul 12 04:34:34 PM PDT 24 | Jul 12 04:34:42 PM PDT 24 | 136612553 ps | ||
T336 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.716733271 | Jul 12 04:34:34 PM PDT 24 | Jul 12 04:34:44 PM PDT 24 | 9966072347 ps | ||
T115 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.815042734 | Jul 12 04:34:15 PM PDT 24 | Jul 12 04:35:31 PM PDT 24 | 4140295043 ps | ||
T337 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3826271959 | Jul 12 04:34:01 PM PDT 24 | Jul 12 04:34:05 PM PDT 24 | 237525844 ps | ||
T116 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4238174156 | Jul 12 04:34:34 PM PDT 24 | Jul 12 04:34:44 PM PDT 24 | 734837590 ps | ||
T338 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2040547097 | Jul 12 04:34:24 PM PDT 24 | Jul 12 04:34:31 PM PDT 24 | 3035160005 ps | ||
T110 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.940188404 | Jul 12 04:34:05 PM PDT 24 | Jul 12 04:34:09 PM PDT 24 | 2413298637 ps | ||
T117 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2982908748 | Jul 12 04:34:41 PM PDT 24 | Jul 12 04:34:48 PM PDT 24 | 134335562 ps | ||
T339 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2364809123 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:35:14 PM PDT 24 | 47114768510 ps | ||
T134 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3897357649 | Jul 12 04:34:35 PM PDT 24 | Jul 12 04:34:45 PM PDT 24 | 515949655 ps | ||
T340 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2856317947 | Jul 12 04:33:57 PM PDT 24 | Jul 12 04:34:13 PM PDT 24 | 14449545140 ps | ||
T341 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2922287864 | Jul 12 04:34:17 PM PDT 24 | Jul 12 04:34:19 PM PDT 24 | 211591676 ps | ||
T342 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.638134730 | Jul 12 04:34:25 PM PDT 24 | Jul 12 04:34:30 PM PDT 24 | 1647164907 ps | ||
T118 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2259930095 | Jul 12 04:34:31 PM PDT 24 | Jul 12 04:34:39 PM PDT 24 | 117856384 ps | ||
T175 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1533830332 | Jul 12 04:34:32 PM PDT 24 | Jul 12 04:34:47 PM PDT 24 | 908796605 ps | ||
T343 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.370854914 | Jul 12 04:33:58 PM PDT 24 | Jul 12 04:34:19 PM PDT 24 | 25871813605 ps | ||
T344 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3742568434 | Jul 12 04:34:29 PM PDT 24 | Jul 12 04:34:35 PM PDT 24 | 158615415 ps | ||
T345 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1253784077 | Jul 12 04:34:01 PM PDT 24 | Jul 12 04:35:50 PM PDT 24 | 39078853208 ps | ||
T346 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.298232253 | Jul 12 04:34:42 PM PDT 24 | Jul 12 04:34:48 PM PDT 24 | 796392688 ps | ||
T347 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2681358034 | Jul 12 04:34:01 PM PDT 24 | Jul 12 04:34:03 PM PDT 24 | 28190524 ps | ||
T135 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3827165449 | Jul 12 04:34:33 PM PDT 24 | Jul 12 04:34:49 PM PDT 24 | 835458189 ps | ||
T174 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.564029615 | Jul 12 04:34:14 PM PDT 24 | Jul 12 04:34:33 PM PDT 24 | 1246924826 ps | ||
T348 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2975132442 | Jul 12 04:34:27 PM PDT 24 | Jul 12 04:34:34 PM PDT 24 | 1654778436 ps | ||
T349 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3788974619 | Jul 12 04:34:36 PM PDT 24 | Jul 12 04:34:43 PM PDT 24 | 438645376 ps | ||
T350 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2454837221 | Jul 12 04:34:19 PM PDT 24 | Jul 12 04:35:28 PM PDT 24 | 9755003457 ps | ||
T351 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1101828926 | Jul 12 04:34:29 PM PDT 24 | Jul 12 04:34:35 PM PDT 24 | 111083711 ps | ||
T352 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.972569471 | Jul 12 04:34:44 PM PDT 24 | Jul 12 04:34:50 PM PDT 24 | 339039717 ps | ||
T125 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2202862140 | Jul 12 04:34:05 PM PDT 24 | Jul 12 04:35:19 PM PDT 24 | 8434979194 ps | ||
T353 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.569146665 | Jul 12 04:34:36 PM PDT 24 | Jul 12 04:34:47 PM PDT 24 | 6941517932 ps | ||
T354 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4215796191 | Jul 12 04:34:08 PM PDT 24 | Jul 12 04:34:09 PM PDT 24 | 177527573 ps | ||
T55 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.66532323 | Jul 12 04:34:24 PM PDT 24 | Jul 12 04:36:39 PM PDT 24 | 47294688899 ps | ||
T172 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.665535006 | Jul 12 04:34:40 PM PDT 24 | Jul 12 04:34:49 PM PDT 24 | 256553579 ps | ||
T355 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2041965372 | Jul 12 04:34:31 PM PDT 24 | Jul 12 04:34:43 PM PDT 24 | 511188217 ps | ||
T356 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3464359513 | Jul 12 04:34:16 PM PDT 24 | Jul 12 04:34:18 PM PDT 24 | 184502040 ps | ||
T136 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.782629554 | Jul 12 04:34:32 PM PDT 24 | Jul 12 04:34:58 PM PDT 24 | 2936798318 ps | ||
T357 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4125057128 | Jul 12 04:34:26 PM PDT 24 | Jul 12 04:36:48 PM PDT 24 | 54959503527 ps | ||
T358 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1154028717 | Jul 12 04:34:40 PM PDT 24 | Jul 12 04:35:16 PM PDT 24 | 12184028091 ps | ||
T180 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.921156978 | Jul 12 04:33:52 PM PDT 24 | Jul 12 04:34:40 PM PDT 24 | 28575703188 ps | ||
T359 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3679982188 | Jul 12 04:34:31 PM PDT 24 | Jul 12 04:34:39 PM PDT 24 | 139026235 ps | ||
T360 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4099142831 | Jul 12 04:33:52 PM PDT 24 | Jul 12 04:33:54 PM PDT 24 | 65139664 ps | ||
T361 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3660500486 | Jul 12 04:34:07 PM PDT 24 | Jul 12 04:34:10 PM PDT 24 | 800634164 ps | ||
T126 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4095441972 | Jul 12 04:33:49 PM PDT 24 | Jul 12 04:35:07 PM PDT 24 | 7412824874 ps | ||
T179 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3305154641 | Jul 12 04:34:27 PM PDT 24 | Jul 12 04:35:01 PM PDT 24 | 5364609463 ps | ||
T362 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2819038591 | Jul 12 04:34:33 PM PDT 24 | Jul 12 04:34:43 PM PDT 24 | 359345232 ps | ||
T181 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3286537182 | Jul 12 04:34:32 PM PDT 24 | Jul 12 04:35:27 PM PDT 24 | 62910938688 ps | ||
T363 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2608685142 | Jul 12 04:34:37 PM PDT 24 | Jul 12 04:34:51 PM PDT 24 | 2578897588 ps | ||
T364 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1797066263 | Jul 12 04:34:16 PM PDT 24 | Jul 12 04:34:30 PM PDT 24 | 4742214151 ps | ||
T365 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3363494459 | Jul 12 04:34:37 PM PDT 24 | Jul 12 04:34:51 PM PDT 24 | 3792731901 ps | ||
T366 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3599234919 | Jul 12 04:34:27 PM PDT 24 | Jul 12 04:34:39 PM PDT 24 | 2831580578 ps | ||
T367 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3925212321 | Jul 12 04:34:31 PM PDT 24 | Jul 12 04:34:39 PM PDT 24 | 79939836 ps | ||
T368 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.121521939 | Jul 12 04:34:26 PM PDT 24 | Jul 12 04:35:32 PM PDT 24 | 44702495618 ps | ||
T369 | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1776441459 | Jul 12 04:34:18 PM PDT 24 | Jul 12 04:35:45 PM PDT 24 | 56696854088 ps | ||
T370 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1246133211 | Jul 12 04:34:26 PM PDT 24 | Jul 12 04:34:40 PM PDT 24 | 777466359 ps | ||
T371 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2658845606 | Jul 12 04:34:37 PM PDT 24 | Jul 12 04:35:01 PM PDT 24 | 3905016550 ps | ||
T372 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3420866365 | Jul 12 04:34:26 PM PDT 24 | Jul 12 04:38:30 PM PDT 24 | 86697847573 ps | ||
T373 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2559099623 | Jul 12 04:34:11 PM PDT 24 | Jul 12 04:35:06 PM PDT 24 | 5724749702 ps | ||
T374 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2014859478 | Jul 12 04:34:25 PM PDT 24 | Jul 12 04:34:29 PM PDT 24 | 78807069 ps | ||
T375 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1186560265 | Jul 12 04:34:31 PM PDT 24 | Jul 12 04:34:45 PM PDT 24 | 5252723964 ps | ||
T122 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3143392935 | Jul 12 04:34:37 PM PDT 24 | Jul 12 04:34:44 PM PDT 24 | 217911787 ps | ||
T376 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.250407208 | Jul 12 04:34:23 PM PDT 24 | Jul 12 04:35:18 PM PDT 24 | 7908162074 ps | ||
T377 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3187814520 | Jul 12 04:34:25 PM PDT 24 | Jul 12 04:34:32 PM PDT 24 | 7095500151 ps | ||
T378 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1505504995 | Jul 12 04:34:02 PM PDT 24 | Jul 12 04:34:03 PM PDT 24 | 80243300 ps | ||
T379 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3735112277 | Jul 12 04:34:38 PM PDT 24 | Jul 12 04:35:48 PM PDT 24 | 32818994748 ps | ||
T380 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2903254564 | Jul 12 04:34:40 PM PDT 24 | Jul 12 04:34:54 PM PDT 24 | 3672898743 ps | ||
T381 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1348536815 | Jul 12 04:34:32 PM PDT 24 | Jul 12 04:34:42 PM PDT 24 | 202028487 ps | ||
T382 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2141902223 | Jul 12 04:34:23 PM PDT 24 | Jul 12 04:34:28 PM PDT 24 | 322915088 ps | ||
T383 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2280983469 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:40 PM PDT 24 | 305965142 ps | ||
T127 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1451066602 | Jul 12 04:34:27 PM PDT 24 | Jul 12 04:34:33 PM PDT 24 | 90366861 ps | ||
T384 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1725882415 | Jul 12 04:34:34 PM PDT 24 | Jul 12 04:34:44 PM PDT 24 | 1913834647 ps | ||
T385 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2566763690 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:41 PM PDT 24 | 3442272283 ps | ||
T386 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2211594989 | Jul 12 04:34:31 PM PDT 24 | Jul 12 04:34:55 PM PDT 24 | 12416252734 ps | ||
T387 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3242058871 | Jul 12 04:34:37 PM PDT 24 | Jul 12 04:35:01 PM PDT 24 | 1392711525 ps | ||
T388 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2077953634 | Jul 12 04:34:19 PM PDT 24 | Jul 12 04:34:24 PM PDT 24 | 232397489 ps | ||
T389 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1985640346 | Jul 12 04:33:54 PM PDT 24 | Jul 12 04:33:55 PM PDT 24 | 53486295 ps | ||
T390 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2776623783 | Jul 12 04:34:31 PM PDT 24 | Jul 12 04:34:39 PM PDT 24 | 283904080 ps | ||
T391 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.4251081300 | Jul 12 04:34:25 PM PDT 24 | Jul 12 04:34:31 PM PDT 24 | 100321593 ps | ||
T392 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2128427615 | Jul 12 04:34:24 PM PDT 24 | Jul 12 04:34:27 PM PDT 24 | 225423166 ps | ||
T393 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.771801153 | Jul 12 04:34:25 PM PDT 24 | Jul 12 04:34:38 PM PDT 24 | 3911136285 ps | ||
T394 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3431687644 | Jul 12 04:34:07 PM PDT 24 | Jul 12 04:34:09 PM PDT 24 | 89507107 ps | ||
T395 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3315562302 | Jul 12 04:34:31 PM PDT 24 | Jul 12 04:34:38 PM PDT 24 | 220845111 ps | ||
T123 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.375748385 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:37 PM PDT 24 | 137957692 ps | ||
T396 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2627332102 | Jul 12 04:33:51 PM PDT 24 | Jul 12 04:33:57 PM PDT 24 | 1587028494 ps | ||
T397 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.864417887 | Jul 12 04:34:02 PM PDT 24 | Jul 12 04:35:22 PM PDT 24 | 13613872434 ps | ||
T398 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.65254939 | Jul 12 04:34:42 PM PDT 24 | Jul 12 04:34:50 PM PDT 24 | 434396527 ps | ||
T399 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3096325242 | Jul 12 04:34:15 PM PDT 24 | Jul 12 04:34:18 PM PDT 24 | 115501000 ps | ||
T400 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.304009430 | Jul 12 04:34:33 PM PDT 24 | Jul 12 04:34:44 PM PDT 24 | 878584819 ps | ||
T401 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3954446039 | Jul 12 04:33:54 PM PDT 24 | Jul 12 04:33:58 PM PDT 24 | 426451356 ps | ||
T402 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.630197940 | Jul 12 04:33:56 PM PDT 24 | Jul 12 04:36:28 PM PDT 24 | 58751634280 ps | ||
T403 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4147783039 | Jul 12 04:33:48 PM PDT 24 | Jul 12 04:33:56 PM PDT 24 | 873390716 ps | ||
T177 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1865749809 | Jul 12 04:34:31 PM PDT 24 | Jul 12 04:34:55 PM PDT 24 | 3324603616 ps | ||
T404 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3248978109 | Jul 12 04:34:25 PM PDT 24 | Jul 12 04:34:30 PM PDT 24 | 48443695 ps | ||
T405 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1023736454 | Jul 12 04:34:25 PM PDT 24 | Jul 12 04:34:31 PM PDT 24 | 102367170 ps | ||
T406 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3978531622 | Jul 12 04:34:26 PM PDT 24 | Jul 12 04:34:37 PM PDT 24 | 221995169 ps | ||
T124 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2898961385 | Jul 12 04:39:42 PM PDT 24 | Jul 12 04:39:50 PM PDT 24 | 87147736 ps | ||
T407 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1674585568 | Jul 12 04:33:50 PM PDT 24 | Jul 12 04:34:03 PM PDT 24 | 2949965940 ps | ||
T408 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3128076480 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:46 PM PDT 24 | 964532119 ps | ||
T182 | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3968294743 | Jul 12 04:34:26 PM PDT 24 | Jul 12 04:36:18 PM PDT 24 | 36108638702 ps | ||
T409 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3273347980 | Jul 12 04:34:25 PM PDT 24 | Jul 12 04:34:30 PM PDT 24 | 494302612 ps | ||
T410 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1520974931 | Jul 12 04:34:25 PM PDT 24 | Jul 12 04:34:29 PM PDT 24 | 812700066 ps | ||
T411 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2126255656 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:38 PM PDT 24 | 460017873 ps | ||
T412 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2040666596 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:36 PM PDT 24 | 464260854 ps | ||
T413 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2493431714 | Jul 12 04:34:33 PM PDT 24 | Jul 12 04:34:42 PM PDT 24 | 176417253 ps | ||
T414 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4598057 | Jul 12 04:34:00 PM PDT 24 | Jul 12 04:34:01 PM PDT 24 | 153512693 ps | ||
T415 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1837062509 | Jul 12 04:34:38 PM PDT 24 | Jul 12 04:34:57 PM PDT 24 | 4406372988 ps | ||
T416 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1591846848 | Jul 12 04:34:14 PM PDT 24 | Jul 12 04:34:19 PM PDT 24 | 2011766878 ps | ||
T417 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3609846240 | Jul 12 04:34:16 PM PDT 24 | Jul 12 04:34:18 PM PDT 24 | 62577704 ps | ||
T418 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2502671336 | Jul 12 04:33:51 PM PDT 24 | Jul 12 04:33:53 PM PDT 24 | 356042848 ps | ||
T419 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1413906511 | Jul 12 04:34:39 PM PDT 24 | Jul 12 04:34:47 PM PDT 24 | 2497594112 ps | ||
T420 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1464285163 | Jul 12 04:34:27 PM PDT 24 | Jul 12 04:34:42 PM PDT 24 | 4711805932 ps | ||
T421 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.783001538 | Jul 12 04:34:23 PM PDT 24 | Jul 12 04:34:51 PM PDT 24 | 25858037766 ps | ||
T422 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3317767090 | Jul 12 04:34:29 PM PDT 24 | Jul 12 04:34:45 PM PDT 24 | 7031133011 ps | ||
T423 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4247076474 | Jul 12 04:34:24 PM PDT 24 | Jul 12 04:34:37 PM PDT 24 | 7838587192 ps | ||
T424 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1684566443 | Jul 12 04:34:22 PM PDT 24 | Jul 12 04:34:24 PM PDT 24 | 137073515 ps | ||
T425 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.670993280 | Jul 12 04:34:15 PM PDT 24 | Jul 12 04:34:19 PM PDT 24 | 3395781258 ps | ||
T178 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.396293586 | Jul 12 04:34:00 PM PDT 24 | Jul 12 04:34:20 PM PDT 24 | 1886822882 ps | ||
T426 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1918932195 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:42 PM PDT 24 | 624742579 ps | ||
T427 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1788054508 | Jul 12 04:34:27 PM PDT 24 | Jul 12 04:34:34 PM PDT 24 | 396876304 ps | ||
T428 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4231349308 | Jul 12 04:33:51 PM PDT 24 | Jul 12 04:33:53 PM PDT 24 | 315233496 ps | ||
T429 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3694924262 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:39 PM PDT 24 | 2023674078 ps | ||
T430 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.518049879 | Jul 12 04:34:16 PM PDT 24 | Jul 12 04:34:19 PM PDT 24 | 176430835 ps | ||
T431 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.150883146 | Jul 12 04:34:25 PM PDT 24 | Jul 12 04:34:32 PM PDT 24 | 2868176745 ps | ||
T432 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3423776668 | Jul 12 04:34:27 PM PDT 24 | Jul 12 04:35:51 PM PDT 24 | 49675340232 ps | ||
T433 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1509436077 | Jul 12 04:34:24 PM PDT 24 | Jul 12 04:34:30 PM PDT 24 | 219272415 ps | ||
T434 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2121174727 | Jul 12 04:34:36 PM PDT 24 | Jul 12 04:34:49 PM PDT 24 | 1706256046 ps | ||
T435 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2503845784 | Jul 12 04:34:31 PM PDT 24 | Jul 12 04:34:44 PM PDT 24 | 4195262934 ps | ||
T436 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.4133793706 | Jul 12 04:34:49 PM PDT 24 | Jul 12 04:34:55 PM PDT 24 | 823681780 ps | ||
T437 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.115929487 | Jul 12 04:34:30 PM PDT 24 | Jul 12 04:34:44 PM PDT 24 | 649025488 ps | ||
T438 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1836214617 | Jul 12 04:34:26 PM PDT 24 | Jul 12 04:37:01 PM PDT 24 | 55393456280 ps | ||
T176 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3527681803 | Jul 12 04:34:41 PM PDT 24 | Jul 12 04:35:10 PM PDT 24 | 6365775326 ps | ||
T439 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4126099993 | Jul 12 04:34:20 PM PDT 24 | Jul 12 04:34:28 PM PDT 24 | 2331580442 ps | ||
T440 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3605189534 | Jul 12 04:34:32 PM PDT 24 | Jul 12 04:34:38 PM PDT 24 | 695042671 ps | ||
T441 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1430849170 | Jul 12 04:34:27 PM PDT 24 | Jul 12 04:34:31 PM PDT 24 | 243334840 ps | ||
T442 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2436670913 | Jul 12 04:34:34 PM PDT 24 | Jul 12 04:34:42 PM PDT 24 | 232680303 ps | ||
T443 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1410725724 | Jul 12 04:34:37 PM PDT 24 | Jul 12 04:35:00 PM PDT 24 | 17659451103 ps | ||
T444 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2722577636 | Jul 12 04:34:32 PM PDT 24 | Jul 12 04:34:51 PM PDT 24 | 1604354228 ps | ||
T445 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2033361865 | Jul 12 04:34:46 PM PDT 24 | Jul 12 04:34:54 PM PDT 24 | 714652796 ps | ||
T446 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.290272962 | Jul 12 04:34:38 PM PDT 24 | Jul 12 04:34:46 PM PDT 24 | 151771944 ps | ||
T447 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1446613278 | Jul 12 04:34:19 PM PDT 24 | Jul 12 04:34:26 PM PDT 24 | 3849377310 ps | ||
T448 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2939686433 | Jul 12 04:34:41 PM PDT 24 | Jul 12 04:34:49 PM PDT 24 | 1843420398 ps |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.4085281583 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 1397025222 ps |
CPU time | 1.95 seconds |
Started | Jul 12 06:00:18 PM PDT 24 |
Finished | Jul 12 06:00:23 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-fdba4223-1ac8-43c3-8708-e2cbed51cf3c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085281583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.4085281583 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.212321286 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 3922476637 ps |
CPU time | 5.18 seconds |
Started | Jul 12 06:00:01 PM PDT 24 |
Finished | Jul 12 06:00:08 PM PDT 24 |
Peak memory | 213728 kb |
Host | smart-49253e67-91fe-4b64-b71b-5a4bcfdd5855 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=212321286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.212321286 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3885416820 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 53570286615 ps |
CPU time | 49.9 seconds |
Started | Jul 12 04:33:58 PM PDT 24 |
Finished | Jul 12 04:34:48 PM PDT 24 |
Peak memory | 221044 kb |
Host | smart-62e009e8-c00f-4aa1-b041-b5712bf48f3d |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885416820 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3885416820 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.2917906177 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 15089964349 ps |
CPU time | 12.89 seconds |
Started | Jul 12 06:00:20 PM PDT 24 |
Finished | Jul 12 06:00:36 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-66bacb87-05e0-4762-a765-ad663a870349 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917906177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2917906177 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3767289012 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 4232194381 ps |
CPU time | 18.67 seconds |
Started | Jul 12 04:34:34 PM PDT 24 |
Finished | Jul 12 04:34:59 PM PDT 24 |
Peak memory | 213040 kb |
Host | smart-d55f118f-d9ef-495f-b717-10aa799fcb8c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767289012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3 767289012 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2014341658 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 13818547178 ps |
CPU time | 76.8 seconds |
Started | Jul 12 04:33:54 PM PDT 24 |
Finished | Jul 12 04:35:11 PM PDT 24 |
Peak memory | 213016 kb |
Host | smart-5068dc49-f77b-469f-bdb8-9967749b977f |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014341658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.2014341658 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2474849164 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 24492008367 ps |
CPU time | 62.34 seconds |
Started | Jul 12 06:00:13 PM PDT 24 |
Finished | Jul 12 06:01:16 PM PDT 24 |
Peak memory | 218524 kb |
Host | smart-06969893-c7e0-4cfb-8896-5d82b48ed89e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2474849164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2474849164 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.2592047033 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 194623260 ps |
CPU time | 0.77 seconds |
Started | Jul 12 06:00:23 PM PDT 24 |
Finished | Jul 12 06:00:27 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-14307287-44e4-4803-b36a-3488b9eb843e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592047033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2592047033 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/30.rv_dm_stress_all.2807057866 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 1962598739 ps |
CPU time | 6.54 seconds |
Started | Jul 12 06:00:15 PM PDT 24 |
Finished | Jul 12 06:00:23 PM PDT 24 |
Peak memory | 204772 kb |
Host | smart-c30b4ebd-e123-4db4-8a07-4447c6bc6dd8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807057866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.2807057866 |
Directory | /workspace/30.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.1283210732 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 510949930 ps |
CPU time | 1.05 seconds |
Started | Jul 12 05:59:33 PM PDT 24 |
Finished | Jul 12 05:59:39 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-fe5f5de2-1ed0-4998-a9c4-f0b99cffa639 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283210732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1283210732 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.4097384062 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 128936403 ps |
CPU time | 1.14 seconds |
Started | Jul 12 05:59:46 PM PDT 24 |
Finished | Jul 12 05:59:48 PM PDT 24 |
Peak memory | 215352 kb |
Host | smart-caf39f06-50b5-41e0-ad47-0900c2a07d38 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097384062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.4097384062 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1541419275 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 4998517318 ps |
CPU time | 66.06 seconds |
Started | Jul 12 04:34:27 PM PDT 24 |
Finished | Jul 12 04:35:36 PM PDT 24 |
Peak memory | 213032 kb |
Host | smart-f8e5f9dd-9985-4e18-9320-ea2afb8374bc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541419275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1541419275 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/default/24.rv_dm_stress_all.625861291 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 7994314769 ps |
CPU time | 6.4 seconds |
Started | Jul 12 06:00:14 PM PDT 24 |
Finished | Jul 12 06:00:22 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-9238e240-0b4b-451e-bbdc-a7df8072b3c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625861291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.625861291 |
Directory | /workspace/24.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.3883941030 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 3981791575 ps |
CPU time | 11.85 seconds |
Started | Jul 12 05:59:35 PM PDT 24 |
Finished | Jul 12 05:59:51 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-ba846eb6-2e5f-41b9-a669-da6761b820bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883941030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3883941030 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.424571344 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 2773468353 ps |
CPU time | 8.48 seconds |
Started | Jul 12 06:00:00 PM PDT 24 |
Finished | Jul 12 06:00:11 PM PDT 24 |
Peak memory | 213720 kb |
Host | smart-051c4ffa-6055-43fd-b5bc-c3ce2124f983 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=424571344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.424571344 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.815042734 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 4140295043 ps |
CPU time | 74.85 seconds |
Started | Jul 12 04:34:15 PM PDT 24 |
Finished | Jul 12 04:35:31 PM PDT 24 |
Peak memory | 213012 kb |
Host | smart-fad82d42-d24b-4a32-ab20-e8bd6aa67ac1 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815042734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 3.rv_dm_csr_aliasing.815042734 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.266906706 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 2247663857 ps |
CPU time | 6.92 seconds |
Started | Jul 12 05:59:50 PM PDT 24 |
Finished | Jul 12 05:59:58 PM PDT 24 |
Peak memory | 228840 kb |
Host | smart-73811b37-77de-4f99-9743-6aa64d594030 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266906706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.266906706 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2378471658 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 1846922268 ps |
CPU time | 5.77 seconds |
Started | Jul 12 05:59:53 PM PDT 24 |
Finished | Jul 12 06:00:00 PM PDT 24 |
Peak memory | 205672 kb |
Host | smart-c4f87066-814e-4841-b4c3-0f97837cdc50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2378471658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2378471658 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_busy.2428849451 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 1148667819 ps |
CPU time | 1.68 seconds |
Started | Jul 12 05:59:36 PM PDT 24 |
Finished | Jul 12 05:59:40 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-05f59d33-69de-4762-9625-a5ff1c4b65c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428849451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2428849451 |
Directory | /workspace/0.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.3604260212 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 573586581 ps |
CPU time | 0.94 seconds |
Started | Jul 12 05:59:43 PM PDT 24 |
Finished | Jul 12 05:59:45 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-d5f5d017-aeed-4eb4-933f-e4cfa6013f6a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3604260212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3604260212 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/18.rv_dm_stress_all.2810578698 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 3761837212 ps |
CPU time | 3.96 seconds |
Started | Jul 12 06:00:11 PM PDT 24 |
Finished | Jul 12 06:00:16 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-6beac5d8-70dd-405e-a548-f0ced1a6b999 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810578698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2810578698 |
Directory | /workspace/18.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.2880225094 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 147712769 ps |
CPU time | 0.87 seconds |
Started | Jul 12 05:59:46 PM PDT 24 |
Finished | Jul 12 05:59:48 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-a944230d-5c5d-4a69-9926-83ef92e4f867 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880225094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2880225094 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_dmi_failed_op.3122462240 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 149791084 ps |
CPU time | 0.78 seconds |
Started | Jul 12 05:59:38 PM PDT 24 |
Finished | Jul 12 05:59:42 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-845bf5a2-bc32-407a-8889-51edcb72ae6c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3122462240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.3122462240 |
Directory | /workspace/0.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1310270477 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 3385829530 ps |
CPU time | 75.84 seconds |
Started | Jul 12 04:34:25 PM PDT 24 |
Finished | Jul 12 04:35:43 PM PDT 24 |
Peak memory | 212968 kb |
Host | smart-0e742532-0edc-49ef-9474-0fc8ccfe3888 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310270477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.1310270477 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.782629554 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 2936798318 ps |
CPU time | 19.88 seconds |
Started | Jul 12 04:34:32 PM PDT 24 |
Finished | Jul 12 04:34:58 PM PDT 24 |
Peak memory | 213008 kb |
Host | smart-43174705-6636-4466-a7de-022cb2f0d272 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782629554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.782629554 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1109267528 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 3671760245 ps |
CPU time | 3.33 seconds |
Started | Jul 12 06:00:08 PM PDT 24 |
Finished | Jul 12 06:00:13 PM PDT 24 |
Peak memory | 213652 kb |
Host | smart-59b24cd2-9f47-4209-8c3d-10c15c8bd2af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1109267528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1109267528 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1061747210 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 351155696 ps |
CPU time | 1.04 seconds |
Started | Jul 12 05:59:44 PM PDT 24 |
Finished | Jul 12 05:59:46 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-57a6cf80-2fdc-4ade-8758-5c8701ae73e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1061747210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1061747210 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.999497012 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 20960175385 ps |
CPU time | 33.68 seconds |
Started | Jul 12 06:00:05 PM PDT 24 |
Finished | Jul 12 06:00:40 PM PDT 24 |
Peak memory | 221688 kb |
Host | smart-0ace4964-74de-4354-80df-86b958ed3e64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999497012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.999497012 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2535077562 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 7358059116 ps |
CPU time | 20.65 seconds |
Started | Jul 12 06:00:08 PM PDT 24 |
Finished | Jul 12 06:00:30 PM PDT 24 |
Peak memory | 215036 kb |
Host | smart-c2f4c141-7ba7-4645-9087-675dd0859b38 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2535077562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2535077562 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2312893462 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 6858879295 ps |
CPU time | 5.74 seconds |
Started | Jul 12 05:59:34 PM PDT 24 |
Finished | Jul 12 05:59:44 PM PDT 24 |
Peak memory | 213596 kb |
Host | smart-790d8fd9-70be-458d-8fa1-72247d62b559 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2312893462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2312893462 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all.3553487200 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 6385529135 ps |
CPU time | 2.6 seconds |
Started | Jul 12 05:59:37 PM PDT 24 |
Finished | Jul 12 05:59:43 PM PDT 24 |
Peak memory | 213548 kb |
Host | smart-476d9ea6-70ce-4e80-8fb9-c77f0ed2342b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553487200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3553487200 |
Directory | /workspace/0.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.1994935349 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 3813275997 ps |
CPU time | 6.88 seconds |
Started | Jul 12 06:00:15 PM PDT 24 |
Finished | Jul 12 06:00:23 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-d83335f3-6136-41fa-be22-48978f0ee79c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994935349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1994935349 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.2253943784 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 509209857 ps |
CPU time | 2.12 seconds |
Started | Jul 12 05:59:43 PM PDT 24 |
Finished | Jul 12 05:59:46 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-da4d8c8e-e613-46af-bf65-e17b1bc72f5c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2253943784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2253943784 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3807683164 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 578990171 ps |
CPU time | 2.08 seconds |
Started | Jul 12 04:33:53 PM PDT 24 |
Finished | Jul 12 04:33:56 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-11a90711-9b4e-4ec9-be2f-905ce46b825f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807683164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.3807683164 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.940188404 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 2413298637 ps |
CPU time | 3.72 seconds |
Started | Jul 12 04:34:05 PM PDT 24 |
Finished | Jul 12 04:34:09 PM PDT 24 |
Peak memory | 204752 kb |
Host | smart-d4c1f9dd-0f54-4477-83f4-69e2894f3528 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940188404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr _hw_reset.940188404 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3206615824 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 262880406 ps |
CPU time | 6.14 seconds |
Started | Jul 12 04:34:06 PM PDT 24 |
Finished | Jul 12 04:34:13 PM PDT 24 |
Peak memory | 204744 kb |
Host | smart-4c5d005c-6753-45a1-a29d-2804fe9f9489 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206615824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.3206615824 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1533830332 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 908796605 ps |
CPU time | 8.79 seconds |
Started | Jul 12 04:34:32 PM PDT 24 |
Finished | Jul 12 04:34:47 PM PDT 24 |
Peak memory | 212900 kb |
Host | smart-9859a923-1286-4d58-9b90-82d3be40e6fe |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533830332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1 533830332 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1374178769 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 4404449548 ps |
CPU time | 5.62 seconds |
Started | Jul 12 06:00:01 PM PDT 24 |
Finished | Jul 12 06:00:09 PM PDT 24 |
Peak memory | 213748 kb |
Host | smart-f9a256b5-7900-4521-b58a-9028be828d89 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1374178769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1374178769 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.1896852893 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 7450344862 ps |
CPU time | 10.03 seconds |
Started | Jul 12 06:00:05 PM PDT 24 |
Finished | Jul 12 06:00:16 PM PDT 24 |
Peak memory | 213652 kb |
Host | smart-66fdd955-6500-4bcf-b8ec-7273c1cd5d03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1896852893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1896852893 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.73818126 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 8842072698 ps |
CPU time | 12.35 seconds |
Started | Jul 12 06:00:07 PM PDT 24 |
Finished | Jul 12 06:00:21 PM PDT 24 |
Peak memory | 205400 kb |
Host | smart-cbef951e-2f03-4356-a401-530a6bfb83e9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73818126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.73818126 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1619877638 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 4937540280 ps |
CPU time | 7.48 seconds |
Started | Jul 12 05:59:59 PM PDT 24 |
Finished | Jul 12 06:00:08 PM PDT 24 |
Peak memory | 213716 kb |
Host | smart-8996ce74-d869-49a8-9f7a-698c2484214f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619877638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1619877638 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1554644719 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 1817498006 ps |
CPU time | 1.83 seconds |
Started | Jul 12 05:59:35 PM PDT 24 |
Finished | Jul 12 05:59:40 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-e5a47dcd-febc-47a8-8dbf-c45e2cc05235 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1554644719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1554644719 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2158046985 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 8375463736 ps |
CPU time | 6.32 seconds |
Started | Jul 12 06:00:09 PM PDT 24 |
Finished | Jul 12 06:00:17 PM PDT 24 |
Peak memory | 213632 kb |
Host | smart-b997739b-f116-41e3-92de-c220c799b8d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2158046985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2158046985 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3143392935 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 217911787 ps |
CPU time | 1.61 seconds |
Started | Jul 12 04:34:37 PM PDT 24 |
Finished | Jul 12 04:34:44 PM PDT 24 |
Peak memory | 212884 kb |
Host | smart-06ae9f02-33ac-42a3-8a90-84c79dc172f7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143392935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3143392935 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1359890753 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 1040059752 ps |
CPU time | 0.79 seconds |
Started | Jul 12 05:59:31 PM PDT 24 |
Finished | Jul 12 05:59:38 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-7a75b5ac-a4cb-4c34-baed-fbc7c5be88ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1359890753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1359890753 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1203603146 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 305746307 ps |
CPU time | 1.48 seconds |
Started | Jul 12 05:59:38 PM PDT 24 |
Finished | Jul 12 05:59:42 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-8f88ad6b-1950-48da-b0ea-4ac2fb097405 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1203603146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1203603146 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.3061867786 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 14468248541 ps |
CPU time | 39.85 seconds |
Started | Jul 12 05:59:31 PM PDT 24 |
Finished | Jul 12 06:00:16 PM PDT 24 |
Peak memory | 215704 kb |
Host | smart-e0e70090-f94b-4671-ac11-76ae270e43ae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3061867786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3061867786 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.3370527202 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 5904475708 ps |
CPU time | 15.74 seconds |
Started | Jul 12 05:59:33 PM PDT 24 |
Finished | Jul 12 05:59:54 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-3b60c0d8-31e4-4b13-b7d8-457e78ca81a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370527202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3370527202 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2507973297 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 216985479 ps |
CPU time | 0.73 seconds |
Started | Jul 12 05:59:46 PM PDT 24 |
Finished | Jul 12 05:59:47 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-ec930957-b230-47c5-809e-3a4976d20826 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507973297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2507973297 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3461461233 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 7391502587 ps |
CPU time | 5.3 seconds |
Started | Jul 12 06:00:00 PM PDT 24 |
Finished | Jul 12 06:00:08 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-b43818b6-9493-40a6-a89c-f6cc690589a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3461461233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3461461233 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_stress_all.534889386 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 13013805119 ps |
CPU time | 18.52 seconds |
Started | Jul 12 06:00:00 PM PDT 24 |
Finished | Jul 12 06:00:21 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-a5b2455b-2fdb-4228-aab0-636e839e2fd6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534889386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.534889386 |
Directory | /workspace/12.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.1903880220 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 1561477820 ps |
CPU time | 2.19 seconds |
Started | Jul 12 06:00:07 PM PDT 24 |
Finished | Jul 12 06:00:11 PM PDT 24 |
Peak memory | 213652 kb |
Host | smart-d3dda00c-329d-4abd-9e85-0798960b611c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1903880220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1903880220 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.3594371085 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 2599101661 ps |
CPU time | 8.15 seconds |
Started | Jul 12 06:00:08 PM PDT 24 |
Finished | Jul 12 06:00:18 PM PDT 24 |
Peak memory | 205552 kb |
Host | smart-64f85511-edfb-4f0a-a93f-da775f06415a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594371085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3594371085 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3113127441 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 5245608491 ps |
CPU time | 4.73 seconds |
Started | Jul 12 06:00:10 PM PDT 24 |
Finished | Jul 12 06:00:16 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-29c80bab-b0f9-494b-aae5-bb768cbd5afb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3113127441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3113127441 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.1404857867 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 12682218746 ps |
CPU time | 10.3 seconds |
Started | Jul 12 05:59:51 PM PDT 24 |
Finished | Jul 12 06:00:02 PM PDT 24 |
Peak memory | 213664 kb |
Host | smart-4c96a373-63cd-42e1-bd4f-610ccb1c8826 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1404857867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1404857867 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.2991307899 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 2806871197 ps |
CPU time | 8.3 seconds |
Started | Jul 12 06:00:18 PM PDT 24 |
Finished | Jul 12 06:00:28 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-df14b2ee-1669-438c-bb9d-99d6f2326b8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991307899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2991307899 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all.430408529 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 905197225 ps |
CPU time | 2.52 seconds |
Started | Jul 12 05:59:52 PM PDT 24 |
Finished | Jul 12 05:59:56 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-2070d362-db1e-43ed-b3ca-e2669cf6dcab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430408529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.430408529 |
Directory | /workspace/4.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.2315615387 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 9940067995 ps |
CPU time | 9.92 seconds |
Started | Jul 12 06:00:18 PM PDT 24 |
Finished | Jul 12 06:00:31 PM PDT 24 |
Peak memory | 205436 kb |
Host | smart-b8064f59-c40f-487b-91ee-44d67273719f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315615387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2315615387 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3607084858 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 2043124844 ps |
CPU time | 4.2 seconds |
Started | Jul 12 06:00:10 PM PDT 24 |
Finished | Jul 12 06:00:16 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-2d884929-3d39-4e69-8720-8724a373660e |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3607084858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.3607084858 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.1640087460 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 2020719399 ps |
CPU time | 2.04 seconds |
Started | Jul 12 05:59:59 PM PDT 24 |
Finished | Jul 12 06:00:04 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-00a5dbed-6b58-4525-b0d7-2e9ad33fea77 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640087460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1640087460 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4095441972 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 7412824874 ps |
CPU time | 77.7 seconds |
Started | Jul 12 04:33:49 PM PDT 24 |
Finished | Jul 12 04:35:07 PM PDT 24 |
Peak memory | 213024 kb |
Host | smart-5d66cbaa-c608-4e4d-900e-b44dd99f3dd4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095441972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.4095441972 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3954446039 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 426451356 ps |
CPU time | 2.57 seconds |
Started | Jul 12 04:33:54 PM PDT 24 |
Finished | Jul 12 04:33:58 PM PDT 24 |
Peak memory | 212984 kb |
Host | smart-934f6a9a-9b08-4490-8c29-ea43e89fa936 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954446039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3954446039 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1297165753 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 6393378769 ps |
CPU time | 9.15 seconds |
Started | Jul 12 04:34:00 PM PDT 24 |
Finished | Jul 12 04:34:10 PM PDT 24 |
Peak memory | 221200 kb |
Host | smart-95924aed-6441-41bf-9a2b-8963092b67f2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297165753 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1297165753 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2898961385 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 87147736 ps |
CPU time | 2.18 seconds |
Started | Jul 12 04:39:42 PM PDT 24 |
Finished | Jul 12 04:39:50 PM PDT 24 |
Peak memory | 213084 kb |
Host | smart-cebcfeb0-a8c0-4d53-87ae-5495fbef1983 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898961385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2898961385 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.630197940 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 58751634280 ps |
CPU time | 151.67 seconds |
Started | Jul 12 04:33:56 PM PDT 24 |
Finished | Jul 12 04:36:28 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-3092a95c-0167-48ca-b770-c1c45f3bc48c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630197940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr _aliasing.630197940 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3210908088 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 6457027241 ps |
CPU time | 15.38 seconds |
Started | Jul 12 04:33:48 PM PDT 24 |
Finished | Jul 12 04:34:04 PM PDT 24 |
Peak memory | 204748 kb |
Host | smart-763cad75-8cb3-449a-abeb-1e5805510745 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210908088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.3210908088 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2627332102 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 1587028494 ps |
CPU time | 5.34 seconds |
Started | Jul 12 04:33:51 PM PDT 24 |
Finished | Jul 12 04:33:57 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-56c8e7e2-6fb3-46d9-8822-891c42baf98b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627332102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.2627332102 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2771003253 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 1139488835 ps |
CPU time | 2.52 seconds |
Started | Jul 12 04:33:55 PM PDT 24 |
Finished | Jul 12 04:33:58 PM PDT 24 |
Peak memory | 204648 kb |
Host | smart-0ffaa268-3dd1-4930-a85c-4bf5aa017541 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771003253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2 771003253 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.355768262 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 3474958840 ps |
CPU time | 10.49 seconds |
Started | Jul 12 04:33:53 PM PDT 24 |
Finished | Jul 12 04:34:04 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-e42f3f34-6367-4c1c-b482-e71ea6dd308e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355768262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr _bit_bash.355768262 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4231349308 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 315233496 ps |
CPU time | 0.92 seconds |
Started | Jul 12 04:33:51 PM PDT 24 |
Finished | Jul 12 04:33:53 PM PDT 24 |
Peak memory | 204424 kb |
Host | smart-921cf478-bd1a-4c99-bad9-510c84926220 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231349308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.4231349308 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2502671336 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 356042848 ps |
CPU time | 1.18 seconds |
Started | Jul 12 04:33:51 PM PDT 24 |
Finished | Jul 12 04:33:53 PM PDT 24 |
Peak memory | 204424 kb |
Host | smart-ea776ae5-6c95-44eb-abaf-26399ec68983 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502671336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2 502671336 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4099142831 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 65139664 ps |
CPU time | 0.83 seconds |
Started | Jul 12 04:33:52 PM PDT 24 |
Finished | Jul 12 04:33:54 PM PDT 24 |
Peak memory | 204396 kb |
Host | smart-a8553670-c76e-413f-b5bc-5caf34fd3df0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099142831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.4099142831 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1985640346 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 53486295 ps |
CPU time | 0.67 seconds |
Started | Jul 12 04:33:54 PM PDT 24 |
Finished | Jul 12 04:33:55 PM PDT 24 |
Peak memory | 204440 kb |
Host | smart-e8624fe6-ec62-4546-8d53-bc69f40f65e5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985640346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1985640346 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4147783039 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 873390716 ps |
CPU time | 7.03 seconds |
Started | Jul 12 04:33:48 PM PDT 24 |
Finished | Jul 12 04:33:56 PM PDT 24 |
Peak memory | 204640 kb |
Host | smart-8b5b0f1b-1b01-4196-9b37-21ad8390bebf |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147783039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.4147783039 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.921156978 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 28575703188 ps |
CPU time | 46.85 seconds |
Started | Jul 12 04:33:52 PM PDT 24 |
Finished | Jul 12 04:34:40 PM PDT 24 |
Peak memory | 215044 kb |
Host | smart-2e9d5530-697f-40fb-a261-edb6f257d973 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921156978 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.921156978 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2596919191 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 175657549 ps |
CPU time | 3.64 seconds |
Started | Jul 12 04:33:52 PM PDT 24 |
Finished | Jul 12 04:33:56 PM PDT 24 |
Peak memory | 213020 kb |
Host | smart-9330e77f-0415-437a-b468-c717fe411f6d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596919191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2596919191 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1674585568 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 2949965940 ps |
CPU time | 12.1 seconds |
Started | Jul 12 04:33:50 PM PDT 24 |
Finished | Jul 12 04:34:03 PM PDT 24 |
Peak memory | 213028 kb |
Host | smart-8ee9c61d-bb96-499d-b59b-2c4d15cf49e8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674585568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1674585568 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.864417887 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 13613872434 ps |
CPU time | 78.53 seconds |
Started | Jul 12 04:34:02 PM PDT 24 |
Finished | Jul 12 04:35:22 PM PDT 24 |
Peak memory | 212216 kb |
Host | smart-3e74e6e2-5b29-437f-a530-a98cb965c319 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864417887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 1.rv_dm_csr_aliasing.864417887 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2559099623 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 5724749702 ps |
CPU time | 54.08 seconds |
Started | Jul 12 04:34:11 PM PDT 24 |
Finished | Jul 12 04:35:06 PM PDT 24 |
Peak memory | 212980 kb |
Host | smart-3c4349e4-c6f0-4ba0-860f-cbaf1142e412 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559099623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2559099623 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2586258917 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 241294081 ps |
CPU time | 2.83 seconds |
Started | Jul 12 04:34:07 PM PDT 24 |
Finished | Jul 12 04:34:11 PM PDT 24 |
Peak memory | 213028 kb |
Host | smart-94c8f8b7-fddd-442d-b71b-304066198b71 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586258917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2586258917 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3336800985 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 4184151346 ps |
CPU time | 5.07 seconds |
Started | Jul 12 04:34:07 PM PDT 24 |
Finished | Jul 12 04:34:13 PM PDT 24 |
Peak memory | 218772 kb |
Host | smart-28ac5f6b-3329-4e01-8674-b07f681ea602 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336800985 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3336800985 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3431687644 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 89507107 ps |
CPU time | 1.55 seconds |
Started | Jul 12 04:34:07 PM PDT 24 |
Finished | Jul 12 04:34:09 PM PDT 24 |
Peak memory | 212964 kb |
Host | smart-76eeae51-6758-4bfa-a50d-e1424768accd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431687644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3431687644 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2856317947 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 14449545140 ps |
CPU time | 15.28 seconds |
Started | Jul 12 04:33:57 PM PDT 24 |
Finished | Jul 12 04:34:13 PM PDT 24 |
Peak memory | 203868 kb |
Host | smart-3486cfce-a007-413e-9b78-7fbaabba2d19 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856317947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.2856317947 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1253784077 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 39078853208 ps |
CPU time | 108.49 seconds |
Started | Jul 12 04:34:01 PM PDT 24 |
Finished | Jul 12 04:35:50 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-1bf47088-64f3-4a04-bb14-05ef27a69bfa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253784077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.1253784077 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2767417297 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 2126799362 ps |
CPU time | 3.74 seconds |
Started | Jul 12 04:34:00 PM PDT 24 |
Finished | Jul 12 04:34:05 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-68287412-a9f3-4672-b8df-bd5bf62aa094 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767417297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2 767417297 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1962575734 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 444152583 ps |
CPU time | 1.34 seconds |
Started | Jul 12 04:34:14 PM PDT 24 |
Finished | Jul 12 04:34:16 PM PDT 24 |
Peak memory | 204424 kb |
Host | smart-3ec1f2cc-4dee-4d5d-ab1c-89fadc2c5357 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962575734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.1962575734 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.370854914 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 25871813605 ps |
CPU time | 19.38 seconds |
Started | Jul 12 04:33:58 PM PDT 24 |
Finished | Jul 12 04:34:19 PM PDT 24 |
Peak memory | 204760 kb |
Host | smart-fcf3d645-0e2b-43c3-a03c-d95ac5524c1d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370854914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr _bit_bash.370854914 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1177764815 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 1442857718 ps |
CPU time | 1.95 seconds |
Started | Jul 12 04:34:13 PM PDT 24 |
Finished | Jul 12 04:34:16 PM PDT 24 |
Peak memory | 204420 kb |
Host | smart-64ce3243-d184-4aa5-9183-d27adca015bb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177764815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.1177764815 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4598057 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 153512693 ps |
CPU time | 0.77 seconds |
Started | Jul 12 04:34:00 PM PDT 24 |
Finished | Jul 12 04:34:01 PM PDT 24 |
Peak memory | 204444 kb |
Host | smart-6934af42-3b02-4191-9e3f-ea885bf54f55 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4598057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4598057 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2681358034 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 28190524 ps |
CPU time | 0.73 seconds |
Started | Jul 12 04:34:01 PM PDT 24 |
Finished | Jul 12 04:34:03 PM PDT 24 |
Peak memory | 204376 kb |
Host | smart-c98eb6a1-cddf-456d-bbb7-6467aecb8dd1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681358034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.2681358034 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1505504995 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 80243300 ps |
CPU time | 0.7 seconds |
Started | Jul 12 04:34:02 PM PDT 24 |
Finished | Jul 12 04:34:03 PM PDT 24 |
Peak memory | 204432 kb |
Host | smart-4042adf6-2627-463f-97e4-3508a18b097c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505504995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1505504995 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3826271959 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 237525844 ps |
CPU time | 3.47 seconds |
Started | Jul 12 04:34:01 PM PDT 24 |
Finished | Jul 12 04:34:05 PM PDT 24 |
Peak memory | 212984 kb |
Host | smart-243ca400-4424-4026-9060-64b1a2228df6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826271959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3826271959 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.396293586 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 1886822882 ps |
CPU time | 19.32 seconds |
Started | Jul 12 04:34:00 PM PDT 24 |
Finished | Jul 12 04:34:20 PM PDT 24 |
Peak memory | 212868 kb |
Host | smart-eb41ac29-9cd5-4bf6-a071-f77eeebf1ac3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396293586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.396293586 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3694924262 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 2023674078 ps |
CPU time | 3.36 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:39 PM PDT 24 |
Peak memory | 220520 kb |
Host | smart-f7cc60af-73e3-4c47-b764-f87609906893 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694924262 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3694924262 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1340913861 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 77030454 ps |
CPU time | 2.28 seconds |
Started | Jul 12 04:34:35 PM PDT 24 |
Finished | Jul 12 04:34:43 PM PDT 24 |
Peak memory | 212900 kb |
Host | smart-fcaa950e-0cde-46a9-8181-f40a0cc8377c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340913861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1340913861 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2461768684 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 5541285256 ps |
CPU time | 12.27 seconds |
Started | Jul 12 04:34:29 PM PDT 24 |
Finished | Jul 12 04:34:47 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-f2801918-e107-44be-8fae-d0bbb63c1c27 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461768684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.2461768684 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1837062509 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 4406372988 ps |
CPU time | 13.34 seconds |
Started | Jul 12 04:34:38 PM PDT 24 |
Finished | Jul 12 04:34:57 PM PDT 24 |
Peak memory | 204700 kb |
Host | smart-f0f3d207-8aee-4d41-a62d-2038b8c26297 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837062509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 1837062509 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1568309208 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 341943419 ps |
CPU time | 1.59 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:37 PM PDT 24 |
Peak memory | 204444 kb |
Host | smart-2ce5394b-65c5-4a1a-ac58-7e56f4223337 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568309208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 1568309208 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.421962071 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 6360926012 ps |
CPU time | 9.06 seconds |
Started | Jul 12 04:34:31 PM PDT 24 |
Finished | Jul 12 04:34:46 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-4ee83aa2-9bac-44a1-ba7a-18653b6cd767 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421962071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_ csr_outstanding.421962071 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3198121083 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 156150764 ps |
CPU time | 2.64 seconds |
Started | Jul 12 04:34:34 PM PDT 24 |
Finished | Jul 12 04:34:43 PM PDT 24 |
Peak memory | 213084 kb |
Host | smart-15886932-d792-479d-9ea8-f5fde35cc80e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198121083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3198121083 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.115929487 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 649025488 ps |
CPU time | 8.31 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:44 PM PDT 24 |
Peak memory | 212924 kb |
Host | smart-58af723d-8af2-476d-ab88-664d83985071 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115929487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.115929487 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.168920314 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 4584273832 ps |
CPU time | 6.27 seconds |
Started | Jul 12 04:34:29 PM PDT 24 |
Finished | Jul 12 04:34:41 PM PDT 24 |
Peak memory | 221072 kb |
Host | smart-7d2430b8-6e2a-4673-b957-d20f2d17777b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168920314 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.168920314 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.392775796 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 69627037 ps |
CPU time | 1.49 seconds |
Started | Jul 12 04:34:38 PM PDT 24 |
Finished | Jul 12 04:34:45 PM PDT 24 |
Peak memory | 212880 kb |
Host | smart-52538878-6917-4c5f-a7a5-0ec29ac74bc8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392775796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.392775796 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2211594989 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 12416252734 ps |
CPU time | 17.19 seconds |
Started | Jul 12 04:34:31 PM PDT 24 |
Finished | Jul 12 04:34:55 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-cf56f035-127f-46a5-80a7-c43d15f24b24 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211594989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .rv_dm_jtag_dmi_csr_bit_bash.2211594989 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3726289263 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 7150735736 ps |
CPU time | 5.35 seconds |
Started | Jul 12 04:34:36 PM PDT 24 |
Finished | Jul 12 04:34:48 PM PDT 24 |
Peak memory | 204748 kb |
Host | smart-92aa4020-42eb-4873-8361-ce364e0db0a0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726289263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 3726289263 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3244746745 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 192630030 ps |
CPU time | 1.18 seconds |
Started | Jul 12 04:34:33 PM PDT 24 |
Finished | Jul 12 04:34:41 PM PDT 24 |
Peak memory | 204432 kb |
Host | smart-413daf61-4df6-4541-9e9e-d9f13fc04d7f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244746745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 3244746745 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4238174156 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 734837590 ps |
CPU time | 4.37 seconds |
Started | Jul 12 04:34:34 PM PDT 24 |
Finished | Jul 12 04:34:44 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-6f0cb8a1-91ec-4316-ab64-1f90777fafe4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238174156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.4238174156 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.290272962 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 151771944 ps |
CPU time | 2.61 seconds |
Started | Jul 12 04:34:38 PM PDT 24 |
Finished | Jul 12 04:34:46 PM PDT 24 |
Peak memory | 213084 kb |
Host | smart-7aefffc5-4fdf-4cac-9c64-4459994b2f62 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290272962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.290272962 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2503845784 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 4195262934 ps |
CPU time | 7.04 seconds |
Started | Jul 12 04:34:31 PM PDT 24 |
Finished | Jul 12 04:34:44 PM PDT 24 |
Peak memory | 220808 kb |
Host | smart-5dab60b9-20f7-4755-a3fb-041b13abf171 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503845784 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2503845784 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2364809123 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 47114768510 ps |
CPU time | 38.43 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:35:14 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-b7dd3932-8066-4a06-aba3-08de6358cd21 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364809123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .rv_dm_jtag_dmi_csr_bit_bash.2364809123 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.569146665 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 6941517932 ps |
CPU time | 5.8 seconds |
Started | Jul 12 04:34:36 PM PDT 24 |
Finished | Jul 12 04:34:47 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-f2a33a03-203c-451a-aba7-a8ea64222797 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569146665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.569146665 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3605189534 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 695042671 ps |
CPU time | 0.84 seconds |
Started | Jul 12 04:34:32 PM PDT 24 |
Finished | Jul 12 04:34:38 PM PDT 24 |
Peak memory | 204384 kb |
Host | smart-94d89347-541c-4cf8-852e-73d9030efc78 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605189534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 3605189534 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3827165449 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 835458189 ps |
CPU time | 9.47 seconds |
Started | Jul 12 04:34:33 PM PDT 24 |
Finished | Jul 12 04:34:49 PM PDT 24 |
Peak memory | 204272 kb |
Host | smart-cb75d97b-d3d2-4eed-b215-e9653d76c380 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827165449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.3827165449 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3679982188 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 139026235 ps |
CPU time | 2.88 seconds |
Started | Jul 12 04:34:31 PM PDT 24 |
Finished | Jul 12 04:34:39 PM PDT 24 |
Peak memory | 213020 kb |
Host | smart-de62a1dd-4c50-4142-a34a-4ecf6ce4a0f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679982188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3679982188 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3242058871 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 1392711525 ps |
CPU time | 18.36 seconds |
Started | Jul 12 04:34:37 PM PDT 24 |
Finished | Jul 12 04:35:01 PM PDT 24 |
Peak memory | 212444 kb |
Host | smart-db82b7e7-72df-4ffe-8e38-164f110174b4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242058871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3 242058871 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3317767090 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 7031133011 ps |
CPU time | 10.96 seconds |
Started | Jul 12 04:34:29 PM PDT 24 |
Finished | Jul 12 04:34:45 PM PDT 24 |
Peak memory | 219608 kb |
Host | smart-cdf591e8-0815-4469-97c5-9f3788f422c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317767090 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3317767090 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3925212321 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 79939836 ps |
CPU time | 1.61 seconds |
Started | Jul 12 04:34:31 PM PDT 24 |
Finished | Jul 12 04:34:39 PM PDT 24 |
Peak memory | 212868 kb |
Host | smart-9b79431c-9a21-4350-8068-18b5ef0f0012 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925212321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3925212321 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.284932110 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 36010422910 ps |
CPU time | 98.52 seconds |
Started | Jul 12 04:34:33 PM PDT 24 |
Finished | Jul 12 04:36:18 PM PDT 24 |
Peak memory | 204364 kb |
Host | smart-8057a15a-288b-4ea7-a484-f4b86e621c60 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284932110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. rv_dm_jtag_dmi_csr_bit_bash.284932110 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2608685142 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 2578897588 ps |
CPU time | 8.2 seconds |
Started | Jul 12 04:34:37 PM PDT 24 |
Finished | Jul 12 04:34:51 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-8693b779-d23a-4bf4-9853-b01e4ba05788 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608685142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 2608685142 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3315562302 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 220845111 ps |
CPU time | 0.94 seconds |
Started | Jul 12 04:34:31 PM PDT 24 |
Finished | Jul 12 04:34:38 PM PDT 24 |
Peak memory | 204416 kb |
Host | smart-024d84ac-cf81-4f43-9292-e0e7a6a4d2e2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315562302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 3315562302 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3897357649 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 515949655 ps |
CPU time | 4.08 seconds |
Started | Jul 12 04:34:35 PM PDT 24 |
Finished | Jul 12 04:34:45 PM PDT 24 |
Peak memory | 204760 kb |
Host | smart-6811faee-9830-4cc7-b616-06939ea0b7c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897357649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.3897357649 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2041965372 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 511188217 ps |
CPU time | 6.05 seconds |
Started | Jul 12 04:34:31 PM PDT 24 |
Finished | Jul 12 04:34:43 PM PDT 24 |
Peak memory | 213500 kb |
Host | smart-2579dea1-8426-43a3-8561-7d39dc3e83a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041965372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2041965372 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1413906511 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 2497594112 ps |
CPU time | 2.67 seconds |
Started | Jul 12 04:34:39 PM PDT 24 |
Finished | Jul 12 04:34:47 PM PDT 24 |
Peak memory | 216880 kb |
Host | smart-d8515900-43af-4a8b-a207-188ddf1f26da |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413906511 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1413906511 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3858222061 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 114909001 ps |
CPU time | 1.43 seconds |
Started | Jul 12 04:34:31 PM PDT 24 |
Finished | Jul 12 04:34:39 PM PDT 24 |
Peak memory | 212880 kb |
Host | smart-91c4c1c0-3e67-43ba-8674-8e6583a1e8e8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858222061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3858222061 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3735112277 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 32818994748 ps |
CPU time | 65.22 seconds |
Started | Jul 12 04:34:38 PM PDT 24 |
Finished | Jul 12 04:35:48 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-de1e67c1-ab4c-47a2-9d8f-8751eb69f76e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735112277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .rv_dm_jtag_dmi_csr_bit_bash.3735112277 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1186560265 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 5252723964 ps |
CPU time | 8.2 seconds |
Started | Jul 12 04:34:31 PM PDT 24 |
Finished | Jul 12 04:34:45 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-944327cc-068f-4c2a-bb16-9d44326b3ed8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186560265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 1186560265 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3788974619 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 438645376 ps |
CPU time | 1.09 seconds |
Started | Jul 12 04:34:36 PM PDT 24 |
Finished | Jul 12 04:34:43 PM PDT 24 |
Peak memory | 204392 kb |
Host | smart-4b38c99f-9a26-4a16-96f5-943926d00a0b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788974619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 3788974619 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2692643578 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 203766060 ps |
CPU time | 3.73 seconds |
Started | Jul 12 04:34:38 PM PDT 24 |
Finished | Jul 12 04:34:48 PM PDT 24 |
Peak memory | 204756 kb |
Host | smart-f1c6787a-5a9a-49d7-a0d9-04f0a0372688 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692643578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.2692643578 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2776623783 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 283904080 ps |
CPU time | 2.16 seconds |
Started | Jul 12 04:34:31 PM PDT 24 |
Finished | Jul 12 04:34:39 PM PDT 24 |
Peak memory | 213012 kb |
Host | smart-c92cc793-630e-473c-aeb5-9ed3f92fe7ac |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776623783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2776623783 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.236011241 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 1515527844 ps |
CPU time | 10.53 seconds |
Started | Jul 12 04:34:37 PM PDT 24 |
Finished | Jul 12 04:34:53 PM PDT 24 |
Peak memory | 212900 kb |
Host | smart-ded760ff-a2a1-46de-90f6-88d336d8e179 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236011241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.236011241 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2939686433 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 1843420398 ps |
CPU time | 4.24 seconds |
Started | Jul 12 04:34:41 PM PDT 24 |
Finished | Jul 12 04:34:49 PM PDT 24 |
Peak memory | 217932 kb |
Host | smart-af176959-ef27-4bf3-b172-c98b8a529420 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939686433 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2939686433 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.674828487 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 136612553 ps |
CPU time | 1.47 seconds |
Started | Jul 12 04:34:34 PM PDT 24 |
Finished | Jul 12 04:34:42 PM PDT 24 |
Peak memory | 212920 kb |
Host | smart-7ffbd2f2-f8b3-4c4d-8239-57a07ab053e4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674828487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.674828487 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1410725724 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 17659451103 ps |
CPU time | 17.16 seconds |
Started | Jul 12 04:34:37 PM PDT 24 |
Finished | Jul 12 04:35:00 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-a9e5672a-ea1f-4ae4-8c2f-5dd573bc6156 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410725724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.1410725724 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1725882415 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 1913834647 ps |
CPU time | 3.78 seconds |
Started | Jul 12 04:34:34 PM PDT 24 |
Finished | Jul 12 04:34:44 PM PDT 24 |
Peak memory | 204636 kb |
Host | smart-e9e370a3-74c7-40ef-9e81-8168b63358d5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725882415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 1725882415 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.298232253 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 796392688 ps |
CPU time | 1.24 seconds |
Started | Jul 12 04:34:42 PM PDT 24 |
Finished | Jul 12 04:34:48 PM PDT 24 |
Peak memory | 204440 kb |
Host | smart-3c5286f7-9fbd-44fa-95b9-09b72ab5cd79 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298232253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.298232253 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3950345078 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 4082220022 ps |
CPU time | 5.72 seconds |
Started | Jul 12 04:34:34 PM PDT 24 |
Finished | Jul 12 04:34:46 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-05fba790-40aa-4b7c-9081-79f4e35f14ca |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950345078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.3950345078 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4108460931 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 186667760 ps |
CPU time | 2.12 seconds |
Started | Jul 12 04:34:35 PM PDT 24 |
Finished | Jul 12 04:34:43 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-e75da660-3896-461e-ad2b-8065dc12cb72 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108460931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.4108460931 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2658845606 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 3905016550 ps |
CPU time | 19.02 seconds |
Started | Jul 12 04:34:37 PM PDT 24 |
Finished | Jul 12 04:35:01 PM PDT 24 |
Peak memory | 212980 kb |
Host | smart-1b43cce9-1beb-42db-bc9d-80e65e7ed385 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658845606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2 658845606 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3339588922 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 3529707441 ps |
CPU time | 9.71 seconds |
Started | Jul 12 04:34:40 PM PDT 24 |
Finished | Jul 12 04:34:54 PM PDT 24 |
Peak memory | 220112 kb |
Host | smart-7218d5c4-0cb3-448b-8028-db8160a7fe1d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339588922 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3339588922 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2493431714 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 176417253 ps |
CPU time | 2.33 seconds |
Started | Jul 12 04:34:33 PM PDT 24 |
Finished | Jul 12 04:34:42 PM PDT 24 |
Peak memory | 212940 kb |
Host | smart-eff8309d-7a39-467a-9669-e5cfefca9d9d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493431714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2493431714 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.716733271 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 9966072347 ps |
CPU time | 3.96 seconds |
Started | Jul 12 04:34:34 PM PDT 24 |
Finished | Jul 12 04:34:44 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-e9b405f7-7e5b-41bc-a293-ed6ed0dc9351 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716733271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. rv_dm_jtag_dmi_csr_bit_bash.716733271 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.316976558 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 7381866606 ps |
CPU time | 20.37 seconds |
Started | Jul 12 04:34:36 PM PDT 24 |
Finished | Jul 12 04:35:02 PM PDT 24 |
Peak memory | 204756 kb |
Host | smart-f1aacdfe-1e9a-40c7-a605-3f9fcb8ad500 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316976558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.316976558 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2511528260 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 894958451 ps |
CPU time | 2.81 seconds |
Started | Jul 12 04:34:37 PM PDT 24 |
Finished | Jul 12 04:34:45 PM PDT 24 |
Peak memory | 203948 kb |
Host | smart-7e31475a-0471-4d0a-9280-816e0715d445 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511528260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 2511528260 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2121174727 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 1706256046 ps |
CPU time | 7.69 seconds |
Started | Jul 12 04:34:36 PM PDT 24 |
Finished | Jul 12 04:34:49 PM PDT 24 |
Peak memory | 204648 kb |
Host | smart-ecc4950c-2313-45c9-b2c2-68e0172d7d12 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121174727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.2121174727 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2033361865 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 714652796 ps |
CPU time | 4.22 seconds |
Started | Jul 12 04:34:46 PM PDT 24 |
Finished | Jul 12 04:34:54 PM PDT 24 |
Peak memory | 212988 kb |
Host | smart-f8a94da5-70a0-4be0-ba74-dd9205df74c3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033361865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2033361865 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2722577636 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 1604354228 ps |
CPU time | 12.12 seconds |
Started | Jul 12 04:34:32 PM PDT 24 |
Finished | Jul 12 04:34:51 PM PDT 24 |
Peak memory | 212924 kb |
Host | smart-daf7d8f7-2349-427d-8b93-51ee2aab5938 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722577636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2 722577636 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2903254564 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 3672898743 ps |
CPU time | 9.38 seconds |
Started | Jul 12 04:34:40 PM PDT 24 |
Finished | Jul 12 04:34:54 PM PDT 24 |
Peak memory | 221160 kb |
Host | smart-745f1c5f-9d89-474e-b73f-b1e50dc0039f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903254564 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2903254564 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1054926374 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 76396259 ps |
CPU time | 1.53 seconds |
Started | Jul 12 04:34:41 PM PDT 24 |
Finished | Jul 12 04:34:47 PM PDT 24 |
Peak memory | 212784 kb |
Host | smart-c3dff40c-fab8-462a-95d9-0abc5617aec7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054926374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1054926374 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3770513932 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 4422388868 ps |
CPU time | 5.67 seconds |
Started | Jul 12 04:34:33 PM PDT 24 |
Finished | Jul 12 04:34:44 PM PDT 24 |
Peak memory | 204656 kb |
Host | smart-50701f69-db7c-4c41-8864-5bb2bfd850b0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770513932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.3770513932 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1154028717 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 12184028091 ps |
CPU time | 31.44 seconds |
Started | Jul 12 04:34:40 PM PDT 24 |
Finished | Jul 12 04:35:16 PM PDT 24 |
Peak memory | 204656 kb |
Host | smart-4c272c97-b166-48d6-9637-912f71feb5ed |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154028717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 1154028717 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2471974964 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 607538590 ps |
CPU time | 1.43 seconds |
Started | Jul 12 04:34:50 PM PDT 24 |
Finished | Jul 12 04:34:53 PM PDT 24 |
Peak memory | 204496 kb |
Host | smart-e2c6d066-0fb0-4fc0-9566-827882de3a2b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471974964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 2471974964 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3639167114 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 726660403 ps |
CPU time | 8.29 seconds |
Started | Jul 12 04:34:41 PM PDT 24 |
Finished | Jul 12 04:34:54 PM PDT 24 |
Peak memory | 204652 kb |
Host | smart-5e43a3e8-4088-4e96-9e19-2be2954574c2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639167114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.3639167114 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.65254939 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 434396527 ps |
CPU time | 2.78 seconds |
Started | Jul 12 04:34:42 PM PDT 24 |
Finished | Jul 12 04:34:50 PM PDT 24 |
Peak memory | 213088 kb |
Host | smart-ca5485a9-2ba0-48c2-aa7d-a8f3a6d5ca9d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65254939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.65254939 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.4133793706 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 823681780 ps |
CPU time | 3.81 seconds |
Started | Jul 12 04:34:49 PM PDT 24 |
Finished | Jul 12 04:34:55 PM PDT 24 |
Peak memory | 221200 kb |
Host | smart-01cab2c8-4018-42e7-bf04-2f58e60efe65 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133793706 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.4133793706 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2335668055 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 406151610 ps |
CPU time | 2.73 seconds |
Started | Jul 12 04:34:44 PM PDT 24 |
Finished | Jul 12 04:34:51 PM PDT 24 |
Peak memory | 213208 kb |
Host | smart-421ce4b9-4956-4df3-84da-c7e282319541 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335668055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2335668055 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.684785035 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 1997532281 ps |
CPU time | 2.28 seconds |
Started | Jul 12 04:34:32 PM PDT 24 |
Finished | Jul 12 04:34:40 PM PDT 24 |
Peak memory | 204656 kb |
Host | smart-7ef37372-c3ab-40e4-aa70-61b5bb26bc0a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684785035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. rv_dm_jtag_dmi_csr_bit_bash.684785035 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.600878700 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 1480835409 ps |
CPU time | 1.92 seconds |
Started | Jul 12 04:34:35 PM PDT 24 |
Finished | Jul 12 04:34:43 PM PDT 24 |
Peak memory | 204624 kb |
Host | smart-73e05022-c08d-4bdd-8f93-275c78b7581f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600878700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.600878700 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2436670913 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 232680303 ps |
CPU time | 0.83 seconds |
Started | Jul 12 04:34:34 PM PDT 24 |
Finished | Jul 12 04:34:42 PM PDT 24 |
Peak memory | 204440 kb |
Host | smart-7ef6df7b-15e3-41ac-b640-7e030bea96ae |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436670913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 2436670913 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.416259489 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 3949052600 ps |
CPU time | 4.18 seconds |
Started | Jul 12 04:34:48 PM PDT 24 |
Finished | Jul 12 04:34:55 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-554b4444-0f27-4257-9cbc-0917c3ad9f3c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416259489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_ csr_outstanding.416259489 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2819038591 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 359345232 ps |
CPU time | 3.36 seconds |
Started | Jul 12 04:34:33 PM PDT 24 |
Finished | Jul 12 04:34:43 PM PDT 24 |
Peak memory | 213008 kb |
Host | smart-83fae8bb-14f8-4179-b205-d4c5cedfdbe3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819038591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2819038591 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3527681803 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 6365775326 ps |
CPU time | 23.89 seconds |
Started | Jul 12 04:34:41 PM PDT 24 |
Finished | Jul 12 04:35:10 PM PDT 24 |
Peak memory | 212972 kb |
Host | smart-68ef9fbf-a97f-482d-8412-a5083ef389ba |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527681803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3 527681803 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3363494459 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 3792731901 ps |
CPU time | 7.78 seconds |
Started | Jul 12 04:34:37 PM PDT 24 |
Finished | Jul 12 04:34:51 PM PDT 24 |
Peak memory | 218260 kb |
Host | smart-efff4be0-d34f-478b-9581-7895b92d0f3c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363494459 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3363494459 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2982908748 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 134335562 ps |
CPU time | 2.09 seconds |
Started | Jul 12 04:34:41 PM PDT 24 |
Finished | Jul 12 04:34:48 PM PDT 24 |
Peak memory | 212804 kb |
Host | smart-73b5603e-1f3d-4c6e-8c31-8d166438a131 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982908748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2982908748 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1092352600 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 85474400167 ps |
CPU time | 114.58 seconds |
Started | Jul 12 04:34:44 PM PDT 24 |
Finished | Jul 12 04:36:43 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-70197bd8-cc23-4d3c-bea1-49fad4a22423 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092352600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .rv_dm_jtag_dmi_csr_bit_bash.1092352600 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2625453644 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 1549756419 ps |
CPU time | 2.02 seconds |
Started | Jul 12 04:34:39 PM PDT 24 |
Finished | Jul 12 04:34:46 PM PDT 24 |
Peak memory | 204584 kb |
Host | smart-4a37e2bf-5ae4-4fc9-9cd2-1f0c7e8b7366 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625453644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 2625453644 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.972569471 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 339039717 ps |
CPU time | 1.58 seconds |
Started | Jul 12 04:34:44 PM PDT 24 |
Finished | Jul 12 04:34:50 PM PDT 24 |
Peak memory | 204388 kb |
Host | smart-9a80154f-b15d-4d42-ae63-0a05d8963fef |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972569471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.972569471 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.589651077 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 214127526 ps |
CPU time | 3.84 seconds |
Started | Jul 12 04:34:37 PM PDT 24 |
Finished | Jul 12 04:34:46 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-7bd88d63-b4d3-40f9-80ba-0b71581f2f2c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589651077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_ csr_outstanding.589651077 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.665535006 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 256553579 ps |
CPU time | 4.31 seconds |
Started | Jul 12 04:34:40 PM PDT 24 |
Finished | Jul 12 04:34:49 PM PDT 24 |
Peak memory | 213060 kb |
Host | smart-b9e26da2-52ae-45ab-842c-6be447e2fcf4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665535006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.665535006 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.364379647 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 3287569409 ps |
CPU time | 11.08 seconds |
Started | Jul 12 04:34:37 PM PDT 24 |
Finished | Jul 12 04:34:54 PM PDT 24 |
Peak memory | 213020 kb |
Host | smart-e5ec1e13-fb93-4ab5-b5af-d97078e8f69f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364379647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.364379647 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2202862140 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 8434979194 ps |
CPU time | 72.97 seconds |
Started | Jul 12 04:34:05 PM PDT 24 |
Finished | Jul 12 04:35:19 PM PDT 24 |
Peak memory | 204800 kb |
Host | smart-5c941594-63a2-4a3e-b8d4-23fb14ab3833 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202862140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.2202862140 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2454837221 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 9755003457 ps |
CPU time | 67.97 seconds |
Started | Jul 12 04:34:19 PM PDT 24 |
Finished | Jul 12 04:35:28 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-141ce579-5f81-47bf-aae9-4cac063f122b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454837221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2454837221 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.518049879 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 176430835 ps |
CPU time | 1.71 seconds |
Started | Jul 12 04:34:16 PM PDT 24 |
Finished | Jul 12 04:34:19 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-7d7d4f5b-c845-4e09-a04c-7f1f849496b6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518049879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.518049879 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3096325242 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 115501000 ps |
CPU time | 2.17 seconds |
Started | Jul 12 04:34:15 PM PDT 24 |
Finished | Jul 12 04:34:18 PM PDT 24 |
Peak memory | 216100 kb |
Host | smart-1e34e8cf-c9d9-4c5e-af1d-d175dd016145 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096325242 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3096325242 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1610944292 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 155392954 ps |
CPU time | 1.75 seconds |
Started | Jul 12 04:34:15 PM PDT 24 |
Finished | Jul 12 04:34:18 PM PDT 24 |
Peak memory | 212924 kb |
Host | smart-120af0aa-0821-47ec-ace8-f245cd48491e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610944292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1610944292 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3243518016 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 52294899675 ps |
CPU time | 49.35 seconds |
Started | Jul 12 04:34:16 PM PDT 24 |
Finished | Jul 12 04:35:07 PM PDT 24 |
Peak memory | 204468 kb |
Host | smart-d568f38d-aaf0-4c1c-90a0-2f782c7ce688 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243518016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.3243518016 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1446613278 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 3849377310 ps |
CPU time | 5.68 seconds |
Started | Jul 12 04:34:19 PM PDT 24 |
Finished | Jul 12 04:34:26 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-7416045e-35a8-4dc3-90fb-2e277a3ef52b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446613278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. rv_dm_jtag_dmi_csr_bit_bash.1446613278 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3975188466 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 3676548513 ps |
CPU time | 11.15 seconds |
Started | Jul 12 04:34:19 PM PDT 24 |
Finished | Jul 12 04:34:31 PM PDT 24 |
Peak memory | 204760 kb |
Host | smart-beec8847-7d35-4133-8b35-7b800bbc5ac9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975188466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.3975188466 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4126099993 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 2331580442 ps |
CPU time | 6.92 seconds |
Started | Jul 12 04:34:20 PM PDT 24 |
Finished | Jul 12 04:34:28 PM PDT 24 |
Peak memory | 204660 kb |
Host | smart-55e8aa3f-429c-4bce-972c-eab559218516 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126099993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.4 126099993 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3660500486 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 800634164 ps |
CPU time | 2.69 seconds |
Started | Jul 12 04:34:07 PM PDT 24 |
Finished | Jul 12 04:34:10 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-a52f9c94-1d1e-4640-a2f1-036628ab15d7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660500486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.3660500486 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3206591062 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 15689390497 ps |
CPU time | 40.2 seconds |
Started | Jul 12 04:34:05 PM PDT 24 |
Finished | Jul 12 04:34:46 PM PDT 24 |
Peak memory | 204632 kb |
Host | smart-5ad273ac-e9f5-4d2a-8888-1e189cb7cac5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206591062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.3206591062 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4215796191 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 177527573 ps |
CPU time | 0.73 seconds |
Started | Jul 12 04:34:08 PM PDT 24 |
Finished | Jul 12 04:34:09 PM PDT 24 |
Peak memory | 204376 kb |
Host | smart-95e682ff-54a8-4485-ae77-94dee3ce9f83 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215796191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.4215796191 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2853698211 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 486044399 ps |
CPU time | 0.96 seconds |
Started | Jul 12 04:34:04 PM PDT 24 |
Finished | Jul 12 04:34:05 PM PDT 24 |
Peak memory | 204376 kb |
Host | smart-40eef6fa-0826-492e-961d-d09769eba064 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853698211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2 853698211 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3609846240 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 62577704 ps |
CPU time | 0.71 seconds |
Started | Jul 12 04:34:16 PM PDT 24 |
Finished | Jul 12 04:34:18 PM PDT 24 |
Peak memory | 204180 kb |
Host | smart-3c068e52-83d8-45c2-a8ef-0079073f0f9a |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609846240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.3609846240 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3431908852 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 133633329 ps |
CPU time | 0.7 seconds |
Started | Jul 12 04:34:13 PM PDT 24 |
Finished | Jul 12 04:34:14 PM PDT 24 |
Peak memory | 204396 kb |
Host | smart-88163156-c414-4d9e-a2a0-4aca2e8284d5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431908852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3431908852 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2077953634 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 232397489 ps |
CPU time | 3.7 seconds |
Started | Jul 12 04:34:19 PM PDT 24 |
Finished | Jul 12 04:34:24 PM PDT 24 |
Peak memory | 204748 kb |
Host | smart-9e8c001b-9708-4583-9f4c-58016333d5aa |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077953634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.2077953634 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1776441459 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 56696854088 ps |
CPU time | 86.23 seconds |
Started | Jul 12 04:34:18 PM PDT 24 |
Finished | Jul 12 04:35:45 PM PDT 24 |
Peak memory | 221292 kb |
Host | smart-a98f5e6b-6298-42ac-9df8-9cecc74b71d4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776441459 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.1776441459 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3246573532 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 317817261 ps |
CPU time | 2.6 seconds |
Started | Jul 12 04:34:12 PM PDT 24 |
Finished | Jul 12 04:34:15 PM PDT 24 |
Peak memory | 213032 kb |
Host | smart-68e90696-9d3f-4b51-aed7-537258640e2d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246573532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3246573532 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.564029615 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 1246924826 ps |
CPU time | 17.99 seconds |
Started | Jul 12 04:34:14 PM PDT 24 |
Finished | Jul 12 04:34:33 PM PDT 24 |
Peak memory | 212884 kb |
Host | smart-05f5f34d-23b5-4a3c-a1a9-20cc7cd4ad2a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564029615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.564029615 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1023736454 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 102367170 ps |
CPU time | 1.78 seconds |
Started | Jul 12 04:34:25 PM PDT 24 |
Finished | Jul 12 04:34:31 PM PDT 24 |
Peak memory | 212964 kb |
Host | smart-45a055c5-857a-4d1c-87c7-d0b5aee9c7ea |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023736454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1023736454 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2566763690 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 3442272283 ps |
CPU time | 4.92 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:41 PM PDT 24 |
Peak memory | 219076 kb |
Host | smart-f43cb69c-215b-4319-93f8-e3597143ff71 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566763690 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2566763690 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.747543184 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 462256177 ps |
CPU time | 2.52 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:34:31 PM PDT 24 |
Peak memory | 212964 kb |
Host | smart-ed81d97a-37f7-465b-a378-ab82c30b133a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747543184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.747543184 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4125057128 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 54959503527 ps |
CPU time | 137.95 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:36:48 PM PDT 24 |
Peak memory | 204652 kb |
Host | smart-ab1eee28-c6f7-4336-9be4-5f16d479571d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125057128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.4125057128 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.702326353 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 18108736288 ps |
CPU time | 54.32 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:35:24 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-6646108d-39f1-460d-a95f-a5857d4eaeed |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702326353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r v_dm_jtag_dmi_csr_bit_bash.702326353 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.670993280 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 3395781258 ps |
CPU time | 2.6 seconds |
Started | Jul 12 04:34:15 PM PDT 24 |
Finished | Jul 12 04:34:19 PM PDT 24 |
Peak memory | 204640 kb |
Host | smart-b423e506-30ac-4fd0-bd43-099c6679267a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670993280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr _hw_reset.670993280 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1591846848 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 2011766878 ps |
CPU time | 4.26 seconds |
Started | Jul 12 04:34:14 PM PDT 24 |
Finished | Jul 12 04:34:19 PM PDT 24 |
Peak memory | 204612 kb |
Host | smart-648fdbcc-edbd-4980-8a72-1571430b5306 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591846848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1 591846848 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2966038288 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 310142704 ps |
CPU time | 1.05 seconds |
Started | Jul 12 04:34:18 PM PDT 24 |
Finished | Jul 12 04:34:20 PM PDT 24 |
Peak memory | 204424 kb |
Host | smart-6f0e26e0-b759-4c9a-8d9a-3d766b176caf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966038288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.2966038288 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1797066263 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 4742214151 ps |
CPU time | 13.61 seconds |
Started | Jul 12 04:34:16 PM PDT 24 |
Finished | Jul 12 04:34:30 PM PDT 24 |
Peak memory | 204764 kb |
Host | smart-e69210c8-04ae-4f56-b6b5-680f75bf2e8a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797066263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.1797066263 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3464359513 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 184502040 ps |
CPU time | 1.01 seconds |
Started | Jul 12 04:34:16 PM PDT 24 |
Finished | Jul 12 04:34:18 PM PDT 24 |
Peak memory | 204432 kb |
Host | smart-a35c4aad-193c-48c7-852c-a1542679ea71 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464359513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.3464359513 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2922287864 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 211591676 ps |
CPU time | 1.21 seconds |
Started | Jul 12 04:34:17 PM PDT 24 |
Finished | Jul 12 04:34:19 PM PDT 24 |
Peak memory | 204412 kb |
Host | smart-f15fa8fd-95ec-477a-b72e-0d69637874c1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922287864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2 922287864 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.844881292 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 36465008 ps |
CPU time | 0.73 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:34:31 PM PDT 24 |
Peak memory | 204412 kb |
Host | smart-5c580920-fa02-4215-8323-079c261b79c1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844881292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part ial_access.844881292 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1101828926 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 111083711 ps |
CPU time | 0.72 seconds |
Started | Jul 12 04:34:29 PM PDT 24 |
Finished | Jul 12 04:34:35 PM PDT 24 |
Peak memory | 204368 kb |
Host | smart-06b48e29-4042-424b-8e89-64385cb4618f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101828926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1101828926 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2141902223 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 322915088 ps |
CPU time | 3.63 seconds |
Started | Jul 12 04:34:23 PM PDT 24 |
Finished | Jul 12 04:34:28 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-a4fdc1ee-56f0-46ab-9199-c1b4da3eb2fe |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141902223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.2141902223 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3248978109 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 48443695 ps |
CPU time | 2.44 seconds |
Started | Jul 12 04:34:25 PM PDT 24 |
Finished | Jul 12 04:34:30 PM PDT 24 |
Peak memory | 212968 kb |
Host | smart-635f77ee-eea0-4ee4-87c4-8ae9b73e4709 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248978109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3248978109 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3305154641 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 5364609463 ps |
CPU time | 29.99 seconds |
Started | Jul 12 04:34:27 PM PDT 24 |
Finished | Jul 12 04:35:01 PM PDT 24 |
Peak memory | 213028 kb |
Host | smart-8a7ce025-3d2d-4352-a1c1-b0ce47612d7c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305154641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3305154641 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.250407208 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 7908162074 ps |
CPU time | 53.5 seconds |
Started | Jul 12 04:34:23 PM PDT 24 |
Finished | Jul 12 04:35:18 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-2df1e097-b6f2-4512-a690-19af6c016902 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250407208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.250407208 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.375748385 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 137957692 ps |
CPU time | 1.65 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:37 PM PDT 24 |
Peak memory | 212300 kb |
Host | smart-15a34ceb-d924-4ca1-a0f4-9d970778df59 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375748385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.375748385 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2975132442 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 1654778436 ps |
CPU time | 3.26 seconds |
Started | Jul 12 04:34:27 PM PDT 24 |
Finished | Jul 12 04:34:34 PM PDT 24 |
Peak memory | 219196 kb |
Host | smart-fa1a46fa-71b8-49c1-acad-6804d7f785bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975132442 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2975132442 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3742568434 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 158615415 ps |
CPU time | 1.59 seconds |
Started | Jul 12 04:34:29 PM PDT 24 |
Finished | Jul 12 04:34:35 PM PDT 24 |
Peak memory | 212944 kb |
Host | smart-66af153e-b1ee-4358-9da6-5755230965b0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742568434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3742568434 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3420866365 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 86697847573 ps |
CPU time | 241.42 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:38:30 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-700ea982-c4cf-4ea0-9ab6-faa6644b3204 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420866365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.3420866365 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.121521939 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 44702495618 ps |
CPU time | 62.77 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:35:32 PM PDT 24 |
Peak memory | 204756 kb |
Host | smart-171a7c44-6723-4292-88f7-ff4eef43775a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121521939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r v_dm_jtag_dmi_csr_bit_bash.121521939 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3658476548 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 2014225626 ps |
CPU time | 6.88 seconds |
Started | Jul 12 04:34:27 PM PDT 24 |
Finished | Jul 12 04:34:38 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-5c66fbc7-531c-49f0-8bfe-49dd63c01c16 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658476548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.3658476548 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3187814520 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 7095500151 ps |
CPU time | 5.34 seconds |
Started | Jul 12 04:34:25 PM PDT 24 |
Finished | Jul 12 04:34:32 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-e67cc417-0157-4049-adbb-8c3d4784d2f3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187814520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3 187814520 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1520974931 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 812700066 ps |
CPU time | 1.26 seconds |
Started | Jul 12 04:34:25 PM PDT 24 |
Finished | Jul 12 04:34:29 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-a1da70a5-3f39-456b-9430-ef0657ec248a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520974931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.1520974931 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.771801153 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 3911136285 ps |
CPU time | 11.61 seconds |
Started | Jul 12 04:34:25 PM PDT 24 |
Finished | Jul 12 04:34:38 PM PDT 24 |
Peak memory | 204760 kb |
Host | smart-765a5de0-720f-4d11-8e5d-6bc04d22473f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771801153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _bit_bash.771801153 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1430849170 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 243334840 ps |
CPU time | 0.8 seconds |
Started | Jul 12 04:34:27 PM PDT 24 |
Finished | Jul 12 04:34:31 PM PDT 24 |
Peak memory | 204368 kb |
Host | smart-c73a8271-f906-4ce4-b9a1-1740b487ef7f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430849170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.1430849170 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3273347980 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 494302612 ps |
CPU time | 1.95 seconds |
Started | Jul 12 04:34:25 PM PDT 24 |
Finished | Jul 12 04:34:30 PM PDT 24 |
Peak memory | 204376 kb |
Host | smart-96d6c72e-ceaf-406b-be76-b585e352f3ab |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273347980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3 273347980 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1684566443 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 137073515 ps |
CPU time | 0.73 seconds |
Started | Jul 12 04:34:22 PM PDT 24 |
Finished | Jul 12 04:34:24 PM PDT 24 |
Peak memory | 204412 kb |
Host | smart-8ceaf306-50da-4e37-ae66-69c073802571 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684566443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.1684566443 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3564522997 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 86057377 ps |
CPU time | 0.85 seconds |
Started | Jul 12 04:34:22 PM PDT 24 |
Finished | Jul 12 04:34:24 PM PDT 24 |
Peak memory | 204432 kb |
Host | smart-44e6eecc-ada6-4408-8f30-104cbe1fc0a6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564522997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3564522997 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1509436077 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 219272415 ps |
CPU time | 3.68 seconds |
Started | Jul 12 04:34:24 PM PDT 24 |
Finished | Jul 12 04:34:30 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-fbe7514e-ddd5-41e1-839d-891a6717282f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509436077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.1509436077 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3423776668 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 49675340232 ps |
CPU time | 79.04 seconds |
Started | Jul 12 04:34:27 PM PDT 24 |
Finished | Jul 12 04:35:51 PM PDT 24 |
Peak memory | 221156 kb |
Host | smart-642d88f7-d9e4-4fcf-a4f5-4b3eb65f65a2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423776668 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3423776668 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4261114902 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 522375376 ps |
CPU time | 2.84 seconds |
Started | Jul 12 04:34:25 PM PDT 24 |
Finished | Jul 12 04:34:30 PM PDT 24 |
Peak memory | 213064 kb |
Host | smart-674404f9-a9b0-443a-9f18-0092c13bcabf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261114902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.4261114902 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1014279209 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 4105347193 ps |
CPU time | 19.03 seconds |
Started | Jul 12 04:34:27 PM PDT 24 |
Finished | Jul 12 04:34:50 PM PDT 24 |
Peak memory | 212948 kb |
Host | smart-727f34e6-8843-4e72-847e-4ce4f3d57656 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014279209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1014279209 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2683678041 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 78829078 ps |
CPU time | 2.66 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:34:33 PM PDT 24 |
Peak memory | 218060 kb |
Host | smart-2c576bfe-039f-42b2-b5a1-63d2157a6750 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683678041 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2683678041 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2014859478 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 78807069 ps |
CPU time | 1.75 seconds |
Started | Jul 12 04:34:25 PM PDT 24 |
Finished | Jul 12 04:34:29 PM PDT 24 |
Peak memory | 212876 kb |
Host | smart-f4b60e72-e6d1-4e28-b2f4-612e4d4b6041 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014859478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2014859478 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4247076474 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 7838587192 ps |
CPU time | 11.73 seconds |
Started | Jul 12 04:34:24 PM PDT 24 |
Finished | Jul 12 04:34:37 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-6a92c9dc-e3dd-432c-9e00-8847b2b12f25 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247076474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. rv_dm_jtag_dmi_csr_bit_bash.4247076474 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3599234919 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 2831580578 ps |
CPU time | 9.18 seconds |
Started | Jul 12 04:34:27 PM PDT 24 |
Finished | Jul 12 04:34:39 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-cf68c709-7f2a-495d-9377-c218e69feb15 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599234919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3 599234919 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2128427615 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 225423166 ps |
CPU time | 1 seconds |
Started | Jul 12 04:34:24 PM PDT 24 |
Finished | Jul 12 04:34:27 PM PDT 24 |
Peak memory | 204420 kb |
Host | smart-0fc6a922-cc6c-4aa8-8357-0b0691a74b58 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128427615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2 128427615 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3978531622 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 221995169 ps |
CPU time | 6.82 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:34:37 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-d693e27b-7765-4676-b47e-d97f7657e3d5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978531622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.3978531622 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.66532323 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 47294688899 ps |
CPU time | 133.29 seconds |
Started | Jul 12 04:34:24 PM PDT 24 |
Finished | Jul 12 04:36:39 PM PDT 24 |
Peak memory | 220888 kb |
Host | smart-e184fd24-db03-4b57-ae0e-654366b26084 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66532323 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.66532323 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3186689679 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 240941887 ps |
CPU time | 3.88 seconds |
Started | Jul 12 04:34:28 PM PDT 24 |
Finished | Jul 12 04:34:36 PM PDT 24 |
Peak memory | 213000 kb |
Host | smart-0c5dfee9-9f83-4c1c-a66a-41dfa01f34b5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186689679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3186689679 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3218521728 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 709781139 ps |
CPU time | 9.21 seconds |
Started | Jul 12 04:34:27 PM PDT 24 |
Finished | Jul 12 04:34:39 PM PDT 24 |
Peak memory | 212908 kb |
Host | smart-b0e2c122-518c-4117-9825-25f5d159e257 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218521728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3218521728 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.4097785894 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 3705219881 ps |
CPU time | 6.07 seconds |
Started | Jul 12 04:34:24 PM PDT 24 |
Finished | Jul 12 04:34:31 PM PDT 24 |
Peak memory | 216988 kb |
Host | smart-c28b475e-dcdd-48ef-8523-f82ffb526650 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097785894 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.4097785894 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.895860387 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 159795473 ps |
CPU time | 2.15 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:34:32 PM PDT 24 |
Peak memory | 212924 kb |
Host | smart-913a6bfa-7e77-4f85-9841-32ea081bddfb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895860387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.895860387 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.611075613 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 131721380 ps |
CPU time | 0.88 seconds |
Started | Jul 12 04:34:24 PM PDT 24 |
Finished | Jul 12 04:34:26 PM PDT 24 |
Peak memory | 204404 kb |
Host | smart-b21b5b35-c84f-44d2-b77c-1cee569ab01a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611075613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r v_dm_jtag_dmi_csr_bit_bash.611075613 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.638134730 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 1647164907 ps |
CPU time | 2.05 seconds |
Started | Jul 12 04:34:25 PM PDT 24 |
Finished | Jul 12 04:34:30 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-50c69f59-e18a-47c8-8bb4-e503da25bde0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638134730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.638134730 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2912017021 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 546938050 ps |
CPU time | 2.12 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:34:31 PM PDT 24 |
Peak memory | 204432 kb |
Host | smart-9ae92fb9-65fd-4e5e-a1ef-bc6872df79ed |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912017021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2 912017021 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1918932195 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 624742579 ps |
CPU time | 6.5 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:42 PM PDT 24 |
Peak memory | 204648 kb |
Host | smart-2a20b64c-2a64-47ac-8593-91597d206ce8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918932195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.1918932195 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.783001538 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 25858037766 ps |
CPU time | 26.26 seconds |
Started | Jul 12 04:34:23 PM PDT 24 |
Finished | Jul 12 04:34:51 PM PDT 24 |
Peak memory | 221276 kb |
Host | smart-f19ff4aa-7510-4c7a-b016-3b1a2f1e270b |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783001538 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.783001538 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2280983469 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 305965142 ps |
CPU time | 4.42 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:40 PM PDT 24 |
Peak memory | 213012 kb |
Host | smart-57edc50f-fde0-4a98-ba5e-b28bd7389c19 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280983469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2280983469 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1800952391 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 5607107824 ps |
CPU time | 20.42 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:56 PM PDT 24 |
Peak memory | 212728 kb |
Host | smart-cb198009-4e5b-4cf7-9818-becd4d70edac |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800952391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1800952391 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1464285163 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 4711805932 ps |
CPU time | 10.76 seconds |
Started | Jul 12 04:34:27 PM PDT 24 |
Finished | Jul 12 04:34:42 PM PDT 24 |
Peak memory | 220820 kb |
Host | smart-7140d1d6-05f8-4001-88e8-573a899158a9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464285163 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1464285163 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1451066602 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 90366861 ps |
CPU time | 2.16 seconds |
Started | Jul 12 04:34:27 PM PDT 24 |
Finished | Jul 12 04:34:33 PM PDT 24 |
Peak memory | 212852 kb |
Host | smart-ee19cf42-cde3-4a10-a1b3-0d9062b99452 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451066602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1451066602 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3295725247 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 23003576799 ps |
CPU time | 23.51 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:59 PM PDT 24 |
Peak memory | 204388 kb |
Host | smart-2b87810b-5b4c-49de-8403-ac344d4f0ca9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295725247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. rv_dm_jtag_dmi_csr_bit_bash.3295725247 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.150883146 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 2868176745 ps |
CPU time | 2.85 seconds |
Started | Jul 12 04:34:25 PM PDT 24 |
Finished | Jul 12 04:34:32 PM PDT 24 |
Peak memory | 204756 kb |
Host | smart-866072a2-4027-470d-b3db-58aaae3192c4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150883146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.150883146 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2126255656 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 460017873 ps |
CPU time | 1.87 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:38 PM PDT 24 |
Peak memory | 204360 kb |
Host | smart-7a20964f-bd79-44b0-a1d0-de2704186108 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126255656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2 126255656 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.4287315162 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 422623490 ps |
CPU time | 4.13 seconds |
Started | Jul 12 04:34:22 PM PDT 24 |
Finished | Jul 12 04:34:28 PM PDT 24 |
Peak memory | 204744 kb |
Host | smart-2f571a77-6a3b-49df-964c-986dfe47d3f8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287315162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.4287315162 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1836214617 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 55393456280 ps |
CPU time | 152.45 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:37:01 PM PDT 24 |
Peak memory | 221180 kb |
Host | smart-7bb9a7ec-5b5e-4b86-99ec-c872f87b301c |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836214617 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1836214617 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1788054508 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 396876304 ps |
CPU time | 2.44 seconds |
Started | Jul 12 04:34:27 PM PDT 24 |
Finished | Jul 12 04:34:34 PM PDT 24 |
Peak memory | 212992 kb |
Host | smart-0bc33b3b-32db-4a59-9f95-0c2435984c53 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788054508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1788054508 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1246133211 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 777466359 ps |
CPU time | 9.85 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:34:40 PM PDT 24 |
Peak memory | 212848 kb |
Host | smart-f82a224c-3d74-4e08-8ab4-4ddbfb674798 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246133211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1246133211 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3888871208 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 2972971503 ps |
CPU time | 3.47 seconds |
Started | Jul 12 04:34:32 PM PDT 24 |
Finished | Jul 12 04:34:42 PM PDT 24 |
Peak memory | 213064 kb |
Host | smart-8cbd0b39-1d93-40ed-9192-27bde0452609 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888871208 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3888871208 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.4251081300 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 100321593 ps |
CPU time | 2.27 seconds |
Started | Jul 12 04:34:25 PM PDT 24 |
Finished | Jul 12 04:34:31 PM PDT 24 |
Peak memory | 212968 kb |
Host | smart-0fed86f9-5b87-4bda-b15c-3280e698649e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251081300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.4251081300 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3725382037 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 1700497342 ps |
CPU time | 3.68 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:34:34 PM PDT 24 |
Peak memory | 204568 kb |
Host | smart-653b15cb-bd9a-4552-a61f-44572683992b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725382037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. rv_dm_jtag_dmi_csr_bit_bash.3725382037 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2040547097 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 3035160005 ps |
CPU time | 5.51 seconds |
Started | Jul 12 04:34:24 PM PDT 24 |
Finished | Jul 12 04:34:31 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-35a690c5-adf0-4d82-8264-a751a7af604f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040547097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2 040547097 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1186369443 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 272134567 ps |
CPU time | 0.96 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:36 PM PDT 24 |
Peak memory | 204380 kb |
Host | smart-86ea2795-5bc8-4fb4-8a64-b1ac9bf3a87a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186369443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1 186369443 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1423425037 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 864860009 ps |
CPU time | 3.74 seconds |
Started | Jul 12 04:34:42 PM PDT 24 |
Finished | Jul 12 04:34:50 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-018ced7b-60e4-436e-8567-bfaf23efe212 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423425037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.1423425037 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3968294743 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 36108638702 ps |
CPU time | 109.17 seconds |
Started | Jul 12 04:34:26 PM PDT 24 |
Finished | Jul 12 04:36:18 PM PDT 24 |
Peak memory | 221208 kb |
Host | smart-c01308ea-da6b-45e3-bb38-4dbf1bd9f003 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968294743 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3968294743 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1790207581 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 245734407 ps |
CPU time | 3.31 seconds |
Started | Jul 12 04:34:28 PM PDT 24 |
Finished | Jul 12 04:34:36 PM PDT 24 |
Peak memory | 212972 kb |
Host | smart-cf1263fc-619e-4117-ada7-796aeb994016 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790207581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1790207581 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3128076480 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 964532119 ps |
CPU time | 11.13 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:46 PM PDT 24 |
Peak memory | 212952 kb |
Host | smart-c7ceb389-c18f-4c78-991b-716b2a8b21c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128076480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3128076480 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3183742179 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 1922561717 ps |
CPU time | 6.32 seconds |
Started | Jul 12 04:34:38 PM PDT 24 |
Finished | Jul 12 04:34:50 PM PDT 24 |
Peak memory | 216932 kb |
Host | smart-970d9825-dc6a-4972-a335-a7b1b09dd108 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183742179 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3183742179 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2259930095 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 117856384 ps |
CPU time | 2.22 seconds |
Started | Jul 12 04:34:31 PM PDT 24 |
Finished | Jul 12 04:34:39 PM PDT 24 |
Peak memory | 212852 kb |
Host | smart-c7d1b72a-6fa7-43c3-bc8f-fd30a7b24ec5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259930095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2259930095 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2304305442 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 25900723802 ps |
CPU time | 31.97 seconds |
Started | Jul 12 04:34:32 PM PDT 24 |
Finished | Jul 12 04:35:10 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-044dca63-a708-4cc1-ad67-5274957cde00 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304305442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.2304305442 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3555373473 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 3336613389 ps |
CPU time | 2.78 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:39 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-bb2a6da1-816a-4707-97a8-c2e78e42bb8e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555373473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3 555373473 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2040666596 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 464260854 ps |
CPU time | 0.9 seconds |
Started | Jul 12 04:34:30 PM PDT 24 |
Finished | Jul 12 04:34:36 PM PDT 24 |
Peak memory | 204400 kb |
Host | smart-c1543870-e6b1-4011-8c96-95a568f57683 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040666596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2 040666596 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.304009430 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 878584819 ps |
CPU time | 4.11 seconds |
Started | Jul 12 04:34:33 PM PDT 24 |
Finished | Jul 12 04:34:44 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-a4391ae5-da21-427a-8484-326a1eaa3d75 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304009430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c sr_outstanding.304009430 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3286537182 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 62910938688 ps |
CPU time | 49.19 seconds |
Started | Jul 12 04:34:32 PM PDT 24 |
Finished | Jul 12 04:35:27 PM PDT 24 |
Peak memory | 221228 kb |
Host | smart-cdbd3c36-2049-4010-a2a8-95d8b31a0df1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286537182 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3286537182 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1348536815 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 202028487 ps |
CPU time | 4.55 seconds |
Started | Jul 12 04:34:32 PM PDT 24 |
Finished | Jul 12 04:34:42 PM PDT 24 |
Peak memory | 213068 kb |
Host | smart-b4db33cd-2e08-47cb-afb0-399fd8e0ceec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348536815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1348536815 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1865749809 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 3324603616 ps |
CPU time | 18.05 seconds |
Started | Jul 12 04:34:31 PM PDT 24 |
Finished | Jul 12 04:34:55 PM PDT 24 |
Peak memory | 213008 kb |
Host | smart-e3ee8e79-476f-42ce-a405-75791eb692a4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865749809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1865749809 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.2150898113 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 137570210 ps |
CPU time | 1.06 seconds |
Started | Jul 12 05:59:38 PM PDT 24 |
Finished | Jul 12 05:59:42 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-5ffb46f4-99ad-4e48-8e61-2fc43227b3ba |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150898113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2150898113 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3001929192 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 6416424539 ps |
CPU time | 10.3 seconds |
Started | Jul 12 05:59:34 PM PDT 24 |
Finished | Jul 12 05:59:48 PM PDT 24 |
Peak memory | 213604 kb |
Host | smart-18e39bf4-018a-4066-8de1-1668fd342914 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3001929192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3001929192 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.4218544222 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 998303208 ps |
CPU time | 1.46 seconds |
Started | Jul 12 05:59:33 PM PDT 24 |
Finished | Jul 12 05:59:39 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-c586b05f-a640-4489-9464-706099dd41b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4218544222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.4218544222 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3880926782 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 280354449 ps |
CPU time | 0.8 seconds |
Started | Jul 12 05:59:30 PM PDT 24 |
Finished | Jul 12 05:59:37 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-887bf984-5bf7-4ca9-bdb1-dd8eafae1c7b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3880926782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3880926782 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.162993197 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 171050964 ps |
CPU time | 1.02 seconds |
Started | Jul 12 05:59:38 PM PDT 24 |
Finished | Jul 12 05:59:41 PM PDT 24 |
Peak memory | 215404 kb |
Host | smart-71836fd2-5709-49f0-9513-a5d1815fd0e1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=162993197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.162993197 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1911048092 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 5689016346 ps |
CPU time | 5.38 seconds |
Started | Jul 12 05:59:33 PM PDT 24 |
Finished | Jul 12 05:59:43 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-520c2230-90db-42ee-ab3c-4316fd7adffc |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1911048092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.1911048092 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1207195984 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 688061770 ps |
CPU time | 1.06 seconds |
Started | Jul 12 05:59:36 PM PDT 24 |
Finished | Jul 12 05:59:40 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-35eb0e2c-893f-4f7c-8e73-f68758e84d2a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1207195984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1207195984 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.694183601 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 281028347 ps |
CPU time | 0.73 seconds |
Started | Jul 12 05:59:32 PM PDT 24 |
Finished | Jul 12 05:59:38 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-4bccdd22-ddbe-434b-9659-206759f5f62c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=694183601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.694183601 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2870199627 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 396570389 ps |
CPU time | 1.77 seconds |
Started | Jul 12 05:59:39 PM PDT 24 |
Finished | Jul 12 05:59:43 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-df233349-844e-4075-8eb9-3958f6b07d6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2870199627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2870199627 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.161244702 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 737383737 ps |
CPU time | 2.91 seconds |
Started | Jul 12 05:59:39 PM PDT 24 |
Finished | Jul 12 05:59:44 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-dda79b7e-3214-4c81-9451-8916fc9210b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161244702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.161244702 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2075759248 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 377711030 ps |
CPU time | 0.98 seconds |
Started | Jul 12 05:59:39 PM PDT 24 |
Finished | Jul 12 05:59:42 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-1542e489-34e6-4edc-bd7e-2e93cd0a735c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075759248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2075759248 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1503584968 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 501424157 ps |
CPU time | 0.9 seconds |
Started | Jul 12 05:59:33 PM PDT 24 |
Finished | Jul 12 05:59:39 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-41d24217-ab79-498a-9bad-19c336d055b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1503584968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1503584968 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.447550628 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 3120537170 ps |
CPU time | 9.14 seconds |
Started | Jul 12 05:59:35 PM PDT 24 |
Finished | Jul 12 05:59:48 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-96c88cc2-8251-493f-928f-04fefb5dc926 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=447550628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.447550628 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.2399185437 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 224636953 ps |
CPU time | 0.82 seconds |
Started | Jul 12 05:59:36 PM PDT 24 |
Finished | Jul 12 05:59:40 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-a8bab737-5018-4465-a0fa-d66c109fcdf4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2399185437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2399185437 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.530426042 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 1039620090 ps |
CPU time | 3.3 seconds |
Started | Jul 12 05:59:38 PM PDT 24 |
Finished | Jul 12 05:59:44 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-3524a310-cb69-4f25-9663-de4706bb9975 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=530426042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.530426042 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.3863093761 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 164424894 ps |
CPU time | 0.92 seconds |
Started | Jul 12 05:59:38 PM PDT 24 |
Finished | Jul 12 05:59:42 PM PDT 24 |
Peak memory | 213404 kb |
Host | smart-6158e1d3-5872-4249-a062-af64737a20d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863093761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3863093761 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.1911790783 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 929275250 ps |
CPU time | 2.38 seconds |
Started | Jul 12 05:59:37 PM PDT 24 |
Finished | Jul 12 05:59:42 PM PDT 24 |
Peak memory | 236876 kb |
Host | smart-a8cb2f74-dbf2-4bce-a2f0-3cd254ed4663 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911790783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1911790783 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.4027013742 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 3435048540 ps |
CPU time | 10.45 seconds |
Started | Jul 12 05:59:32 PM PDT 24 |
Finished | Jul 12 05:59:48 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-227c13f5-09c9-4c70-87df-f75fbb6a5ca6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027013742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.4027013742 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.3111781133 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 542952395 ps |
CPU time | 1.08 seconds |
Started | Jul 12 05:59:45 PM PDT 24 |
Finished | Jul 12 05:59:47 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-f155cfac-1bfb-4ffe-971d-5633ea13a9fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3111781133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3111781133 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.160669179 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 155293118 ps |
CPU time | 0.87 seconds |
Started | Jul 12 05:59:44 PM PDT 24 |
Finished | Jul 12 05:59:46 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-a4c25469-6ed8-448a-8f66-4753943d7c90 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160669179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.160669179 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1265313089 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 17546132211 ps |
CPU time | 30.31 seconds |
Started | Jul 12 05:59:43 PM PDT 24 |
Finished | Jul 12 06:00:14 PM PDT 24 |
Peak memory | 213696 kb |
Host | smart-759f4e2d-7e2f-4393-899c-064e25e31987 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1265313089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1265313089 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2674113904 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 9374504473 ps |
CPU time | 11.92 seconds |
Started | Jul 12 05:59:37 PM PDT 24 |
Finished | Jul 12 05:59:52 PM PDT 24 |
Peak memory | 215484 kb |
Host | smart-46624d6b-3d0f-468a-98d0-f0951232dda2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2674113904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2674113904 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.3102038859 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 870889593 ps |
CPU time | 1.74 seconds |
Started | Jul 12 05:59:38 PM PDT 24 |
Finished | Jul 12 05:59:42 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-ec4b8fde-36f4-4f19-9c4e-71183d8edfd2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3102038859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3102038859 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2124873220 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 346586153 ps |
CPU time | 1.83 seconds |
Started | Jul 12 05:59:44 PM PDT 24 |
Finished | Jul 12 05:59:47 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-934c3dcd-1695-4987-a2aa-32e4771d8650 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2124873220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2124873220 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.138314519 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 172609663 ps |
CPU time | 0.93 seconds |
Started | Jul 12 05:59:37 PM PDT 24 |
Finished | Jul 12 05:59:41 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-2b9db284-60d0-4ce1-b7bf-b2e42b0d3004 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=138314519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.138314519 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1289075705 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 321767306 ps |
CPU time | 1.55 seconds |
Started | Jul 12 05:59:43 PM PDT 24 |
Finished | Jul 12 05:59:46 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-2ed60370-64bc-49d1-8dba-fe1c0d0f80cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1289075705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1289075705 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.734760245 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 4616332238 ps |
CPU time | 8.37 seconds |
Started | Jul 12 05:59:37 PM PDT 24 |
Finished | Jul 12 05:59:48 PM PDT 24 |
Peak memory | 213720 kb |
Host | smart-88d5982c-f050-4bbf-8c92-0a8ca35c289d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=734760245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl _access.734760245 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_dmi_failed_op.2952188836 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 210708235 ps |
CPU time | 1.26 seconds |
Started | Jul 12 05:59:44 PM PDT 24 |
Finished | Jul 12 05:59:47 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-62047e17-bff1-4489-9d30-72d0bf0e7547 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2952188836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2952188836 |
Directory | /workspace/1.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1301619370 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 1925296868 ps |
CPU time | 1.25 seconds |
Started | Jul 12 05:59:44 PM PDT 24 |
Finished | Jul 12 05:59:47 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-2c228552-ba8a-4dd4-9cbc-f097aef49560 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1301619370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1301619370 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.4289351431 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 208465238 ps |
CPU time | 0.87 seconds |
Started | Jul 12 05:59:43 PM PDT 24 |
Finished | Jul 12 05:59:45 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-a3ef3d90-01e1-428e-a436-d6f4b3a3c230 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4289351431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.4289351431 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2720430287 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 2394836874 ps |
CPU time | 3.61 seconds |
Started | Jul 12 05:59:44 PM PDT 24 |
Finished | Jul 12 05:59:49 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-5f0952ac-e05c-4471-a5ba-7d1cf78b547f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2720430287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2720430287 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1310125674 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 2159798221 ps |
CPU time | 2.83 seconds |
Started | Jul 12 05:59:45 PM PDT 24 |
Finished | Jul 12 05:59:49 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-97a7c817-8f31-4c59-9a78-a288a45a6988 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1310125674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1310125674 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2013004040 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 109109293 ps |
CPU time | 0.84 seconds |
Started | Jul 12 05:59:44 PM PDT 24 |
Finished | Jul 12 05:59:46 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-6dde264b-7421-4284-a7b9-aa35e8e717d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013004040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2013004040 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.770720455 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 633426039 ps |
CPU time | 2.34 seconds |
Started | Jul 12 05:59:38 PM PDT 24 |
Finished | Jul 12 05:59:43 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-12dde000-0039-4e37-89b1-6ad3f5420db0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=770720455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.770720455 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.329311807 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 478468701 ps |
CPU time | 1.34 seconds |
Started | Jul 12 05:59:38 PM PDT 24 |
Finished | Jul 12 05:59:42 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-d00e4d51-3765-465a-9ed6-1659152fe64e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329311807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.329311807 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.3495188494 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 410339794 ps |
CPU time | 0.91 seconds |
Started | Jul 12 05:59:43 PM PDT 24 |
Finished | Jul 12 05:59:45 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-f2b3313b-ae43-4f19-94d9-d2e1656f2dd5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3495188494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3495188494 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_busy.2239304308 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 810596779 ps |
CPU time | 1.5 seconds |
Started | Jul 12 05:59:44 PM PDT 24 |
Finished | Jul 12 05:59:47 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-e61e5a9f-5b6e-48f8-a192-6cc4effea8e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2239304308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2239304308 |
Directory | /workspace/1.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3955507541 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 3242676574 ps |
CPU time | 3.81 seconds |
Started | Jul 12 05:59:44 PM PDT 24 |
Finished | Jul 12 05:59:49 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-863b2170-3a66-4227-8d1f-fe84b6f4d26e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3955507541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3955507541 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.1895626488 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 3926265475 ps |
CPU time | 7.29 seconds |
Started | Jul 12 05:59:39 PM PDT 24 |
Finished | Jul 12 05:59:49 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-9056e3ca-f916-4174-9c2a-c3a7e5130d82 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1895626488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1895626488 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.3363448680 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 1891243843 ps |
CPU time | 6.16 seconds |
Started | Jul 12 05:59:42 PM PDT 24 |
Finished | Jul 12 05:59:48 PM PDT 24 |
Peak memory | 229144 kb |
Host | smart-cd5229d9-595c-4c72-b330-e3c05ae4b82b |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363448680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3363448680 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.2673424485 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 1565058699 ps |
CPU time | 5.3 seconds |
Started | Jul 12 05:59:35 PM PDT 24 |
Finished | Jul 12 05:59:44 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-f27a0380-fde6-423e-9aed-da39bc30e64f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2673424485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2673424485 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.4018346976 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 2378565498 ps |
CPU time | 2.24 seconds |
Started | Jul 12 05:59:44 PM PDT 24 |
Finished | Jul 12 05:59:47 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-c5c75ce8-69db-4353-aa26-c9b4ff9c6264 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018346976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.4018346976 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.2990228650 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 38129178 ps |
CPU time | 0.79 seconds |
Started | Jul 12 06:00:04 PM PDT 24 |
Finished | Jul 12 06:00:06 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-8991f207-f9a6-4b3c-bd90-f287c6e0ba54 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990228650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2990228650 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.989680884 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 8638647581 ps |
CPU time | 24.24 seconds |
Started | Jul 12 06:00:01 PM PDT 24 |
Finished | Jul 12 06:00:28 PM PDT 24 |
Peak memory | 215072 kb |
Host | smart-676c9652-7a1c-4846-b226-6951660b512d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=989680884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t l_access.989680884 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.3851615942 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 1384662058 ps |
CPU time | 3.01 seconds |
Started | Jul 12 06:00:01 PM PDT 24 |
Finished | Jul 12 06:00:07 PM PDT 24 |
Peak memory | 205432 kb |
Host | smart-d2d20120-d096-4450-add4-531e58d27986 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3851615942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3851615942 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.2317283145 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 7424184183 ps |
CPU time | 2.45 seconds |
Started | Jul 12 06:00:04 PM PDT 24 |
Finished | Jul 12 06:00:08 PM PDT 24 |
Peak memory | 213724 kb |
Host | smart-aa57eac9-34f4-4d82-9089-64c525979876 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317283145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2317283145 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.966815569 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 108865128 ps |
CPU time | 0.98 seconds |
Started | Jul 12 06:00:02 PM PDT 24 |
Finished | Jul 12 06:00:05 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-50a2cb12-eb6e-4d69-b1a6-99079acafa4c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966815569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.966815569 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1164364271 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 19808543761 ps |
CPU time | 55.24 seconds |
Started | Jul 12 06:00:02 PM PDT 24 |
Finished | Jul 12 06:00:59 PM PDT 24 |
Peak memory | 213724 kb |
Host | smart-8e00546e-75b3-40c1-a81c-0c00c98190a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1164364271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1164364271 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1288287249 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 2816618171 ps |
CPU time | 8.8 seconds |
Started | Jul 12 06:00:03 PM PDT 24 |
Finished | Jul 12 06:00:14 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-a9792114-8208-4250-8c0e-e09b446c2e21 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1288287249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1288287249 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2833796598 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 10487709285 ps |
CPU time | 28.02 seconds |
Started | Jul 12 06:00:01 PM PDT 24 |
Finished | Jul 12 06:00:32 PM PDT 24 |
Peak memory | 221816 kb |
Host | smart-1ac69e35-34c2-48f9-9a62-0b350d58c280 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2833796598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.2833796598 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.552126805 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 944254426 ps |
CPU time | 1.39 seconds |
Started | Jul 12 06:00:04 PM PDT 24 |
Finished | Jul 12 06:00:07 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-9d822ca6-0a3c-45b7-8755-81a25b965b3a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=552126805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.552126805 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.135844593 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 2458098779 ps |
CPU time | 4.87 seconds |
Started | Jul 12 06:00:02 PM PDT 24 |
Finished | Jul 12 06:00:09 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-541a8b6b-e7a0-4097-b4aa-22d71806d7f6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135844593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.135844593 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.1000684626 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 120943404 ps |
CPU time | 0.99 seconds |
Started | Jul 12 06:00:05 PM PDT 24 |
Finished | Jul 12 06:00:08 PM PDT 24 |
Peak memory | 205088 kb |
Host | smart-16963d3c-4eab-4f13-a731-532f0098d1c3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000684626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1000684626 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3771884679 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 28460536006 ps |
CPU time | 22.68 seconds |
Started | Jul 12 06:00:04 PM PDT 24 |
Finished | Jul 12 06:00:29 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-19b4e1ee-8746-429d-b84d-9de58c37c1ae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771884679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3771884679 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1535728672 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 1385157052 ps |
CPU time | 1.73 seconds |
Started | Jul 12 06:00:01 PM PDT 24 |
Finished | Jul 12 06:00:05 PM PDT 24 |
Peak memory | 213648 kb |
Host | smart-3a345991-33a9-49c3-b670-48f271750803 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1535728672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1535728672 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1042023780 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 9049777952 ps |
CPU time | 24.87 seconds |
Started | Jul 12 06:00:03 PM PDT 24 |
Finished | Jul 12 06:00:30 PM PDT 24 |
Peak memory | 215188 kb |
Host | smart-148f384f-4659-48f3-a9fa-e56e02c845cf |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1042023780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_ tl_access.1042023780 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.1728697859 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 1625427182 ps |
CPU time | 2.03 seconds |
Started | Jul 12 06:00:01 PM PDT 24 |
Finished | Jul 12 06:00:06 PM PDT 24 |
Peak memory | 205516 kb |
Host | smart-2bea5449-e79c-4eb4-864b-ad1dfdd4b598 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1728697859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1728697859 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.2088985303 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 63731081 ps |
CPU time | 0.77 seconds |
Started | Jul 12 06:00:03 PM PDT 24 |
Finished | Jul 12 06:00:06 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-84d9fc4e-85d8-4a3a-a5ff-deac2cfeef54 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088985303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2088985303 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.4282373807 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 711761894 ps |
CPU time | 1.29 seconds |
Started | Jul 12 06:00:02 PM PDT 24 |
Finished | Jul 12 06:00:06 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-b57da401-d223-4543-8ca5-c8659b67ac35 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4282373807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.4282373807 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1318564841 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 2262372029 ps |
CPU time | 7.62 seconds |
Started | Jul 12 06:00:03 PM PDT 24 |
Finished | Jul 12 06:00:13 PM PDT 24 |
Peak memory | 213720 kb |
Host | smart-0d2d1f3a-1b17-459e-b609-aabf5b6c95d3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1318564841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.1318564841 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.309844743 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 1852476825 ps |
CPU time | 2.09 seconds |
Started | Jul 12 06:00:02 PM PDT 24 |
Finished | Jul 12 06:00:07 PM PDT 24 |
Peak memory | 205424 kb |
Host | smart-0417d601-778d-418d-bc58-2c7777b8fcaf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309844743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.309844743 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.3276370797 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 107289655 ps |
CPU time | 0.76 seconds |
Started | Jul 12 06:00:09 PM PDT 24 |
Finished | Jul 12 06:00:12 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-affc9088-8eca-4f20-87ae-3bcf751c02b7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276370797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3276370797 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.719768376 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 8299276889 ps |
CPU time | 8.03 seconds |
Started | Jul 12 06:00:00 PM PDT 24 |
Finished | Jul 12 06:00:11 PM PDT 24 |
Peak memory | 205540 kb |
Host | smart-c4b6fca8-d51a-4345-b9b8-a5f8134f044c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=719768376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.719768376 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2622385491 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 3221171961 ps |
CPU time | 4.03 seconds |
Started | Jul 12 06:00:03 PM PDT 24 |
Finished | Jul 12 06:00:09 PM PDT 24 |
Peak memory | 213624 kb |
Host | smart-2780137d-444f-45c2-adaf-1ec8c25d0339 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2622385491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.2622385491 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.337866810 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 137698514 ps |
CPU time | 0.72 seconds |
Started | Jul 12 06:00:08 PM PDT 24 |
Finished | Jul 12 06:00:11 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-b1b05aaa-6751-484d-a4b2-26640f40835d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337866810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.337866810 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3441738707 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 7755528545 ps |
CPU time | 11.27 seconds |
Started | Jul 12 06:00:14 PM PDT 24 |
Finished | Jul 12 06:00:27 PM PDT 24 |
Peak memory | 221836 kb |
Host | smart-8705697c-bf03-4fe4-a67b-be17f8584c34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3441738707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3441738707 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3953769471 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 4210959847 ps |
CPU time | 11.83 seconds |
Started | Jul 12 06:00:08 PM PDT 24 |
Finished | Jul 12 06:00:22 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-8b65c737-6fb9-487c-9035-307c481f4085 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3953769471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.3953769471 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.2000185525 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 853674449 ps |
CPU time | 3.44 seconds |
Started | Jul 12 06:00:06 PM PDT 24 |
Finished | Jul 12 06:00:11 PM PDT 24 |
Peak memory | 205416 kb |
Host | smart-68c15cc3-05df-45c8-a60a-2e6272a481fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000185525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2000185525 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_stress_all.3525959674 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 1259007148 ps |
CPU time | 1.28 seconds |
Started | Jul 12 06:00:04 PM PDT 24 |
Finished | Jul 12 06:00:07 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-0f17bcfc-6571-440a-b7a5-255e43e05732 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525959674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3525959674 |
Directory | /workspace/15.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.2067701279 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 59171090 ps |
CPU time | 0.85 seconds |
Started | Jul 12 06:00:08 PM PDT 24 |
Finished | Jul 12 06:00:11 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-f9d8b8df-416f-411a-b35e-a05a771e0093 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067701279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2067701279 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3828236446 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 9425765750 ps |
CPU time | 14.38 seconds |
Started | Jul 12 06:00:14 PM PDT 24 |
Finished | Jul 12 06:00:30 PM PDT 24 |
Peak memory | 213684 kb |
Host | smart-f7e3f316-a5b6-4e0c-ae40-6ad3007c6d98 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828236446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3828236446 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2927548802 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 2041253014 ps |
CPU time | 6.01 seconds |
Started | Jul 12 06:00:07 PM PDT 24 |
Finished | Jul 12 06:00:15 PM PDT 24 |
Peak memory | 213624 kb |
Host | smart-031118f8-a8af-48a3-ab12-965b7650bfe6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2927548802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2927548802 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1156456191 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 13748534891 ps |
CPU time | 24.19 seconds |
Started | Jul 12 06:00:13 PM PDT 24 |
Finished | Jul 12 06:00:39 PM PDT 24 |
Peak memory | 221804 kb |
Host | smart-b04c7f43-7faa-4358-88d7-54742c336919 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1156456191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_ tl_access.1156456191 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.1102622070 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 5716614236 ps |
CPU time | 9.11 seconds |
Started | Jul 12 06:00:09 PM PDT 24 |
Finished | Jul 12 06:00:20 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-dfa0b29b-41ab-48f5-81b7-3d3b84c8d472 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102622070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1102622070 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.3129716342 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 6320757583 ps |
CPU time | 2.84 seconds |
Started | Jul 12 06:00:10 PM PDT 24 |
Finished | Jul 12 06:00:14 PM PDT 24 |
Peak memory | 213564 kb |
Host | smart-efe3efc7-c824-4f3a-9714-7bbdedba1cd7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129716342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3129716342 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.331486683 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 156801402 ps |
CPU time | 1.13 seconds |
Started | Jul 12 06:00:14 PM PDT 24 |
Finished | Jul 12 06:00:17 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-02f5bbe0-52fe-430d-be87-13cf66587473 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331486683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.331486683 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2132611214 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 2061443205 ps |
CPU time | 2.77 seconds |
Started | Jul 12 06:00:09 PM PDT 24 |
Finished | Jul 12 06:00:14 PM PDT 24 |
Peak memory | 205432 kb |
Host | smart-f2d8c27b-3018-4110-8b13-3a9c38d96d8b |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2132611214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.2132611214 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_stress_all.932044825 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 4778245568 ps |
CPU time | 15.33 seconds |
Started | Jul 12 06:00:08 PM PDT 24 |
Finished | Jul 12 06:00:24 PM PDT 24 |
Peak memory | 213596 kb |
Host | smart-7f5fb8a8-4b04-4977-b47e-8b779a67dfc3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932044825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.932044825 |
Directory | /workspace/17.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.825925087 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 95106502 ps |
CPU time | 0.92 seconds |
Started | Jul 12 06:00:07 PM PDT 24 |
Finished | Jul 12 06:00:10 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-438e082c-58d5-4cab-829f-fe7d82f31227 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825925087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.825925087 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1690398443 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 9041027975 ps |
CPU time | 7.52 seconds |
Started | Jul 12 06:00:13 PM PDT 24 |
Finished | Jul 12 06:00:22 PM PDT 24 |
Peak memory | 213704 kb |
Host | smart-7d716103-292b-4c08-9583-c96bf2247d7d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1690398443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1690398443 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3815980375 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 7284436221 ps |
CPU time | 13.13 seconds |
Started | Jul 12 06:00:10 PM PDT 24 |
Finished | Jul 12 06:00:24 PM PDT 24 |
Peak memory | 215236 kb |
Host | smart-ad3ee8fb-b7cc-4db0-a56d-01c3f2b5882f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3815980375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3815980375 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.697802864 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 6795190008 ps |
CPU time | 10.8 seconds |
Started | Jul 12 06:00:10 PM PDT 24 |
Finished | Jul 12 06:00:22 PM PDT 24 |
Peak memory | 213724 kb |
Host | smart-dbf8699a-1b7d-49ee-a099-17a99cc1ed55 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=697802864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t l_access.697802864 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.986521644 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 202557193 ps |
CPU time | 0.82 seconds |
Started | Jul 12 06:00:23 PM PDT 24 |
Finished | Jul 12 06:00:26 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-db7af677-ea2a-4500-a720-c76d878acff3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986521644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.986521644 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3350797301 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 5199882528 ps |
CPU time | 15.82 seconds |
Started | Jul 12 06:00:17 PM PDT 24 |
Finished | Jul 12 06:00:35 PM PDT 24 |
Peak memory | 221900 kb |
Host | smart-29f327e2-438e-4251-a708-42af9ce43abf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350797301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3350797301 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3202597334 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 11094241970 ps |
CPU time | 34.06 seconds |
Started | Jul 12 06:00:13 PM PDT 24 |
Finished | Jul 12 06:00:48 PM PDT 24 |
Peak memory | 215596 kb |
Host | smart-700931b3-2f42-438b-ac3d-506cafa2f51c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3202597334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.3202597334 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.4083218671 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 7781199997 ps |
CPU time | 22.38 seconds |
Started | Jul 12 06:00:15 PM PDT 24 |
Finished | Jul 12 06:00:39 PM PDT 24 |
Peak memory | 205544 kb |
Host | smart-cee89580-5429-4305-8043-d53b5482d260 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4083218671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.4083218671 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.3155440866 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 9503902227 ps |
CPU time | 6.96 seconds |
Started | Jul 12 06:00:15 PM PDT 24 |
Finished | Jul 12 06:00:24 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-5d4d3eff-1ede-4369-a01f-a11615104710 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155440866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3155440866 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.3554606720 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 47158642 ps |
CPU time | 0.77 seconds |
Started | Jul 12 06:00:08 PM PDT 24 |
Finished | Jul 12 06:00:10 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-06d09f7f-f88d-4743-9042-60626a02b4f9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554606720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3554606720 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1596071271 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 5596332229 ps |
CPU time | 9.08 seconds |
Started | Jul 12 05:59:52 PM PDT 24 |
Finished | Jul 12 06:00:02 PM PDT 24 |
Peak memory | 221892 kb |
Host | smart-9c1492ff-e191-4b85-a866-fe8892a98d4b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596071271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1596071271 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2829784862 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 12785854898 ps |
CPU time | 34.84 seconds |
Started | Jul 12 06:00:10 PM PDT 24 |
Finished | Jul 12 06:00:46 PM PDT 24 |
Peak memory | 215704 kb |
Host | smart-080b4493-8e72-4f1a-96e7-416a91b4e19c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2829784862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t l_access.2829784862 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.1163541652 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 1334902318 ps |
CPU time | 2.6 seconds |
Started | Jul 12 05:59:50 PM PDT 24 |
Finished | Jul 12 05:59:53 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-fcbd78a3-9cac-4942-8d30-fcd0c7f33002 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1163541652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1163541652 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.4004014550 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 7768009458 ps |
CPU time | 5.3 seconds |
Started | Jul 12 05:59:44 PM PDT 24 |
Finished | Jul 12 05:59:51 PM PDT 24 |
Peak memory | 213688 kb |
Host | smart-e12f20a8-3ac7-49a5-8809-873d334ffefb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004014550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.4004014550 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all.2879336019 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 2967427918 ps |
CPU time | 5.47 seconds |
Started | Jul 12 05:59:50 PM PDT 24 |
Finished | Jul 12 05:59:57 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-18b4d77c-d379-4f98-97ad-47ff6b1d0825 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879336019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2879336019 |
Directory | /workspace/2.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.717109943 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 107543383 ps |
CPU time | 0.84 seconds |
Started | Jul 12 06:00:15 PM PDT 24 |
Finished | Jul 12 06:00:18 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-c2daf858-0389-4f5a-bb70-24dac1e9138f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717109943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.717109943 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/20.rv_dm_stress_all.4190531407 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 4829390910 ps |
CPU time | 7.08 seconds |
Started | Jul 12 06:00:17 PM PDT 24 |
Finished | Jul 12 06:00:26 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-b6b21a9f-a5a2-44c5-a97a-6b5925d155ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190531407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.4190531407 |
Directory | /workspace/20.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.3469914256 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 87355990 ps |
CPU time | 0.74 seconds |
Started | Jul 12 06:00:19 PM PDT 24 |
Finished | Jul 12 06:00:23 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-5382567d-e843-4558-86dc-b636846cf16d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469914256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3469914256 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.3860360783 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 70854047 ps |
CPU time | 0.79 seconds |
Started | Jul 12 06:00:14 PM PDT 24 |
Finished | Jul 12 06:00:17 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-ba836f29-79c1-4d8d-becc-5556f3b9660b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860360783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3860360783 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.2685840839 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 2523522823 ps |
CPU time | 2.96 seconds |
Started | Jul 12 06:00:19 PM PDT 24 |
Finished | Jul 12 06:00:25 PM PDT 24 |
Peak memory | 205396 kb |
Host | smart-a28e0486-1aa4-4f79-a582-187724978f66 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685840839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2685840839 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.1387032341 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 99874108 ps |
CPU time | 0.76 seconds |
Started | Jul 12 06:00:14 PM PDT 24 |
Finished | Jul 12 06:00:17 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-949a3a0a-194d-4a1a-bc12-518ed1070572 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387032341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1387032341 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.1763277064 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 2324870168 ps |
CPU time | 7.29 seconds |
Started | Jul 12 06:00:14 PM PDT 24 |
Finished | Jul 12 06:00:24 PM PDT 24 |
Peak memory | 205416 kb |
Host | smart-32cb132c-d408-4aa1-924e-1e5fafa8a9a7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763277064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1763277064 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.1828543572 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 27598316 ps |
CPU time | 0.73 seconds |
Started | Jul 12 06:00:17 PM PDT 24 |
Finished | Jul 12 06:00:21 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-0711defa-85ac-41de-a834-179876789c9a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828543572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1828543572 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.1115025953 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 48390280 ps |
CPU time | 0.74 seconds |
Started | Jul 12 06:00:15 PM PDT 24 |
Finished | Jul 12 06:00:17 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-59ebb7fb-2ffb-4764-9746-3c17d278b818 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115025953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1115025953 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.3175221435 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 1450326526 ps |
CPU time | 4.98 seconds |
Started | Jul 12 06:00:14 PM PDT 24 |
Finished | Jul 12 06:00:21 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-b771b890-29bc-45d9-abda-3abe51a2847c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175221435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3175221435 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.3583461695 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 156397702 ps |
CPU time | 1.13 seconds |
Started | Jul 12 06:00:20 PM PDT 24 |
Finished | Jul 12 06:00:24 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-4e397168-351c-4159-96aa-b910bd50eef8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583461695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3583461695 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.1682986073 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 5705269429 ps |
CPU time | 8.86 seconds |
Started | Jul 12 06:00:13 PM PDT 24 |
Finished | Jul 12 06:00:24 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-278ca3b4-78b7-4509-8164-fa8f4a78719a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682986073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1682986073 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.533370810 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 72227729 ps |
CPU time | 0.73 seconds |
Started | Jul 12 06:00:14 PM PDT 24 |
Finished | Jul 12 06:00:16 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-c29a96b9-7438-4792-8019-236667875469 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533370810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.533370810 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.3280190391 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 11482285104 ps |
CPU time | 29.84 seconds |
Started | Jul 12 06:00:17 PM PDT 24 |
Finished | Jul 12 06:00:49 PM PDT 24 |
Peak memory | 213568 kb |
Host | smart-4d39dedd-bae5-4e0b-94e3-10e2ca8ef9b4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280190391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3280190391 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.2207315462 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 84513352 ps |
CPU time | 0.82 seconds |
Started | Jul 12 06:00:15 PM PDT 24 |
Finished | Jul 12 06:00:18 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-1733e83c-206d-4f74-8021-d5c0b9ce68c3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207315462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2207315462 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.2426857863 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 5283555633 ps |
CPU time | 14.9 seconds |
Started | Jul 12 06:00:13 PM PDT 24 |
Finished | Jul 12 06:00:30 PM PDT 24 |
Peak memory | 205448 kb |
Host | smart-2623143a-7497-44cf-9460-38ccae5ca31b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426857863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2426857863 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.857575261 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 159756430 ps |
CPU time | 0.79 seconds |
Started | Jul 12 06:00:16 PM PDT 24 |
Finished | Jul 12 06:00:19 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-89f65bab-c3a6-4a03-afb2-9630f7e1333b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857575261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.857575261 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.3998840944 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 46427606 ps |
CPU time | 0.72 seconds |
Started | Jul 12 05:59:50 PM PDT 24 |
Finished | Jul 12 05:59:52 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-5071620e-7a41-4a78-afd8-ae424551de67 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998840944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3998840944 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2923272210 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 14624348702 ps |
CPU time | 39.53 seconds |
Started | Jul 12 05:59:49 PM PDT 24 |
Finished | Jul 12 06:00:29 PM PDT 24 |
Peak memory | 213740 kb |
Host | smart-838bd820-6bc3-4645-a901-bf8d1dcee5fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923272210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2923272210 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.570540925 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 10189958359 ps |
CPU time | 15.1 seconds |
Started | Jul 12 06:00:10 PM PDT 24 |
Finished | Jul 12 06:00:27 PM PDT 24 |
Peak memory | 213540 kb |
Host | smart-462e319b-58e2-4531-849d-440530d6e1a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=570540925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.570540925 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3337739489 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 4984022364 ps |
CPU time | 4.95 seconds |
Started | Jul 12 05:59:49 PM PDT 24 |
Finished | Jul 12 05:59:55 PM PDT 24 |
Peak memory | 213720 kb |
Host | smart-237b91c4-6d2d-40f9-9b2b-f6d51336a33d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3337739489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.3337739489 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.3242645438 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 477966459 ps |
CPU time | 1.3 seconds |
Started | Jul 12 05:59:50 PM PDT 24 |
Finished | Jul 12 05:59:52 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-0a70dd66-094b-4c33-af04-a78babe4e0a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3242645438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3242645438 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.3044457910 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 942565525 ps |
CPU time | 2.37 seconds |
Started | Jul 12 05:59:54 PM PDT 24 |
Finished | Jul 12 05:59:57 PM PDT 24 |
Peak memory | 228736 kb |
Host | smart-733c103e-4f4b-4999-919d-06735e837902 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044457910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3044457910 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.2645456903 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 4479364387 ps |
CPU time | 13.69 seconds |
Started | Jul 12 06:03:45 PM PDT 24 |
Finished | Jul 12 06:04:00 PM PDT 24 |
Peak memory | 213496 kb |
Host | smart-30ce9f83-4051-4769-8849-6653cf8398ac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645456903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2645456903 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.802618260 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 84701943 ps |
CPU time | 0.79 seconds |
Started | Jul 12 06:00:18 PM PDT 24 |
Finished | Jul 12 06:00:21 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-b33dd5ed-eba9-4741-9889-5e39302c80ca |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802618260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.802618260 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.2023896955 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 94380085 ps |
CPU time | 0.89 seconds |
Started | Jul 12 06:00:13 PM PDT 24 |
Finished | Jul 12 06:00:15 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-26a31d11-d343-4182-8ae5-14aa6d242e52 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023896955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2023896955 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.2514422082 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 5724622763 ps |
CPU time | 5.96 seconds |
Started | Jul 12 06:00:12 PM PDT 24 |
Finished | Jul 12 06:00:18 PM PDT 24 |
Peak memory | 221772 kb |
Host | smart-e74ecf1e-b9e4-4fdf-8987-f9943649698d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514422082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2514422082 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.364377125 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 39474810 ps |
CPU time | 0.75 seconds |
Started | Jul 12 06:00:17 PM PDT 24 |
Finished | Jul 12 06:00:21 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-c4ab50fa-57d9-43f9-8d04-04364b807784 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364377125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.364377125 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.1757399995 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 9150258944 ps |
CPU time | 24.5 seconds |
Started | Jul 12 06:00:16 PM PDT 24 |
Finished | Jul 12 06:00:43 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-bc453c8b-1fff-4f0f-847f-147d0c13f5b4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757399995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1757399995 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.2499908306 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 94228752 ps |
CPU time | 0.95 seconds |
Started | Jul 12 06:00:12 PM PDT 24 |
Finished | Jul 12 06:00:14 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-686b2120-deed-4a0f-94ae-8b58368cffea |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499908306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2499908306 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.318039283 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 133955001 ps |
CPU time | 0.73 seconds |
Started | Jul 12 06:00:22 PM PDT 24 |
Finished | Jul 12 06:00:26 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-faa519de-6c73-43c4-9464-75be1fdc3d3a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318039283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.318039283 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.1113952484 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 3597705532 ps |
CPU time | 5.12 seconds |
Started | Jul 12 06:00:19 PM PDT 24 |
Finished | Jul 12 06:00:27 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-5d9e2953-aab1-4acc-9711-390cf59438db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113952484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1113952484 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.2324296226 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 61141143 ps |
CPU time | 0.83 seconds |
Started | Jul 12 06:00:17 PM PDT 24 |
Finished | Jul 12 06:00:21 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-4638c9a0-5aaa-4e58-87ac-dec73a171b38 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324296226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2324296226 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.3699561255 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 5600641064 ps |
CPU time | 8.9 seconds |
Started | Jul 12 06:00:13 PM PDT 24 |
Finished | Jul 12 06:00:23 PM PDT 24 |
Peak memory | 214668 kb |
Host | smart-52d9a21b-1010-4561-88de-54a4bc265584 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699561255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3699561255 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.1443540346 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 58407911 ps |
CPU time | 0.8 seconds |
Started | Jul 12 06:00:23 PM PDT 24 |
Finished | Jul 12 06:00:27 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-cbedfbc8-2315-4150-b79d-e9a42c735e16 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443540346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1443540346 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.2841793031 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 83611461 ps |
CPU time | 0.79 seconds |
Started | Jul 12 06:00:17 PM PDT 24 |
Finished | Jul 12 06:00:21 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-74b4d69a-f9b8-4b04-a850-fcb2ae2b66a5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841793031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2841793031 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.3546086649 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 12368514477 ps |
CPU time | 10.52 seconds |
Started | Jul 12 06:00:15 PM PDT 24 |
Finished | Jul 12 06:00:28 PM PDT 24 |
Peak memory | 213560 kb |
Host | smart-70ee5fbe-41bd-427f-96dc-24520ee15e3e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546086649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3546086649 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.1370475989 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 137751116 ps |
CPU time | 0.79 seconds |
Started | Jul 12 06:00:15 PM PDT 24 |
Finished | Jul 12 06:00:18 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-fafe233d-22b7-4f3a-b77a-0656e4348fb5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370475989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1370475989 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.3433680310 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 3651079851 ps |
CPU time | 6.43 seconds |
Started | Jul 12 06:00:15 PM PDT 24 |
Finished | Jul 12 06:00:23 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-5b65b7af-c728-4651-a2ec-c7290f7f5494 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433680310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3433680310 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.3409185840 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 39539504 ps |
CPU time | 0.8 seconds |
Started | Jul 12 06:00:14 PM PDT 24 |
Finished | Jul 12 06:00:16 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-500bd256-8b40-430f-9e97-c44036301017 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409185840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3409185840 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.3385423004 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 7980540823 ps |
CPU time | 7.47 seconds |
Started | Jul 12 06:00:17 PM PDT 24 |
Finished | Jul 12 06:00:28 PM PDT 24 |
Peak memory | 205396 kb |
Host | smart-06965293-40a2-4586-a599-e40315fc2bf5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385423004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3385423004 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.3109647200 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 41036145 ps |
CPU time | 0.83 seconds |
Started | Jul 12 05:59:54 PM PDT 24 |
Finished | Jul 12 05:59:56 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-1d411d4f-6fb6-4566-90e5-ba10443d7a58 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109647200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3109647200 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3918649875 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 8864064045 ps |
CPU time | 8.24 seconds |
Started | Jul 12 05:59:52 PM PDT 24 |
Finished | Jul 12 06:00:01 PM PDT 24 |
Peak memory | 205552 kb |
Host | smart-0d37ef4d-bdb2-45a8-ab93-3988bb541588 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3918649875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3918649875 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.779248628 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 2560666719 ps |
CPU time | 4.54 seconds |
Started | Jul 12 05:59:51 PM PDT 24 |
Finished | Jul 12 05:59:56 PM PDT 24 |
Peak memory | 213668 kb |
Host | smart-10372ea7-9ed6-4113-86da-13887373b541 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=779248628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.779248628 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2361920728 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 1630785546 ps |
CPU time | 1.77 seconds |
Started | Jul 12 05:59:51 PM PDT 24 |
Finished | Jul 12 05:59:54 PM PDT 24 |
Peak memory | 205460 kb |
Host | smart-aa6f994f-028e-4fab-af87-2d2b6862fcd3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2361920728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.2361920728 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.3955499941 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 435004485 ps |
CPU time | 1.01 seconds |
Started | Jul 12 06:00:07 PM PDT 24 |
Finished | Jul 12 06:00:10 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-0efeac13-4579-4a9c-923f-62e32d88624e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3955499941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3955499941 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.1309394707 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 8859162738 ps |
CPU time | 7.21 seconds |
Started | Jul 12 05:59:53 PM PDT 24 |
Finished | Jul 12 06:00:01 PM PDT 24 |
Peak memory | 205404 kb |
Host | smart-43ccff6f-68d4-4e16-9384-547e11976218 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1309394707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1309394707 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.770621069 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 2859090541 ps |
CPU time | 4.69 seconds |
Started | Jul 12 05:59:50 PM PDT 24 |
Finished | Jul 12 05:59:55 PM PDT 24 |
Peak memory | 229296 kb |
Host | smart-52daa0e3-9beb-4d55-9b60-c66e75d83c55 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770621069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.770621069 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.3889867621 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 119420399 ps |
CPU time | 0.84 seconds |
Started | Jul 12 06:00:17 PM PDT 24 |
Finished | Jul 12 06:00:20 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-cdcff4d9-5654-44f4-a8f3-b5f811558ed7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889867621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3889867621 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.438274248 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 16402824035 ps |
CPU time | 42.78 seconds |
Started | Jul 12 06:00:22 PM PDT 24 |
Finished | Jul 12 06:01:08 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-8ee01e10-ccf7-4409-abf9-858a2aa98e70 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438274248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.438274248 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.2001281802 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 242245015 ps |
CPU time | 0.73 seconds |
Started | Jul 12 06:00:18 PM PDT 24 |
Finished | Jul 12 06:00:21 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-c7e57d06-50bc-4692-b423-9b0ba91c6d9f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001281802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2001281802 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.3349165078 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 84482959 ps |
CPU time | 0.89 seconds |
Started | Jul 12 06:00:18 PM PDT 24 |
Finished | Jul 12 06:00:21 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-aada895c-7d10-4173-b83d-3ced718f22c0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349165078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3349165078 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.4080938051 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 39821264 ps |
CPU time | 0.69 seconds |
Started | Jul 12 06:00:23 PM PDT 24 |
Finished | Jul 12 06:00:26 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-bef225ec-d393-4f11-895f-3bb2f3cb6ea7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080938051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.4080938051 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.1902126522 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 7323120947 ps |
CPU time | 7.28 seconds |
Started | Jul 12 06:00:15 PM PDT 24 |
Finished | Jul 12 06:00:24 PM PDT 24 |
Peak memory | 213452 kb |
Host | smart-0878c6fc-f1b9-48b0-9fb6-a4dc3f2d5f49 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902126522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1902126522 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.342955291 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 76947442 ps |
CPU time | 0.73 seconds |
Started | Jul 12 06:00:13 PM PDT 24 |
Finished | Jul 12 06:00:14 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-fe70478d-1ad3-4105-b357-0aab278bc2a0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342955291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.342955291 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_stress_all.1044863291 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 3596859688 ps |
CPU time | 10.09 seconds |
Started | Jul 12 06:00:19 PM PDT 24 |
Finished | Jul 12 06:00:32 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-4b2bc93b-afab-47b5-a0f8-948bd67ce82c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044863291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1044863291 |
Directory | /workspace/45.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.2349026302 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 31992472 ps |
CPU time | 0.77 seconds |
Started | Jul 12 06:00:17 PM PDT 24 |
Finished | Jul 12 06:00:20 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-bba7fb0e-f88f-44d4-a6f9-215da22c3750 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349026302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2349026302 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.324751013 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 2515838408 ps |
CPU time | 3.03 seconds |
Started | Jul 12 06:00:25 PM PDT 24 |
Finished | Jul 12 06:00:31 PM PDT 24 |
Peak memory | 205500 kb |
Host | smart-fec465e5-591e-4bde-8143-69932dd6ef03 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324751013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.324751013 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.3561806595 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 30805746 ps |
CPU time | 0.77 seconds |
Started | Jul 12 06:00:18 PM PDT 24 |
Finished | Jul 12 06:00:21 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-e5d34e1d-5eae-4787-b397-fd90ea293fc2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561806595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3561806595 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_stress_all.3762294936 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 7333759603 ps |
CPU time | 11.25 seconds |
Started | Jul 12 06:00:22 PM PDT 24 |
Finished | Jul 12 06:00:37 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-67ce2652-b442-48fc-968c-0fc63886e836 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762294936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3762294936 |
Directory | /workspace/47.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.3807688655 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 37431637 ps |
CPU time | 0.81 seconds |
Started | Jul 12 06:00:22 PM PDT 24 |
Finished | Jul 12 06:00:26 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-51fb944c-95a9-4242-a513-2bcb76f33d25 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807688655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3807688655 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.1105105492 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 209237671 ps |
CPU time | 0.71 seconds |
Started | Jul 12 06:00:29 PM PDT 24 |
Finished | Jul 12 06:00:32 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-2dee378d-a7e5-4824-a140-575c0c543f05 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105105492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1105105492 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.3621219718 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 3248475834 ps |
CPU time | 9.76 seconds |
Started | Jul 12 06:00:29 PM PDT 24 |
Finished | Jul 12 06:00:40 PM PDT 24 |
Peak memory | 205380 kb |
Host | smart-b1246578-5f8d-4305-8d16-2bc2e642acc8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621219718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3621219718 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.3943425523 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 174119300 ps |
CPU time | 0.79 seconds |
Started | Jul 12 05:59:57 PM PDT 24 |
Finished | Jul 12 06:00:00 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-c5682dcd-7773-4814-8f67-52226a78bcbb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943425523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3943425523 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1516935669 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 4661610199 ps |
CPU time | 4.18 seconds |
Started | Jul 12 05:59:52 PM PDT 24 |
Finished | Jul 12 05:59:57 PM PDT 24 |
Peak memory | 215436 kb |
Host | smart-5a269e4a-0c22-4a54-b9a0-fa6fbd3fd223 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1516935669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1516935669 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2635873065 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 13186401904 ps |
CPU time | 11 seconds |
Started | Jul 12 05:59:51 PM PDT 24 |
Finished | Jul 12 06:00:03 PM PDT 24 |
Peak memory | 221796 kb |
Host | smart-b8e5f627-1555-4b5d-b49c-5fe760e5de43 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2635873065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t l_access.2635873065 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.877305207 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 6128118456 ps |
CPU time | 16.46 seconds |
Started | Jul 12 05:59:52 PM PDT 24 |
Finished | Jul 12 06:00:09 PM PDT 24 |
Peak memory | 205644 kb |
Host | smart-85357322-9b3e-41da-a5b5-c2490c353a2e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877305207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.877305207 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.3051349719 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 1750642517 ps |
CPU time | 6.16 seconds |
Started | Jul 12 05:59:58 PM PDT 24 |
Finished | Jul 12 06:00:06 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-39cf6055-8955-4414-8b77-dcca12bb7dc1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051349719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3051349719 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.1007206520 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 37498350 ps |
CPU time | 0.77 seconds |
Started | Jul 12 05:59:56 PM PDT 24 |
Finished | Jul 12 06:00:00 PM PDT 24 |
Peak memory | 205088 kb |
Host | smart-b915a612-c744-4abe-a7fa-b44663f4f8bc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007206520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1007206520 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1468809141 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 4051716872 ps |
CPU time | 3.64 seconds |
Started | Jul 12 05:59:57 PM PDT 24 |
Finished | Jul 12 06:00:03 PM PDT 24 |
Peak memory | 205580 kb |
Host | smart-eb12191e-6c71-4939-bbd5-f98ad072c2d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1468809141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1468809141 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2944830777 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 2516118686 ps |
CPU time | 4.68 seconds |
Started | Jul 12 05:59:58 PM PDT 24 |
Finished | Jul 12 06:00:06 PM PDT 24 |
Peak memory | 205496 kb |
Host | smart-c781e1e9-e33a-4329-b827-c740c70e1636 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2944830777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2944830777 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.908250857 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 2958137275 ps |
CPU time | 2.76 seconds |
Started | Jul 12 05:59:55 PM PDT 24 |
Finished | Jul 12 06:00:00 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-53db6e30-2029-45be-8f5f-58b9083ad65e |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=908250857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl _access.908250857 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.2657095210 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 1356496434 ps |
CPU time | 1.48 seconds |
Started | Jul 12 05:59:55 PM PDT 24 |
Finished | Jul 12 05:59:58 PM PDT 24 |
Peak memory | 205496 kb |
Host | smart-0ed53909-021c-4cea-bd73-8f6dc23ba237 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2657095210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2657095210 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.4282746768 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 3600864068 ps |
CPU time | 7.46 seconds |
Started | Jul 12 05:59:57 PM PDT 24 |
Finished | Jul 12 06:00:07 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-9ffc5037-a1a9-4559-bb10-84467ac4a3f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282746768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.4282746768 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.492755144 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 110125032 ps |
CPU time | 0.75 seconds |
Started | Jul 12 05:59:57 PM PDT 24 |
Finished | Jul 12 06:00:00 PM PDT 24 |
Peak memory | 205088 kb |
Host | smart-da3111f0-5371-40e5-b0df-92076cb80649 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492755144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.492755144 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3059568422 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 20845453939 ps |
CPU time | 24.16 seconds |
Started | Jul 12 05:59:56 PM PDT 24 |
Finished | Jul 12 06:00:23 PM PDT 24 |
Peak memory | 213704 kb |
Host | smart-9f660de2-c320-41e1-82ef-088a04ea5673 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3059568422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3059568422 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2503769377 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 3746789530 ps |
CPU time | 3.97 seconds |
Started | Jul 12 05:59:56 PM PDT 24 |
Finished | Jul 12 06:00:03 PM PDT 24 |
Peak memory | 213696 kb |
Host | smart-5dea627b-2c2d-49a3-b6a5-921c2f009337 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2503769377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2503769377 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.4202699659 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 8700026829 ps |
CPU time | 25.25 seconds |
Started | Jul 12 05:59:55 PM PDT 24 |
Finished | Jul 12 06:00:22 PM PDT 24 |
Peak memory | 213684 kb |
Host | smart-e250e999-4eda-4a40-9146-e99941e7f67b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4202699659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.4202699659 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.2808875043 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 6302117283 ps |
CPU time | 3.46 seconds |
Started | Jul 12 05:59:56 PM PDT 24 |
Finished | Jul 12 06:00:02 PM PDT 24 |
Peak memory | 205428 kb |
Host | smart-2386e594-63bb-45fc-a7e6-5012e800e292 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808875043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2808875043 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.975136225 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 40081151 ps |
CPU time | 0.78 seconds |
Started | Jul 12 05:59:58 PM PDT 24 |
Finished | Jul 12 06:00:01 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-5c29f87c-3338-48ba-9f85-31fe31337ab7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975136225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.975136225 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3482622344 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 67711990547 ps |
CPU time | 47.37 seconds |
Started | Jul 12 05:59:57 PM PDT 24 |
Finished | Jul 12 06:00:47 PM PDT 24 |
Peak memory | 213808 kb |
Host | smart-7257aa0b-7cde-4970-89ec-e2fa1fe52580 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3482622344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3482622344 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3038417030 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 5175405537 ps |
CPU time | 8.03 seconds |
Started | Jul 12 06:00:10 PM PDT 24 |
Finished | Jul 12 06:00:20 PM PDT 24 |
Peak memory | 213132 kb |
Host | smart-aa3776e4-11ce-47f1-99a7-7475ac66608a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3038417030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3038417030 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3085031148 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 3824151400 ps |
CPU time | 11.82 seconds |
Started | Jul 12 05:59:57 PM PDT 24 |
Finished | Jul 12 06:00:11 PM PDT 24 |
Peak memory | 213728 kb |
Host | smart-33a05c8c-b8e8-413b-b9de-cd73d0f3fe16 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3085031148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t l_access.3085031148 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.2228071768 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 1942507364 ps |
CPU time | 2.84 seconds |
Started | Jul 12 05:59:56 PM PDT 24 |
Finished | Jul 12 06:00:02 PM PDT 24 |
Peak memory | 213624 kb |
Host | smart-cd1ec252-d0cf-47e9-9132-71bc5543a179 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228071768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2228071768 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.1491229913 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 47222397 ps |
CPU time | 0.82 seconds |
Started | Jul 12 06:00:02 PM PDT 24 |
Finished | Jul 12 06:00:05 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-3ef0abe2-9075-4272-8761-e1bc9bcba581 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491229913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1491229913 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.894528215 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 2635290651 ps |
CPU time | 8 seconds |
Started | Jul 12 05:59:55 PM PDT 24 |
Finished | Jul 12 06:00:05 PM PDT 24 |
Peak memory | 213644 kb |
Host | smart-0a293ff4-f327-479d-9892-5822ff978174 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=894528215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.894528215 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1747528894 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 6905741590 ps |
CPU time | 9.66 seconds |
Started | Jul 12 06:00:01 PM PDT 24 |
Finished | Jul 12 06:00:13 PM PDT 24 |
Peak memory | 213752 kb |
Host | smart-d4874fac-19a8-4418-a77f-4861f1079ac3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1747528894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.1747528894 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.3779513271 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 4000873577 ps |
CPU time | 6.45 seconds |
Started | Jul 12 05:59:56 PM PDT 24 |
Finished | Jul 12 06:00:06 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-d4e51b9f-5bb2-4c35-a483-b8565a6a95f7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779513271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3779513271 |
Directory | /workspace/9.rv_dm_stress_all/latest |
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