Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	209039	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	586318	1		T3	1		T4	19		T5	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	485805	1		T4	19		T5	1		T6	8
values[0x0]	150246	1		T3	1		T4	14		T5	2
values[0x1]	159306	1		T3	1		T4	11		T5	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	158398	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	636959	1		T3	1		T4	22		T5	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3185	1		T35	6		T135	1		T27	1
valid_sources[0x01]	3371	1		T68	19		T70	143		T69	1
valid_sources[0x02]	3519	1		T144	1		T42	3		T68	16
valid_sources[0x03]	3238	1		T6	9		T30	2		T42	1
valid_sources[0x04]	3217	1		T183	1		T68	22		T70	121
valid_sources[0x05]	3305	1		T132	1		T68	24		T70	142
valid_sources[0x06]	2997	1		T7	2		T42	1		T24	1
valid_sources[0x07]	3328	1		T183	1		T68	33		T70	144
valid_sources[0x08]	2938	1		T11	1		T42	1		T27	1
valid_sources[0x09]	3083	1		T135	2		T184	2		T131	1
valid_sources[0x0a]	2987	1		T7	3		T30	1		T68	28
valid_sources[0x0b]	2971	1		T17	2		T135	3		T129	1
valid_sources[0x0c]	2856	1		T133	1		T146	1		T68	17
valid_sources[0x0d]	3102	1		T45	2		T42	1		T183	1
valid_sources[0x0e]	3128	1		T132	1		T68	22		T70	132
valid_sources[0x0f]	3208	1		T4	44		T42	1		T131	1
valid_sources[0x10]	2983	1		T12	14		T45	6		T126	2
valid_sources[0x11]	2834	1		T148	31		T68	19		T70	134
valid_sources[0x12]	3456	1		T143	1		T45	2		T42	1
valid_sources[0x13]	2765	1		T142	2		T68	18		T70	126
valid_sources[0x14]	2915	1		T65	2		T43	1		T68	18
valid_sources[0x15]	2778	1		T137	3		T129	5		T68	22
valid_sources[0x16]	3219	1		T17	1		T144	1		T43	4
valid_sources[0x17]	2687	1		T42	1		T24	1		T132	2
valid_sources[0x18]	2776	1		T25	1		T144	1		T19	1
valid_sources[0x19]	2757	1		T25	1		T183	2		T68	17
valid_sources[0x1a]	3099	1		T42	1		T43	13		T68	20
valid_sources[0x1b]	2947	1		T68	15		T70	130		T69	1
valid_sources[0x1c]	2946	1		T68	27		T70	136		T69	1
valid_sources[0x1d]	3177	1		T42	1		T142	3		T68	39
valid_sources[0x1e]	2981	1		T13	1		T23	1		T68	14
valid_sources[0x1f]	3256	1		T17	1		T68	10		T70	144
valid_sources[0x20]	3628	1		T131	1		T68	15		T70	139
valid_sources[0x21]	2717	1		T135	3		T68	27		T70	156
valid_sources[0x22]	2707	1		T42	1		T183	1		T68	13
valid_sources[0x23]	2851	1		T133	1		T42	1		T183	1
valid_sources[0x24]	2926	1		T25	1		T126	1		T68	34
valid_sources[0x25]	2990	1		T167	14		T125	1		T128	6
valid_sources[0x26]	2681	1		T185	5		T183	1		T132	2
valid_sources[0x27]	3793	1		T135	1		T184	1		T68	28
valid_sources[0x28]	3750	1		T17	1		T125	4		T68	23
valid_sources[0x29]	3112	1		T42	1		T129	1		T130	1
valid_sources[0x2a]	2918	1		T30	4		T45	3		T137	3
valid_sources[0x2b]	3298	1		T125	5		T42	1		T46	1
valid_sources[0x2c]	2787	1		T186	1		T68	27		T70	118
valid_sources[0x2d]	2869	1		T142	1		T68	33		T70	115
valid_sources[0x2e]	3238	1		T42	3		T68	25		T70	140
valid_sources[0x2f]	3224	1		T183	1		T127	2		T146	3
valid_sources[0x30]	2790	1		T68	27		T70	124		T69	5
valid_sources[0x31]	2830	1		T17	2		T29	1		T47	2
valid_sources[0x32]	2865	1		T17	1		T68	39		T70	121
valid_sources[0x33]	3792	1		T131	1		T146	1		T47	2
valid_sources[0x34]	2897	1		T22	1		T129	1		T187	2
valid_sources[0x35]	3097	1		T135	1		T27	2		T68	21
valid_sources[0x36]	3053	1		T68	28		T70	132		T69	1
valid_sources[0x37]	2843	1		T25	1		T45	1		T132	1
valid_sources[0x38]	2873	1		T3	2		T45	1		T27	1
valid_sources[0x39]	3063	1		T39	1		T68	21		T70	152
valid_sources[0x3a]	3057	1		T135	4		T188	1		T68	20
valid_sources[0x3b]	3075	1		T42	1		T131	1		T68	28
valid_sources[0x3c]	3132	1		T68	29		T70	141		T69	3
valid_sources[0x3d]	2923	1		T68	20		T70	118		T69	2
valid_sources[0x3e]	3214	1		T17	1		T68	13		T70	138
valid_sources[0x3f]	2995	1		T134	1		T142	1		T28	2
valid_sources[0x40]	3066	1		T133	1		T19	2		T68	20
valid_sources[0x41]	2901	1		T68	29		T70	145		T55	2
valid_sources[0x42]	3169	1		T129	2		T27	3		T127	1
valid_sources[0x43]	2778	1		T183	1		T132	1		T68	36
valid_sources[0x44]	3125	1		T22	2		T132	1		T68	25
valid_sources[0x45]	3127	1		T17	1		T45	1		T24	1
valid_sources[0x46]	2921	1		T17	1		T133	1		T27	1
valid_sources[0x47]	2762	1		T21	1		T27	1		T68	28
valid_sources[0x48]	2719	1		T26	2		T43	1		T68	21
valid_sources[0x49]	3092	1		T17	1		T68	31		T70	131
valid_sources[0x4a]	3228	1		T68	29		T70	145		T69	7
valid_sources[0x4b]	2884	1		T42	1		T129	2		T27	2
valid_sources[0x4c]	2787	1		T23	2		T24	2		T68	36
valid_sources[0x4d]	2935	1		T25	1		T133	1		T26	1
valid_sources[0x4e]	3398	1		T132	1		T68	29		T70	133
valid_sources[0x4f]	2980	1		T129	2		T47	1		T68	29
valid_sources[0x50]	3474	1		T68	29		T70	125		T55	4
valid_sources[0x51]	2749	1		T68	22		T70	134		T69	4
valid_sources[0x52]	2670	1		T17	1		T144	1		T42	2
valid_sources[0x53]	3371	1		T144	1		T68	24		T70	137
valid_sources[0x54]	5908	1		T135	1		T27	2		T68	37
valid_sources[0x55]	3206	1		T42	1		T68	33		T70	165
valid_sources[0x56]	3153	1		T189	16		T132	2		T68	24
valid_sources[0x57]	3907	1		T68	17		T70	142		T69	3
valid_sources[0x58]	3096	1		T42	1		T46	2		T68	14
valid_sources[0x59]	2947	1		T183	2		T132	2		T68	18
valid_sources[0x5a]	3058	1		T5	7		T7	1		T42	1
valid_sources[0x5b]	2963	1		T27	1		T146	1		T132	1
valid_sources[0x5c]	3117	1		T144	1		T131	2		T27	5
valid_sources[0x5d]	2970	1		T45	2		T68	28		T70	148
valid_sources[0x5e]	3026	1		T129	2		T43	5		T68	17
valid_sources[0x5f]	2800	1		T68	23		T70	143		T69	1
valid_sources[0x60]	2908	1		T42	1		T27	1		T68	30
valid_sources[0x61]	2667	1		T68	17		T70	147		T69	2
valid_sources[0x62]	2871	1		T25	1		T184	1		T183	1
valid_sources[0x63]	3067	1		T126	1		T68	42		T70	111
valid_sources[0x64]	3104	1		T129	2		T68	26		T70	157
valid_sources[0x65]	3706	1		T42	1		T146	1		T132	1
valid_sources[0x66]	2836	1		T137	1		T42	2		T27	2
valid_sources[0x67]	3281	1		T132	1		T187	1		T68	20
valid_sources[0x68]	3025	1		T42	1		T132	1		T68	8
valid_sources[0x69]	3197	1		T68	21		T70	142		T69	2
valid_sources[0x6a]	2847	1		T17	1		T42	1		T129	1
valid_sources[0x6b]	3469	1		T147	1		T131	1		T24	1
valid_sources[0x6c]	3076	1		T135	1		T68	38		T70	135
valid_sources[0x6d]	3292	1		T190	2		T146	1		T68	26
valid_sources[0x6e]	3335	1		T17	1		T68	17		T70	149
valid_sources[0x6f]	3159	1		T137	4		T142	1		T68	32
valid_sources[0x70]	2861	1		T42	1		T68	30		T70	137
valid_sources[0x71]	3241	1		T26	2		T129	2		T183	1
valid_sources[0x72]	3603	1		T138	18		T68	20		T70	108
valid_sources[0x73]	2944	1		T131	1		T27	1		T183	1
valid_sources[0x74]	2750	1		T134	1		T135	6		T27	5
valid_sources[0x75]	2924	1		T43	1		T68	11		T70	131
valid_sources[0x76]	2961	1		T42	2		T129	2		T183	1
valid_sources[0x77]	3192	1		T19	1		T68	21		T70	139
valid_sources[0x78]	3177	1		T68	23		T70	145		T55	1
valid_sources[0x79]	2834	1		T42	1		T126	3		T132	1
valid_sources[0x7a]	3180	1		T135	1		T68	24		T70	139
valid_sources[0x7b]	2637	1		T68	41		T70	123		T55	4
valid_sources[0x7c]	2917	1		T42	1		T68	13		T70	140
valid_sources[0x7d]	3013	1		T24	1		T68	24		T70	146
valid_sources[0x7e]	3507	1		T42	1		T68	15		T70	144
valid_sources[0x7f]	2710	1		T137	1		T68	31		T70	121
valid_sources[0x80]	2775	1		T17	1		T42	1		T131	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

290300

1

T4

13

T5

1

T6

5

values[0x0]

all_enables

biggest_size

147848

1

T3

1

T4

4

T5

1

values[0x1]

all_enables

biggest_size

148170

1

T4

2

T5

1

T34

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5360	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	25697	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11141	1		T68	33		T70	192		T69	3
values[0x0]	9717	1		T1	5		T48	1		T49	6
values[0x1]	10199	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3991	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	27066	1		T1	3		T2	1		T3	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	94	1		T5	8		T191	1		T141	1
valid_sources[0x01]	70	1		T134	1		T192	1		T88	1
valid_sources[0x02]	189	1		T193	1		T194	2		T195	19
valid_sources[0x03]	104	1		T143	2		T67	1		T88	3
valid_sources[0x04]	72	1		T196	1		T56	8		T89	2
valid_sources[0x05]	92	1		T197	1		T196	1		T67	1
valid_sources[0x06]	61	1		T51	1		T198	1		T133	1
valid_sources[0x07]	205	1		T199	2		T200	1		T201	1
valid_sources[0x08]	101	1		T31	1		T17	3		T202	2
valid_sources[0x09]	62	1		T68	1		T88	3		T56	3
valid_sources[0x0a]	175	1		T141	3		T203	1		T56	8
valid_sources[0x0b]	674	1		T71	1		T68	1		T70	384
valid_sources[0x0c]	56	1		T76	1		T67	1		T88	2
valid_sources[0x0d]	130	1		T4	1		T67	3		T56	3
valid_sources[0x0e]	164	1		T67	1		T56	3		T89	6
valid_sources[0x0f]	67	1		T76	1		T68	1		T67	1
valid_sources[0x10]	94	1		T204	1		T67	2		T88	2
valid_sources[0x11]	126	1		T49	2		T204	1		T205	1
valid_sources[0x12]	131	1		T75	1		T193	3		T197	2
valid_sources[0x13]	93	1		T48	1		T206	1		T130	1
valid_sources[0x14]	109	1		T157	1		T207	1		T68	1
valid_sources[0x15]	107	1		T88	1		T56	6		T89	4
valid_sources[0x16]	114	1		T49	2		T208	1		T137	2
valid_sources[0x17]	86	1		T36	1		T75	1		T76	1
valid_sources[0x18]	91	1		T164	1		T193	1		T125	1
valid_sources[0x19]	362	1		T76	1		T17	1		T209	5
valid_sources[0x1a]	118	1		T37	1		T210	1		T211	1
valid_sources[0x1b]	134	1		T20	1		T127	1		T29	1
valid_sources[0x1c]	87	1		T14	1		T212	2		T56	2
valid_sources[0x1d]	95	1		T76	1		T197	1		T67	1
valid_sources[0x1e]	144	1		T67	3		T56	4		T90	6
valid_sources[0x1f]	97	1		T20	1		T14	1		T204	1
valid_sources[0x20]	89	1		T26	3		T67	1		T88	1
valid_sources[0x21]	102	1		T37	4		T140	1		T201	1
valid_sources[0x22]	122	1		T213	1		T55	38		T88	5
valid_sources[0x23]	149	1		T10	1		T20	1		T68	1
valid_sources[0x24]	119	1		T75	1		T67	1		T56	8
valid_sources[0x25]	128	1		T75	1		T214	1		T215	13
valid_sources[0x26]	89	1		T193	1		T216	1		T217	2
valid_sources[0x27]	68	1		T42	1		T67	2		T56	2
valid_sources[0x28]	83	1		T158	7		T218	1		T26	1
valid_sources[0x29]	141	1		T219	1		T190	1		T138	3
valid_sources[0x2a]	79	1		T193	3		T150	1		T67	2
valid_sources[0x2b]	85	1		T220	1		T68	1		T67	1
valid_sources[0x2c]	216	1		T183	8		T221	4		T188	1
valid_sources[0x2d]	89	1		T133	1		T192	1		T67	1
valid_sources[0x2e]	107	1		T44	1		T192	1		T67	2
valid_sources[0x2f]	102	1		T134	1		T58	1		T22	1
valid_sources[0x30]	98	1		T141	1		T67	1		T55	19
valid_sources[0x31]	85	1		T67	2		T55	9		T88	3
valid_sources[0x32]	135	1		T1	7		T214	1		T67	2
valid_sources[0x33]	116	1		T51	1		T67	3		T88	3
valid_sources[0x34]	147	1		T218	1		T88	2		T56	5
valid_sources[0x35]	90	1		T152	1		T18	1		T196	1
valid_sources[0x36]	218	1		T222	3		T131	5		T56	5
valid_sources[0x37]	57	1		T68	1		T67	2		T56	9
valid_sources[0x38]	90	1		T14	1		T223	1		T67	1
valid_sources[0x39]	126	1		T67	1		T56	4		T89	6
valid_sources[0x3a]	373	1		T67	1		T56	5		T66	1
valid_sources[0x3b]	143	1		T48	1		T33	1		T163	2
valid_sources[0x3c]	108	1		T20	1		T202	1		T30	7
valid_sources[0x3d]	160	1		T67	3		T55	17		T56	9
valid_sources[0x3e]	101	1		T67	1		T88	1		T56	6
valid_sources[0x3f]	91	1		T67	3		T56	4		T89	4
valid_sources[0x40]	155	1		T76	1		T59	7		T224	1
valid_sources[0x41]	101	1		T191	1		T225	1		T67	1
valid_sources[0x42]	108	1		T9	1		T17	1		T191	1
valid_sources[0x43]	80	1		T20	1		T132	2		T88	1
valid_sources[0x44]	71	1		T67	1		T88	3		T56	6
valid_sources[0x45]	175	1		T68	1		T56	2		T89	4
valid_sources[0x46]	90	1		T144	2		T226	1		T189	5
valid_sources[0x47]	90	1		T202	1		T67	1		T88	3
valid_sources[0x48]	91	1		T216	1		T197	2		T227	1
valid_sources[0x49]	108	1		T165	7		T14	1		T136	1
valid_sources[0x4a]	90	1		T39	1		T228	1		T19	6
valid_sources[0x4b]	97	1		T71	1		T198	1		T68	1
valid_sources[0x4c]	89	1		T156	8		T198	1		T67	3
valid_sources[0x4d]	153	1		T204	1		T226	1		T138	2
valid_sources[0x4e]	93	1		T60	1		T198	1		T204	1
valid_sources[0x4f]	68	1		T218	1		T229	1		T67	1
valid_sources[0x50]	85	1		T166	1		T211	1		T192	1
valid_sources[0x51]	138	1		T226	1		T230	1		T56	10
valid_sources[0x52]	148	1		T4	1		T119	5		T56	12
valid_sources[0x53]	112	1		T68	1		T67	2		T56	12
valid_sources[0x54]	163	1		T75	1		T16	1		T67	2
valid_sources[0x55]	77	1		T220	1		T67	4		T56	4
valid_sources[0x56]	173	1		T231	20		T204	1		T56	7
valid_sources[0x57]	101	1		T232	1		T67	2		T88	1
valid_sources[0x58]	100	1		T119	1		T201	1		T88	9
valid_sources[0x59]	178	1		T88	5		T56	6		T89	6
valid_sources[0x5a]	75	1		T129	1		T67	3		T56	5
valid_sources[0x5b]	135	1		T202	2		T224	1		T56	7
valid_sources[0x5c]	129	1		T233	1		T67	1		T56	8
valid_sources[0x5d]	481	1		T234	1		T232	1		T166	1
valid_sources[0x5e]	110	1		T226	1		T235	6		T67	1
valid_sources[0x5f]	109	1		T236	1		T211	1		T88	2
valid_sources[0x60]	102	1		T197	1		T67	2		T56	4
valid_sources[0x61]	100	1		T13	9		T132	1		T139	1
valid_sources[0x62]	138	1		T197	1		T47	1		T68	1
valid_sources[0x63]	91	1		T49	5		T224	1		T210	1
valid_sources[0x64]	101	1		T76	1		T162	1		T68	1
valid_sources[0x65]	117	1		T237	17		T207	1		T153	1
valid_sources[0x66]	105	1		T238	1		T133	1		T134	1
valid_sources[0x67]	171	1		T68	2		T88	1		T56	4
valid_sources[0x68]	116	1		T239	2		T185	1		T67	4
valid_sources[0x69]	152	1		T40	1		T240	1		T211	1
valid_sources[0x6a]	94	1		T62	1		T225	1		T166	1
valid_sources[0x6b]	72	1		T20	1		T226	1		T67	1
valid_sources[0x6c]	78	1		T11	1		T65	1		T216	1
valid_sources[0x6d]	87	1		T33	2		T193	1		T223	3
valid_sources[0x6e]	119	1		T76	1		T68	1		T67	1
valid_sources[0x6f]	93	1		T76	1		T241	1		T88	4
valid_sources[0x70]	66	1		T226	1		T67	3		T56	8
valid_sources[0x71]	121	1		T242	13		T239	5		T243	16
valid_sources[0x72]	83	1		T68	1		T67	1		T56	3
valid_sources[0x73]	84	1		T244	9		T21	5		T206	1
valid_sources[0x74]	145	1		T7	1		T212	1		T23	1
valid_sources[0x75]	111	1		T207	1		T245	1		T67	3
valid_sources[0x76]	104	1		T72	11		T141	1		T67	2
valid_sources[0x77]	89	1		T37	4		T43	1		T67	1
valid_sources[0x78]	276	1		T18	1		T68	1		T67	2
valid_sources[0x79]	130	1		T225	3		T196	1		T67	3
valid_sources[0x7a]	87	1		T211	1		T201	2		T68	1
valid_sources[0x7b]	64	1		T166	1		T139	2		T56	6
valid_sources[0x7c]	75	1		T159	1		T226	2		T232	1
valid_sources[0x7d]	114	1		T246	1		T159	1		T126	7
valid_sources[0x7e]	101	1		T32	1		T88	3		T56	5
valid_sources[0x7f]	92	1		T247	1		T248	3		T201	4
valid_sources[0x80]	81	1		T64	1		T20	1		T205	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7997

1

T68

33

T70

88

T69

1

values[0x0]

all_enables

biggest_size

8914

1

T1

2

T48

1

T9

1

values[0x1]

all_enables

biggest_size

8786

1

T2

1

T3

1

T49

1