Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
275336 |
1 |
|
T4 |
25 |
|
T5 |
4 |
|
T6 |
4 |
full_word |
588712 |
1 |
|
T4 |
19 |
|
T5 |
3 |
|
T6 |
5 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
863738 |
1 |
|
T4 |
44 |
|
T5 |
7 |
|
T6 |
9 |
auto[TlIntgErrCmd] |
100 |
1 |
|
T66 |
4 |
|
T85 |
7 |
|
T86 |
4 |
auto[TlIntgErrData] |
100 |
1 |
|
T66 |
1 |
|
T85 |
5 |
|
T86 |
2 |
auto[TlIntgErrBoth] |
110 |
1 |
|
T66 |
5 |
|
T85 |
8 |
|
T86 |
4 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
488635 |
1 |
|
T4 |
19 |
|
T5 |
1 |
|
T6 |
8 |
auto[1] |
375413 |
1 |
|
T4 |
25 |
|
T5 |
6 |
|
T6 |
1 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
1 |
15 |
93.75 |
1 |
Automatically Generated Cross Bins for cr_all
Uncovered bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | NUMBER |
[auto[TlIntgErrCmd]] |
[full_word] |
[auto[0]] |
0 |
1 |
1 |
Covered bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
197895 |
1 |
|
T4 |
6 |
|
T6 |
3 |
|
T7 |
2 |
auto[TlIntgErrNone] |
partial |
auto[1] |
77152 |
1 |
|
T4 |
19 |
|
T5 |
4 |
|
T6 |
1 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
290586 |
1 |
|
T4 |
13 |
|
T5 |
1 |
|
T6 |
5 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
298105 |
1 |
|
T4 |
6 |
|
T5 |
2 |
|
T7 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
51 |
1 |
|
T66 |
3 |
|
T85 |
2 |
|
T86 |
2 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
45 |
1 |
|
T85 |
5 |
|
T86 |
2 |
|
T170 |
4 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
4 |
1 |
|
T66 |
1 |
|
T124 |
1 |
|
T171 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
49 |
1 |
|
T66 |
1 |
|
T85 |
1 |
|
T170 |
1 |
auto[TlIntgErrData] |
partial |
auto[1] |
45 |
1 |
|
T85 |
2 |
|
T86 |
1 |
|
T170 |
1 |
auto[TlIntgErrData] |
full_word |
auto[0] |
4 |
1 |
|
T85 |
1 |
|
T86 |
1 |
|
T172 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
2 |
1 |
|
T85 |
1 |
|
T173 |
1 |
|
- |
- |
auto[TlIntgErrBoth] |
partial |
auto[0] |
46 |
1 |
|
T66 |
2 |
|
T85 |
3 |
|
T86 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
53 |
1 |
|
T66 |
3 |
|
T85 |
4 |
|
T86 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
4 |
1 |
|
T124 |
2 |
|
T174 |
1 |
|
T175 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
7 |
1 |
|
T85 |
1 |
|
T86 |
1 |
|
T176 |
1 |