Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.87	100.00	59.57	92.28		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	110315076	22840	0	0
late_debug_enable_rd_A	110315076	3273	0	0
late_debug_enable_regwen_rd_A	110315076	3040	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110315076	22840	0	0
T55	356054	213	0	0
T56	454968	2152	0	0
T66	56900	1	0	0
T67	9535	712	0	0
T81	7933	636	0	0
T82	104130	36	0	0
T83	11211	19	0	0
T84	13210	305	0	0
T85	55379	5	0	0
T86	82788	5	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110315076	3273	0	0
T56	454968	792	0	0
T69	5378	3	0	0
T83	11211	27	0	0
T93	40596	44	0	0
T103	9580	8	0	0
T105	31101	21	0	0
T116	47100	28	0	0
T122	104435	70	0	0
T123	319818	231	0	0
T124	99514	74	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110315076	3040	0	0
T56	454968	694	0	0
T69	5378	1	0	0
T83	11211	27	0	0
T93	40596	63	0	0
T105	31101	22	0	0
T111	9510	2	0	0
T116	47100	35	0	0
T122	104435	84	0	0
T123	319818	225	0	0
T124	99514	88	0	0