SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.87 | 100.00 | 59.57 | 92.28 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 227 | 227 | 0 | 0 |
OutputsKnown_A | 50520155 | 50477538 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 50520155 | 50475591 | 0 | 681 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 227 | 227 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
T50 | 1 | 1 | 0 | 0 |
T51 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50477538 | 0 | 0 |
T1 | 7218 | 7135 | 0 | 0 |
T2 | 190854 | 190789 | 0 | 0 |
T3 | 2198 | 2108 | 0 | 0 |
T4 | 122989 | 122859 | 0 | 0 |
T9 | 126646 | 126575 | 0 | 0 |
T10 | 145842 | 145790 | 0 | 0 |
T48 | 3303 | 3232 | 0 | 0 |
T49 | 3341 | 3281 | 0 | 0 |
T50 | 6699 | 6628 | 0 | 0 |
T51 | 1292 | 1208 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50475591 | 0 | 681 |
T1 | 7218 | 7132 | 0 | 3 |
T2 | 190854 | 190786 | 0 | 3 |
T3 | 2198 | 2105 | 0 | 3 |
T4 | 122989 | 122853 | 0 | 3 |
T9 | 126646 | 126572 | 0 | 3 |
T10 | 145842 | 145787 | 0 | 3 |
T48 | 3303 | 3229 | 0 | 3 |
T49 | 3341 | 3278 | 0 | 3 |
T50 | 6699 | 6625 | 0 | 3 |
T51 | 1292 | 1205 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |