Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50520155 |
6075406 |
0 |
0 |
T4 |
122989 |
31771 |
0 |
0 |
T5 |
60109 |
38503 |
0 |
0 |
T6 |
16520 |
12092 |
0 |
0 |
T7 |
3516 |
2169 |
0 |
0 |
T8 |
1925 |
0 |
0 |
0 |
T11 |
0 |
11040 |
0 |
0 |
T17 |
0 |
254395 |
0 |
0 |
T20 |
0 |
109008 |
0 |
0 |
T31 |
28479 |
0 |
0 |
0 |
T34 |
0 |
22069 |
0 |
0 |
T35 |
0 |
2954 |
0 |
0 |
T36 |
50937 |
0 |
0 |
0 |
T44 |
0 |
145148 |
0 |
0 |
T51 |
1292 |
0 |
0 |
0 |
T52 |
21256 |
0 |
0 |
0 |
T60 |
222736 |
0 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50520155 |
15 |
0 |
0 |
T3 |
2198 |
5 |
0 |
0 |
T4 |
122989 |
0 |
0 |
0 |
T5 |
60109 |
0 |
0 |
0 |
T9 |
126646 |
0 |
0 |
0 |
T10 |
145842 |
0 |
0 |
0 |
T48 |
3303 |
0 |
0 |
0 |
T49 |
3341 |
0 |
0 |
0 |
T50 |
6699 |
0 |
0 |
0 |
T51 |
1292 |
0 |
0 |
0 |
T60 |
222736 |
0 |
0 |
0 |
T61 |
0 |
10 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50520155 |
0 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50520155 |
12667 |
0 |
0 |
T2 |
190854 |
119 |
0 |
0 |
T3 |
2198 |
0 |
0 |
0 |
T4 |
122989 |
0 |
0 |
0 |
T5 |
60109 |
0 |
0 |
0 |
T9 |
126646 |
57 |
0 |
0 |
T10 |
145842 |
59 |
0 |
0 |
T32 |
0 |
16 |
0 |
0 |
T33 |
0 |
154 |
0 |
0 |
T37 |
0 |
28 |
0 |
0 |
T48 |
3303 |
0 |
0 |
0 |
T49 |
3341 |
0 |
0 |
0 |
T50 |
6699 |
0 |
0 |
0 |
T51 |
1292 |
0 |
0 |
0 |
T60 |
0 |
56 |
0 |
0 |
T62 |
0 |
127 |
0 |
0 |
T63 |
0 |
40 |
0 |
0 |
T64 |
0 |
16 |
0 |
0 |