Unified Coverage Report :: Module :: prim_generic_buf

Module : prim_generic_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[8].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[9].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[10].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[11].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[12].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[13].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[14].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[15].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[16].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[17].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[18].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[19].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[20].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[21].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[22].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[23].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[24].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[25].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[26].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[27].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[28].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[29].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[30].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[31].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[8].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[9].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[10].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[11].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[12].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[13].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[14].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[15].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[16].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[17].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[18].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[19].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[20].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[21].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[22].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[23].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[24].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[25].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[26].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[27].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[28].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[29].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[30].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[31].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[8].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[9].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[10].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[11].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[12].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[13].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[14].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[15].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[16].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[17].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[18].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[19].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[20].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[21].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[22].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[23].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[24].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[25].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[26].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[27].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[28].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[29].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[30].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[31].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[8].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[9].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[10].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[11].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[12].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[13].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[14].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[15].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[16].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[17].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[18].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[19].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[20].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[21].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[22].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[23].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[24].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[25].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[26].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[27].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[28].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[29].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[30].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[31].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[4].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[4].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[4].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_lc_en_sync_copies.gen_buffs[4].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_pm_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_pm_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_pm_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_pm_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_pm_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_pm_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_pm_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_pm_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_pm_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_pm_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_pm_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_pm_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[4].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[5].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[6].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[7].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[4].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[5].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[6].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[7].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[4].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[5].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[6].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[7].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[4].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[5].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[6].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[7].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[4].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[5].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[6].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[7].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[8].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[8].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[9].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[9].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[10].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[10].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[11].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[11].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[12].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[12].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[13].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[13].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[14].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[14].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[15].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[15].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[16].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[16].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[17].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[17].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[18].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[18].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[19].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[19].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[20].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[20].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[21].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[21].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[22].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[22].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[23].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[23].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[24].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[24].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[25].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[25].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[26].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[26].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[27].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[27].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[28].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[28].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[29].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[29].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[30].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[30].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[31].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[31].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[4].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[5].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[6].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[7].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[8].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[8].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[9].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[9].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[10].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[10].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[11].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[11].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[12].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[12].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[13].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[13].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[14].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[14].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[15].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[15].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[16].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[16].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[17].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[17].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[18].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[18].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[19].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[19].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[20].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[20].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[21].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[21].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[22].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[22].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[23].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[23].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[24].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[24].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[25].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[25].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[26].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[26].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[27].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[27].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[28].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[28].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[29].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[29].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[30].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[30].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[31].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[31].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[4].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[5].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[6].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[7].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[8].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[8].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[9].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[9].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[10].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[10].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[11].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[11].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[12].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[12].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[13].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[13].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[14].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[14].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[15].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[15].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[16].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[16].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[17].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[17].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[18].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[18].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[19].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[19].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[20].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[20].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[21].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[21].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[22].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[22].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[23].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[23].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[24].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[24].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[25].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[25].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[26].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[26].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[27].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[27].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[28].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[28].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[29].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[29].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[30].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[30].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[31].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[31].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[4].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[5].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[6].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[7].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[8].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[8].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[9].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[9].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[10].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[10].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[11].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[11].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[12].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[12].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[13].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[13].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[14].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[14].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[15].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[15].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[16].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[16].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[17].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[17].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[18].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[18].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[19].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[19].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[20].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[20].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[21].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[21].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[22].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[22].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[23].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[23].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[24].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[24].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[25].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[25].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[26].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[26].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[27].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[27].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[28].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[28].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[29].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[29].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[30].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[30].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[31].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[31].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[4].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[4].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[4].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[4].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_pm_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_pm_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_pm_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_pm_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_pm_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_pm_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_pm_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_pm_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_pm_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_pm_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_pm_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_pm_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_buf

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[0].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[1].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[2].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_buffs[3].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[8].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[9].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[10].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[11].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[12].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[13].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[14].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[15].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[16].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[17].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[18].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[19].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[20].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[21].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[22].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[23].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[24].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[25].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[26].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[27].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[28].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[29].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[30].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[0].gen_bits[31].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[8].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[9].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[10].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[11].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[12].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[13].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[14].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[15].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[16].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[17].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[18].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[19].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[20].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[21].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[22].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[23].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[24].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[25].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[26].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[27].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[28].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[29].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[30].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[1].gen_bits[31].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[8].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[9].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[10].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[11].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[12].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[13].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[14].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[15].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[16].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[17].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[18].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[19].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[20].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[21].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[22].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[23].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[24].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[25].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[26].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[27].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[28].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[29].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[30].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[2].gen_bits[31].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[4].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[5].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[6].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[7].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[8].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[9].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[10].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[11].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[12].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[13].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[14].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[15].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[16].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[17].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[18].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[19].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[20].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[21].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[22].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[23].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[24].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[25].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[26].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[27].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[28].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[29].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[30].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable.gen_buffs[3].gen_bits[31].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[4].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[4].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[4].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies.gen_buffs[4].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_pm_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_pm_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_pm_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_pm_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_pm_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_pm_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_pm_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_pm_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_pm_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_pm_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_pm_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_pm_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1