Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8517082 8515736 0 0
selKnown1 56506478 56505132 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8517082 8515736 0 0
T1 339 337 0 0
T2 27712 27710 0 0
T3 593 591 0 0
T4 21702 21698 0 0
T5 10 8 0 0
T6 2 0 0 0
T7 2 0 0 0
T8 2 0 0 0
T9 17158 17156 0 0
T10 17729 17727 0 0
T31 2 0 0 0
T32 0 8 0 0
T33 0 10 0 0
T36 7 5 0 0
T37 0 16 0 0
T38 0 10 0 0
T44 0 10 0 0
T48 445 443 0 0
T49 421 419 0 0
T50 299 297 0 0
T51 709 705 0 0
T52 42 40 0 0
T53 0 40 0 0
T59 0 6 0 0
T60 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 56506478 56505132 0 0
T1 7387 7385 0 0
T2 204710 204708 0 0
T3 2494 2492 0 0
T4 133841 133837 0 0
T5 8 6 0 0
T6 2 0 0 0
T7 2 0 0 0
T8 2 0 0 0
T9 135225 135223 0 0
T10 154706 154704 0 0
T31 2 0 0 0
T32 0 8 0 0
T33 0 10 0 0
T36 2 0 0 0
T37 0 16 0 0
T38 0 10 0 0
T44 0 8 0 0
T48 3525 3523 0 0
T49 3551 3549 0 0
T50 6848 6846 0 0
T51 1647 1643 0 0
T52 42 40 0 0
T53 0 40 0 0
T59 0 12 0 0
T60 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2530301 2530074 0 0
selKnown1 50520155 50519928 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2530301 2530074 0 0
T1 169 168 0 0
T2 13856 13855 0 0
T3 296 295 0 0
T4 10848 10847 0 0
T9 8579 8578 0 0
T10 8864 8863 0 0
T48 222 221 0 0
T49 210 209 0 0
T50 149 148 0 0
T51 353 352 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 50520155 50519928 0 0
T1 7218 7217 0 0
T2 190854 190853 0 0
T3 2198 2197 0 0
T4 122989 122988 0 0
T9 126646 126645 0 0
T10 145842 145841 0 0
T48 3303 3302 0 0
T49 3341 3340 0 0
T50 6699 6698 0 0
T51 1292 1291 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 685 458 0 0
selKnown1 649 422 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 685 458 0 0
T4 3 2 0 0
T5 5 4 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 1 0 0 0
T31 1 0 0 0
T32 0 4 0 0
T33 0 5 0 0
T36 1 0 0 0
T37 0 8 0 0
T38 0 5 0 0
T44 0 4 0 0
T51 1 0 0 0
T52 21 20 0 0
T53 0 20 0 0
T59 0 6 0 0
T60 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 649 422 0 0
T4 2 1 0 0
T5 4 3 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 1 0 0 0
T31 1 0 0 0
T32 0 4 0 0
T33 0 5 0 0
T36 1 0 0 0
T37 0 8 0 0
T38 0 5 0 0
T44 0 4 0 0
T51 1 0 0 0
T52 21 20 0 0
T53 0 20 0 0
T59 0 6 0 0
T60 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 5984121 5983675 0 0
selKnown1 5983916 5983470 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 5984121 5983675 0 0
T1 170 169 0 0
T2 13856 13855 0 0
T3 297 296 0 0
T4 10848 10847 0 0
T9 8579 8578 0 0
T10 8865 8864 0 0
T48 223 222 0 0
T49 211 210 0 0
T50 150 149 0 0
T51 354 353 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 5983916 5983470 0 0
T1 169 168 0 0
T2 13856 13855 0 0
T3 296 295 0 0
T4 10848 10847 0 0
T9 8579 8578 0 0
T10 8864 8863 0 0
T48 222 221 0 0
T49 210 209 0 0
T50 149 148 0 0
T51 353 352 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1975 1529 0 0
selKnown1 1758 1312 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1975 1529 0 0
T4 3 2 0 0
T5 5 4 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 1 0 0 0
T31 1 0 0 0
T32 0 4 0 0
T33 0 5 0 0
T36 6 5 0 0
T37 0 8 0 0
T38 0 5 0 0
T44 0 6 0 0
T51 1 0 0 0
T52 21 20 0 0
T53 0 20 0 0
T60 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1758 1312 0 0
T4 2 1 0 0
T5 4 3 0 0
T6 1 0 0 0
T7 1 0 0 0
T8 1 0 0 0
T31 1 0 0 0
T32 0 4 0 0
T33 0 5 0 0
T36 1 0 0 0
T37 0 8 0 0
T38 0 5 0 0
T44 0 4 0 0
T51 1 0 0 0
T52 21 20 0 0
T53 0 20 0 0
T59 0 6 0 0
T60 1 0 0 0

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