SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.87 | 100.00 | 59.57 | 92.28 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.87 | 100.00 | 59.57 | 92.28 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.87 | 100.00 | 59.57 | 92.28 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.87 | 100.00 | 59.57 | 92.28 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
79.81 | 98.04 | 77.78 | 85.71 | 87.50 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1362 | 1362 | 0 | 0 |
OutputsKnown_A | 303120930 | 302865228 | 0 | 0 |
gen_flops.OutputDelay_A | 151560465 | 151426773 | 0 | 2043 |
gen_no_flops.OutputDelay_A | 151560465 | 151432614 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1362 | 1362 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T9 | 6 | 6 | 0 | 0 |
T10 | 6 | 6 | 0 | 0 |
T48 | 6 | 6 | 0 | 0 |
T49 | 6 | 6 | 0 | 0 |
T50 | 6 | 6 | 0 | 0 |
T51 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 303120930 | 302865228 | 0 | 0 |
T1 | 43308 | 42810 | 0 | 0 |
T2 | 1145124 | 1144734 | 0 | 0 |
T3 | 13188 | 12648 | 0 | 0 |
T4 | 737934 | 737154 | 0 | 0 |
T9 | 759876 | 759450 | 0 | 0 |
T10 | 875052 | 874740 | 0 | 0 |
T48 | 19818 | 19392 | 0 | 0 |
T49 | 20046 | 19686 | 0 | 0 |
T50 | 40194 | 39768 | 0 | 0 |
T51 | 7752 | 7248 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 151560465 | 151426773 | 0 | 2043 |
T1 | 21654 | 21396 | 0 | 9 |
T2 | 572562 | 572358 | 0 | 9 |
T3 | 6594 | 6315 | 0 | 9 |
T4 | 368967 | 368559 | 0 | 9 |
T9 | 379938 | 379716 | 0 | 9 |
T10 | 437526 | 437361 | 0 | 9 |
T48 | 9909 | 9687 | 0 | 9 |
T49 | 10023 | 9834 | 0 | 9 |
T50 | 20097 | 19875 | 0 | 9 |
T51 | 3876 | 3615 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 151560465 | 151432614 | 0 | 0 |
T1 | 21654 | 21405 | 0 | 0 |
T2 | 572562 | 572367 | 0 | 0 |
T3 | 6594 | 6324 | 0 | 0 |
T4 | 368967 | 368577 | 0 | 0 |
T9 | 379938 | 379725 | 0 | 0 |
T10 | 437526 | 437370 | 0 | 0 |
T48 | 9909 | 9696 | 0 | 0 |
T49 | 10023 | 9843 | 0 | 0 |
T50 | 20097 | 19884 | 0 | 0 |
T51 | 3876 | 3624 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 227 | 227 | 0 | 0 |
OutputsKnown_A | 50520155 | 50477538 | 0 | 0 |
gen_flops.OutputDelay_A | 50520155 | 50475591 | 0 | 681 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 227 | 227 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
T50 | 1 | 1 | 0 | 0 |
T51 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50477538 | 0 | 0 |
T1 | 7218 | 7135 | 0 | 0 |
T2 | 190854 | 190789 | 0 | 0 |
T3 | 2198 | 2108 | 0 | 0 |
T4 | 122989 | 122859 | 0 | 0 |
T9 | 126646 | 126575 | 0 | 0 |
T10 | 145842 | 145790 | 0 | 0 |
T48 | 3303 | 3232 | 0 | 0 |
T49 | 3341 | 3281 | 0 | 0 |
T50 | 6699 | 6628 | 0 | 0 |
T51 | 1292 | 1208 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50475591 | 0 | 681 |
T1 | 7218 | 7132 | 0 | 3 |
T2 | 190854 | 190786 | 0 | 3 |
T3 | 2198 | 2105 | 0 | 3 |
T4 | 122989 | 122853 | 0 | 3 |
T9 | 126646 | 126572 | 0 | 3 |
T10 | 145842 | 145787 | 0 | 3 |
T48 | 3303 | 3229 | 0 | 3 |
T49 | 3341 | 3278 | 0 | 3 |
T50 | 6699 | 6625 | 0 | 3 |
T51 | 1292 | 1205 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 227 | 227 | 0 | 0 |
OutputsKnown_A | 50520155 | 50477538 | 0 | 0 |
gen_flops.OutputDelay_A | 50520155 | 50475591 | 0 | 681 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 227 | 227 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
T50 | 1 | 1 | 0 | 0 |
T51 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50477538 | 0 | 0 |
T1 | 7218 | 7135 | 0 | 0 |
T2 | 190854 | 190789 | 0 | 0 |
T3 | 2198 | 2108 | 0 | 0 |
T4 | 122989 | 122859 | 0 | 0 |
T9 | 126646 | 126575 | 0 | 0 |
T10 | 145842 | 145790 | 0 | 0 |
T48 | 3303 | 3232 | 0 | 0 |
T49 | 3341 | 3281 | 0 | 0 |
T50 | 6699 | 6628 | 0 | 0 |
T51 | 1292 | 1208 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50475591 | 0 | 681 |
T1 | 7218 | 7132 | 0 | 3 |
T2 | 190854 | 190786 | 0 | 3 |
T3 | 2198 | 2105 | 0 | 3 |
T4 | 122989 | 122853 | 0 | 3 |
T9 | 126646 | 126572 | 0 | 3 |
T10 | 145842 | 145787 | 0 | 3 |
T48 | 3303 | 3229 | 0 | 3 |
T49 | 3341 | 3278 | 0 | 3 |
T50 | 6699 | 6625 | 0 | 3 |
T51 | 1292 | 1205 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 227 | 227 | 0 | 0 |
OutputsKnown_A | 50520155 | 50477538 | 0 | 0 |
gen_no_flops.OutputDelay_A | 50520155 | 50477538 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 227 | 227 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
T50 | 1 | 1 | 0 | 0 |
T51 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50477538 | 0 | 0 |
T1 | 7218 | 7135 | 0 | 0 |
T2 | 190854 | 190789 | 0 | 0 |
T3 | 2198 | 2108 | 0 | 0 |
T4 | 122989 | 122859 | 0 | 0 |
T9 | 126646 | 126575 | 0 | 0 |
T10 | 145842 | 145790 | 0 | 0 |
T48 | 3303 | 3232 | 0 | 0 |
T49 | 3341 | 3281 | 0 | 0 |
T50 | 6699 | 6628 | 0 | 0 |
T51 | 1292 | 1208 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50477538 | 0 | 0 |
T1 | 7218 | 7135 | 0 | 0 |
T2 | 190854 | 190789 | 0 | 0 |
T3 | 2198 | 2108 | 0 | 0 |
T4 | 122989 | 122859 | 0 | 0 |
T9 | 126646 | 126575 | 0 | 0 |
T10 | 145842 | 145790 | 0 | 0 |
T48 | 3303 | 3232 | 0 | 0 |
T49 | 3341 | 3281 | 0 | 0 |
T50 | 6699 | 6628 | 0 | 0 |
T51 | 1292 | 1208 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 227 | 227 | 0 | 0 |
OutputsKnown_A | 50520155 | 50477538 | 0 | 0 |
gen_flops.OutputDelay_A | 50520155 | 50475591 | 0 | 681 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 227 | 227 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
T50 | 1 | 1 | 0 | 0 |
T51 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50477538 | 0 | 0 |
T1 | 7218 | 7135 | 0 | 0 |
T2 | 190854 | 190789 | 0 | 0 |
T3 | 2198 | 2108 | 0 | 0 |
T4 | 122989 | 122859 | 0 | 0 |
T9 | 126646 | 126575 | 0 | 0 |
T10 | 145842 | 145790 | 0 | 0 |
T48 | 3303 | 3232 | 0 | 0 |
T49 | 3341 | 3281 | 0 | 0 |
T50 | 6699 | 6628 | 0 | 0 |
T51 | 1292 | 1208 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50475591 | 0 | 681 |
T1 | 7218 | 7132 | 0 | 3 |
T2 | 190854 | 190786 | 0 | 3 |
T3 | 2198 | 2105 | 0 | 3 |
T4 | 122989 | 122853 | 0 | 3 |
T9 | 126646 | 126572 | 0 | 3 |
T10 | 145842 | 145787 | 0 | 3 |
T48 | 3303 | 3229 | 0 | 3 |
T49 | 3341 | 3278 | 0 | 3 |
T50 | 6699 | 6625 | 0 | 3 |
T51 | 1292 | 1205 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 227 | 227 | 0 | 0 |
OutputsKnown_A | 50520155 | 50477538 | 0 | 0 |
gen_no_flops.OutputDelay_A | 50520155 | 50477538 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 227 | 227 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
T50 | 1 | 1 | 0 | 0 |
T51 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50477538 | 0 | 0 |
T1 | 7218 | 7135 | 0 | 0 |
T2 | 190854 | 190789 | 0 | 0 |
T3 | 2198 | 2108 | 0 | 0 |
T4 | 122989 | 122859 | 0 | 0 |
T9 | 126646 | 126575 | 0 | 0 |
T10 | 145842 | 145790 | 0 | 0 |
T48 | 3303 | 3232 | 0 | 0 |
T49 | 3341 | 3281 | 0 | 0 |
T50 | 6699 | 6628 | 0 | 0 |
T51 | 1292 | 1208 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50477538 | 0 | 0 |
T1 | 7218 | 7135 | 0 | 0 |
T2 | 190854 | 190789 | 0 | 0 |
T3 | 2198 | 2108 | 0 | 0 |
T4 | 122989 | 122859 | 0 | 0 |
T9 | 126646 | 126575 | 0 | 0 |
T10 | 145842 | 145790 | 0 | 0 |
T48 | 3303 | 3232 | 0 | 0 |
T49 | 3341 | 3281 | 0 | 0 |
T50 | 6699 | 6628 | 0 | 0 |
T51 | 1292 | 1208 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 227 | 227 | 0 | 0 |
OutputsKnown_A | 50520155 | 50477538 | 0 | 0 |
gen_no_flops.OutputDelay_A | 50520155 | 50477538 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 227 | 227 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
T50 | 1 | 1 | 0 | 0 |
T51 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50477538 | 0 | 0 |
T1 | 7218 | 7135 | 0 | 0 |
T2 | 190854 | 190789 | 0 | 0 |
T3 | 2198 | 2108 | 0 | 0 |
T4 | 122989 | 122859 | 0 | 0 |
T9 | 126646 | 126575 | 0 | 0 |
T10 | 145842 | 145790 | 0 | 0 |
T48 | 3303 | 3232 | 0 | 0 |
T49 | 3341 | 3281 | 0 | 0 |
T50 | 6699 | 6628 | 0 | 0 |
T51 | 1292 | 1208 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50520155 | 50477538 | 0 | 0 |
T1 | 7218 | 7135 | 0 | 0 |
T2 | 190854 | 190789 | 0 | 0 |
T3 | 2198 | 2108 | 0 | 0 |
T4 | 122989 | 122859 | 0 | 0 |
T9 | 126646 | 126575 | 0 | 0 |
T10 | 145842 | 145790 | 0 | 0 |
T48 | 3303 | 3232 | 0 | 0 |
T49 | 3341 | 3281 | 0 | 0 |
T50 | 6699 | 6628 | 0 | 0 |
T51 | 1292 | 1208 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |