Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.30 95.32 80.00 89.75 73.08 85.83 98.42 53.73


Total test records in report: 445
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T302 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2126088524 Jul 14 05:31:35 PM PDT 24 Jul 14 05:31:43 PM PDT 24 2596077058 ps
T86 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1499956508 Jul 14 05:31:28 PM PDT 24 Jul 14 05:31:53 PM PDT 24 3206379224 ps
T303 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.485299584 Jul 14 05:31:31 PM PDT 24 Jul 14 05:33:01 PM PDT 24 35386998611 ps
T46 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2789285933 Jul 14 05:31:35 PM PDT 24 Jul 14 05:31:50 PM PDT 24 39606872208 ps
T304 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3624707738 Jul 14 05:31:25 PM PDT 24 Jul 14 05:31:28 PM PDT 24 107746877 ps
T305 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.4226043345 Jul 14 05:31:32 PM PDT 24 Jul 14 05:32:02 PM PDT 24 9026055970 ps
T306 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1763259208 Jul 14 05:31:22 PM PDT 24 Jul 14 05:31:43 PM PDT 24 17927107485 ps
T94 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1507013564 Jul 14 05:31:38 PM PDT 24 Jul 14 05:31:46 PM PDT 24 428067797 ps
T307 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2366585304 Jul 14 05:31:29 PM PDT 24 Jul 14 05:31:33 PM PDT 24 583170925 ps
T308 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3807007217 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:36 PM PDT 24 2497526534 ps
T309 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.124801760 Jul 14 05:31:33 PM PDT 24 Jul 14 05:32:10 PM PDT 24 12941213859 ps
T87 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2756194513 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:40 PM PDT 24 805578697 ps
T88 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3605296098 Jul 14 05:32:08 PM PDT 24 Jul 14 05:32:12 PM PDT 24 145438519 ps
T99 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2108395827 Jul 14 05:31:33 PM PDT 24 Jul 14 05:31:44 PM PDT 24 10384960032 ps
T95 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1685727419 Jul 14 05:31:40 PM PDT 24 Jul 14 05:31:43 PM PDT 24 144990446 ps
T126 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.496114711 Jul 14 05:31:27 PM PDT 24 Jul 14 05:31:39 PM PDT 24 1777520205 ps
T310 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.370931096 Jul 14 05:31:41 PM PDT 24 Jul 14 05:31:42 PM PDT 24 306114915 ps
T311 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3527533742 Jul 14 05:31:29 PM PDT 24 Jul 14 05:31:32 PM PDT 24 122359165 ps
T312 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.390669322 Jul 14 05:32:02 PM PDT 24 Jul 14 05:32:20 PM PDT 24 20652628540 ps
T89 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2603038112 Jul 14 05:32:01 PM PDT 24 Jul 14 05:32:04 PM PDT 24 681569976 ps
T96 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2227888544 Jul 14 05:31:34 PM PDT 24 Jul 14 05:31:39 PM PDT 24 285451096 ps
T313 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.172919114 Jul 14 05:31:44 PM PDT 24 Jul 14 05:31:48 PM PDT 24 216927575 ps
T123 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.487750168 Jul 14 05:32:08 PM PDT 24 Jul 14 05:32:20 PM PDT 24 861581517 ps
T314 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3039730817 Jul 14 05:31:23 PM PDT 24 Jul 14 05:31:33 PM PDT 24 2652808789 ps
T124 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2624227519 Jul 14 05:31:33 PM PDT 24 Jul 14 05:31:40 PM PDT 24 462060258 ps
T100 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3007861046 Jul 14 05:31:32 PM PDT 24 Jul 14 05:32:01 PM PDT 24 9115222329 ps
T178 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2007391755 Jul 14 05:31:47 PM PDT 24 Jul 14 05:32:06 PM PDT 24 4292765337 ps
T315 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2516527147 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:42 PM PDT 24 3643802254 ps
T316 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.733776186 Jul 14 05:31:27 PM PDT 24 Jul 14 05:31:36 PM PDT 24 2006626237 ps
T97 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3019165962 Jul 14 05:31:25 PM PDT 24 Jul 14 05:31:29 PM PDT 24 278276052 ps
T317 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2497216828 Jul 14 05:31:29 PM PDT 24 Jul 14 05:31:33 PM PDT 24 286704983 ps
T318 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3092777058 Jul 14 05:32:00 PM PDT 24 Jul 14 05:32:21 PM PDT 24 24578050004 ps
T319 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1128804572 Jul 14 05:32:03 PM PDT 24 Jul 14 05:32:07 PM PDT 24 2313200762 ps
T98 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1764719703 Jul 14 05:31:27 PM PDT 24 Jul 14 05:31:31 PM PDT 24 189963218 ps
T320 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.398131604 Jul 14 05:31:24 PM PDT 24 Jul 14 05:34:31 PM PDT 24 117602927758 ps
T103 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.21155194 Jul 14 05:31:56 PM PDT 24 Jul 14 05:32:04 PM PDT 24 590201938 ps
T321 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1121397296 Jul 14 05:31:28 PM PDT 24 Jul 14 05:31:32 PM PDT 24 237574381 ps
T176 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1660837723 Jul 14 05:31:33 PM PDT 24 Jul 14 05:31:41 PM PDT 24 158589567 ps
T322 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2134083430 Jul 14 05:31:43 PM PDT 24 Jul 14 05:31:53 PM PDT 24 23506821777 ps
T323 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.307589531 Jul 14 05:31:38 PM PDT 24 Jul 14 05:31:43 PM PDT 24 2869088448 ps
T324 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2981307479 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:37 PM PDT 24 272950693 ps
T325 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2082098587 Jul 14 05:32:05 PM PDT 24 Jul 14 05:32:08 PM PDT 24 634490947 ps
T326 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1838288737 Jul 14 05:31:26 PM PDT 24 Jul 14 05:34:15 PM PDT 24 152234137082 ps
T187 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2001745650 Jul 14 05:32:11 PM PDT 24 Jul 14 05:32:24 PM PDT 24 1490505246 ps
T119 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1881734931 Jul 14 05:31:34 PM PDT 24 Jul 14 05:31:45 PM PDT 24 1382010646 ps
T327 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1082197369 Jul 14 05:32:01 PM PDT 24 Jul 14 05:32:02 PM PDT 24 218479812 ps
T328 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1429623226 Jul 14 05:32:12 PM PDT 24 Jul 14 05:32:17 PM PDT 24 1105081323 ps
T329 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2916941769 Jul 14 05:32:02 PM PDT 24 Jul 14 05:32:11 PM PDT 24 1574133960 ps
T330 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1150510964 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:42 PM PDT 24 2667976408 ps
T110 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2685288513 Jul 14 05:32:06 PM PDT 24 Jul 14 05:32:09 PM PDT 24 156994416 ps
T47 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3797279367 Jul 14 05:31:32 PM PDT 24 Jul 14 05:32:54 PM PDT 24 51486777795 ps
T331 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2663831054 Jul 14 05:31:26 PM PDT 24 Jul 14 05:31:29 PM PDT 24 161562250 ps
T332 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4138097724 Jul 14 05:31:32 PM PDT 24 Jul 14 05:31:37 PM PDT 24 198424281 ps
T333 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1728978871 Jul 14 05:31:39 PM PDT 24 Jul 14 05:32:18 PM PDT 24 14017091202 ps
T334 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3900533670 Jul 14 05:31:32 PM PDT 24 Jul 14 05:31:54 PM PDT 24 7364137869 ps
T335 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1617264387 Jul 14 05:31:23 PM PDT 24 Jul 14 05:31:26 PM PDT 24 412454167 ps
T336 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.106212530 Jul 14 05:32:00 PM PDT 24 Jul 14 05:32:03 PM PDT 24 512534091 ps
T337 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2060777189 Jul 14 05:31:35 PM PDT 24 Jul 14 05:31:41 PM PDT 24 143231694 ps
T338 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2585580264 Jul 14 05:32:08 PM PDT 24 Jul 14 05:32:14 PM PDT 24 1210929747 ps
T111 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.239599474 Jul 14 05:31:32 PM PDT 24 Jul 14 05:31:37 PM PDT 24 201721629 ps
T339 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.773253943 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:35 PM PDT 24 374850115 ps
T340 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1687722886 Jul 14 05:31:21 PM PDT 24 Jul 14 05:31:25 PM PDT 24 719631818 ps
T341 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2389959593 Jul 14 05:32:06 PM PDT 24 Jul 14 05:32:11 PM PDT 24 118407389 ps
T342 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2960387319 Jul 14 05:31:22 PM PDT 24 Jul 14 05:31:25 PM PDT 24 539142694 ps
T120 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2252198674 Jul 14 05:31:54 PM PDT 24 Jul 14 05:31:58 PM PDT 24 171282887 ps
T343 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2666126475 Jul 14 05:32:02 PM PDT 24 Jul 14 05:32:05 PM PDT 24 277927038 ps
T344 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3871424953 Jul 14 05:31:29 PM PDT 24 Jul 14 05:32:35 PM PDT 24 4798585726 ps
T104 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.704036697 Jul 14 05:32:05 PM PDT 24 Jul 14 05:32:13 PM PDT 24 1362100522 ps
T345 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3660365281 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:36 PM PDT 24 64742150 ps
T125 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.499037742 Jul 14 05:32:06 PM PDT 24 Jul 14 05:32:19 PM PDT 24 1755226773 ps
T112 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1601752216 Jul 14 05:31:28 PM PDT 24 Jul 14 05:32:45 PM PDT 24 6888538913 ps
T177 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.217418316 Jul 14 05:31:29 PM PDT 24 Jul 14 05:31:36 PM PDT 24 178667218 ps
T346 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2314888668 Jul 14 05:32:04 PM PDT 24 Jul 14 05:32:05 PM PDT 24 164570027 ps
T347 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1412192260 Jul 14 05:32:06 PM PDT 24 Jul 14 05:32:16 PM PDT 24 3222512859 ps
T113 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3081910648 Jul 14 05:32:00 PM PDT 24 Jul 14 05:32:03 PM PDT 24 76768204 ps
T348 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1462965799 Jul 14 05:32:07 PM PDT 24 Jul 14 05:33:08 PM PDT 24 49382618760 ps
T121 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3008494860 Jul 14 05:32:06 PM PDT 24 Jul 14 05:32:15 PM PDT 24 466596055 ps
T349 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3217523093 Jul 14 05:31:23 PM PDT 24 Jul 14 05:31:28 PM PDT 24 1603106995 ps
T350 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1988699514 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:36 PM PDT 24 136728865 ps
T179 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.133765189 Jul 14 05:31:25 PM PDT 24 Jul 14 05:31:36 PM PDT 24 719953301 ps
T114 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3031065781 Jul 14 05:31:29 PM PDT 24 Jul 14 05:31:59 PM PDT 24 2091651970 ps
T180 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3558710994 Jul 14 05:31:36 PM PDT 24 Jul 14 05:32:00 PM PDT 24 3512542632 ps
T351 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1192667033 Jul 14 05:31:48 PM PDT 24 Jul 14 05:31:58 PM PDT 24 17436952389 ps
T105 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1186454246 Jul 14 05:32:09 PM PDT 24 Jul 14 05:32:14 PM PDT 24 324866403 ps
T352 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1283573815 Jul 14 05:31:30 PM PDT 24 Jul 14 05:31:35 PM PDT 24 644002805 ps
T115 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3352334071 Jul 14 05:31:27 PM PDT 24 Jul 14 05:32:05 PM PDT 24 3207996147 ps
T106 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2733370109 Jul 14 05:31:59 PM PDT 24 Jul 14 05:32:06 PM PDT 24 272361527 ps
T353 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.774458652 Jul 14 05:31:32 PM PDT 24 Jul 14 05:31:41 PM PDT 24 612011295 ps
T354 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1556456142 Jul 14 05:31:48 PM PDT 24 Jul 14 05:31:50 PM PDT 24 187344802 ps
T355 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4007443773 Jul 14 05:31:22 PM PDT 24 Jul 14 05:31:57 PM PDT 24 2459698183 ps
T356 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4038466146 Jul 14 05:32:07 PM PDT 24 Jul 14 05:32:12 PM PDT 24 4914276047 ps
T118 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4176411529 Jul 14 05:32:08 PM PDT 24 Jul 14 05:32:12 PM PDT 24 193646130 ps
T357 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1658121426 Jul 14 05:31:26 PM PDT 24 Jul 14 05:31:59 PM PDT 24 11902777788 ps
T358 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1707094603 Jul 14 05:32:09 PM PDT 24 Jul 14 05:32:17 PM PDT 24 6035285874 ps
T101 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.537351328 Jul 14 05:31:27 PM PDT 24 Jul 14 05:31:33 PM PDT 24 4180494005 ps
T359 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2276636969 Jul 14 05:31:23 PM PDT 24 Jul 14 05:31:26 PM PDT 24 197739778 ps
T107 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3137916872 Jul 14 05:31:34 PM PDT 24 Jul 14 05:32:50 PM PDT 24 3792069889 ps
T184 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.220301481 Jul 14 05:31:59 PM PDT 24 Jul 14 05:32:25 PM PDT 24 6453003200 ps
T360 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2375626067 Jul 14 05:31:39 PM PDT 24 Jul 14 05:31:42 PM PDT 24 171290798 ps
T361 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1744703978 Jul 14 05:31:54 PM PDT 24 Jul 14 05:32:03 PM PDT 24 9223040552 ps
T362 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3245334530 Jul 14 05:32:00 PM PDT 24 Jul 14 05:32:05 PM PDT 24 5291421705 ps
T363 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3424615701 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:42 PM PDT 24 2293730740 ps
T364 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3016326790 Jul 14 05:31:34 PM PDT 24 Jul 14 05:31:42 PM PDT 24 4508352503 ps
T183 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.125996942 Jul 14 05:31:57 PM PDT 24 Jul 14 05:32:19 PM PDT 24 3673511124 ps
T365 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3497356228 Jul 14 05:31:32 PM PDT 24 Jul 14 05:31:42 PM PDT 24 2027725643 ps
T366 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2677645330 Jul 14 05:31:33 PM PDT 24 Jul 14 05:31:39 PM PDT 24 732449420 ps
T367 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1269030954 Jul 14 05:32:04 PM PDT 24 Jul 14 05:32:40 PM PDT 24 19717006668 ps
T368 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2871423219 Jul 14 05:31:25 PM PDT 24 Jul 14 05:31:31 PM PDT 24 3834585188 ps
T369 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1595076592 Jul 14 05:31:27 PM PDT 24 Jul 14 05:31:31 PM PDT 24 133873938 ps
T108 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2858467323 Jul 14 05:31:34 PM PDT 24 Jul 14 05:31:40 PM PDT 24 496225460 ps
T188 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.387228026 Jul 14 05:31:33 PM PDT 24 Jul 14 05:32:22 PM PDT 24 41983269670 ps
T370 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3157874182 Jul 14 05:31:47 PM PDT 24 Jul 14 05:31:50 PM PDT 24 384627188 ps
T109 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1408379226 Jul 14 05:32:07 PM PDT 24 Jul 14 05:32:12 PM PDT 24 1192245173 ps
T371 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4053849092 Jul 14 05:31:25 PM PDT 24 Jul 14 05:31:38 PM PDT 24 4750797866 ps
T372 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2652078723 Jul 14 05:31:42 PM PDT 24 Jul 14 05:31:48 PM PDT 24 10073850158 ps
T373 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.945908858 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:35 PM PDT 24 40585473 ps
T374 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3071422288 Jul 14 05:31:33 PM PDT 24 Jul 14 05:31:39 PM PDT 24 166970310 ps
T375 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3758510040 Jul 14 05:31:37 PM PDT 24 Jul 14 05:33:56 PM PDT 24 50635019799 ps
T376 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2454516619 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:42 PM PDT 24 1410965896 ps
T377 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3749336841 Jul 14 05:32:07 PM PDT 24 Jul 14 05:32:14 PM PDT 24 246511138 ps
T378 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.48457737 Jul 14 05:31:27 PM PDT 24 Jul 14 05:31:30 PM PDT 24 435613385 ps
T379 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1610948935 Jul 14 05:31:26 PM PDT 24 Jul 14 05:31:31 PM PDT 24 335070673 ps
T185 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.232848014 Jul 14 05:31:42 PM PDT 24 Jul 14 05:31:54 PM PDT 24 1238177975 ps
T181 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1746445453 Jul 14 05:31:34 PM PDT 24 Jul 14 05:31:57 PM PDT 24 3660627218 ps
T102 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1368320551 Jul 14 05:31:25 PM PDT 24 Jul 14 05:31:30 PM PDT 24 1111026812 ps
T380 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2201681031 Jul 14 05:31:26 PM PDT 24 Jul 14 05:31:29 PM PDT 24 90932349 ps
T381 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2318488616 Jul 14 05:31:38 PM PDT 24 Jul 14 05:31:44 PM PDT 24 242615336 ps
T382 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.297492713 Jul 14 05:32:06 PM PDT 24 Jul 14 05:32:18 PM PDT 24 4828238238 ps
T383 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1512308714 Jul 14 05:31:39 PM PDT 24 Jul 14 05:31:47 PM PDT 24 1981666640 ps
T384 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2267491955 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:42 PM PDT 24 1010672579 ps
T385 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2145266526 Jul 14 05:31:32 PM PDT 24 Jul 14 05:32:57 PM PDT 24 29785001995 ps
T386 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3615812216 Jul 14 05:31:29 PM PDT 24 Jul 14 05:32:24 PM PDT 24 1550668532 ps
T387 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1317839855 Jul 14 05:32:06 PM PDT 24 Jul 14 05:32:09 PM PDT 24 263594871 ps
T388 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2944934379 Jul 14 05:31:25 PM PDT 24 Jul 14 05:32:36 PM PDT 24 45306736143 ps
T389 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1196269778 Jul 14 05:31:32 PM PDT 24 Jul 14 05:31:54 PM PDT 24 11898145311 ps
T390 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2987983988 Jul 14 05:31:34 PM PDT 24 Jul 14 05:31:40 PM PDT 24 174343621 ps
T391 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1147831218 Jul 14 05:31:25 PM PDT 24 Jul 14 05:31:29 PM PDT 24 941037640 ps
T392 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3701344719 Jul 14 05:31:27 PM PDT 24 Jul 14 05:31:50 PM PDT 24 24157438103 ps
T393 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.290456187 Jul 14 05:32:00 PM PDT 24 Jul 14 05:32:07 PM PDT 24 185857627 ps
T394 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3416222073 Jul 14 05:31:47 PM PDT 24 Jul 14 05:31:51 PM PDT 24 143853542 ps
T395 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1171222973 Jul 14 05:31:43 PM PDT 24 Jul 14 05:31:45 PM PDT 24 594755168 ps
T396 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.388083017 Jul 14 05:31:27 PM PDT 24 Jul 14 05:31:29 PM PDT 24 36673443 ps
T397 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.4163018656 Jul 14 05:31:30 PM PDT 24 Jul 14 05:31:55 PM PDT 24 7460892193 ps
T398 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.824109681 Jul 14 05:32:05 PM PDT 24 Jul 14 05:32:08 PM PDT 24 157053140 ps
T399 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3396126478 Jul 14 05:32:00 PM PDT 24 Jul 14 05:32:08 PM PDT 24 3189940854 ps
T400 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1506218588 Jul 14 05:31:26 PM PDT 24 Jul 14 05:34:52 PM PDT 24 108794997048 ps
T401 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1250812801 Jul 14 05:31:22 PM PDT 24 Jul 14 05:31:25 PM PDT 24 176078482 ps
T402 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2618224312 Jul 14 05:31:44 PM PDT 24 Jul 14 05:31:47 PM PDT 24 62468248 ps
T403 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1856325866 Jul 14 05:31:44 PM PDT 24 Jul 14 05:31:48 PM PDT 24 374098033 ps
T404 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3229617903 Jul 14 05:31:22 PM PDT 24 Jul 14 05:32:18 PM PDT 24 1532230863 ps
T405 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.863480181 Jul 14 05:31:25 PM PDT 24 Jul 14 05:33:16 PM PDT 24 40300076026 ps
T406 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2472349136 Jul 14 05:31:32 PM PDT 24 Jul 14 05:31:39 PM PDT 24 130216947 ps
T186 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2379992262 Jul 14 05:31:33 PM PDT 24 Jul 14 05:31:48 PM PDT 24 1278276714 ps
T407 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2279440347 Jul 14 05:31:29 PM PDT 24 Jul 14 05:31:38 PM PDT 24 563396900 ps
T408 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2517650415 Jul 14 05:31:55 PM PDT 24 Jul 14 05:31:58 PM PDT 24 452311362 ps
T116 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1297381059 Jul 14 05:32:08 PM PDT 24 Jul 14 05:32:12 PM PDT 24 61460821 ps
T409 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3528319661 Jul 14 05:31:22 PM PDT 24 Jul 14 05:31:25 PM PDT 24 146243417 ps
T410 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4077093048 Jul 14 05:31:29 PM PDT 24 Jul 14 05:31:32 PM PDT 24 250448732 ps
T411 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1266015466 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:37 PM PDT 24 297062696 ps
T412 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1354092475 Jul 14 05:32:02 PM PDT 24 Jul 14 05:32:05 PM PDT 24 89760963 ps
T413 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2766901872 Jul 14 05:31:24 PM PDT 24 Jul 14 05:31:29 PM PDT 24 748823732 ps
T414 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1889030493 Jul 14 05:32:02 PM PDT 24 Jul 14 05:32:05 PM PDT 24 1207931730 ps
T415 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.352034727 Jul 14 05:31:43 PM PDT 24 Jul 14 05:31:47 PM PDT 24 2293745955 ps
T416 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.668652369 Jul 14 05:32:07 PM PDT 24 Jul 14 05:32:19 PM PDT 24 1527628500 ps
T417 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3929604127 Jul 14 05:31:56 PM PDT 24 Jul 14 05:31:58 PM PDT 24 441879997 ps
T418 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3198430495 Jul 14 05:31:24 PM PDT 24 Jul 14 05:31:30 PM PDT 24 3712042762 ps
T419 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3529645085 Jul 14 05:31:27 PM PDT 24 Jul 14 05:31:32 PM PDT 24 308424857 ps
T420 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2402825166 Jul 14 05:31:56 PM PDT 24 Jul 14 05:32:11 PM PDT 24 1815061338 ps
T421 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.692662644 Jul 14 05:31:32 PM PDT 24 Jul 14 05:31:41 PM PDT 24 247529669 ps
T422 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3630539951 Jul 14 05:31:33 PM PDT 24 Jul 14 05:31:42 PM PDT 24 378349196 ps
T423 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1243611633 Jul 14 05:31:25 PM PDT 24 Jul 14 05:32:07 PM PDT 24 43695483939 ps
T424 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2447796711 Jul 14 05:31:32 PM PDT 24 Jul 14 05:32:16 PM PDT 24 68665673768 ps
T425 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1947001547 Jul 14 05:31:28 PM PDT 24 Jul 14 05:31:39 PM PDT 24 1291609160 ps
T426 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3772732710 Jul 14 05:31:59 PM PDT 24 Jul 14 05:32:02 PM PDT 24 1399038914 ps
T117 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2599102381 Jul 14 05:31:22 PM PDT 24 Jul 14 05:32:45 PM PDT 24 8598066080 ps
T427 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2175768050 Jul 14 05:31:28 PM PDT 24 Jul 14 05:31:40 PM PDT 24 6622159672 ps
T428 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3319693287 Jul 14 05:31:43 PM PDT 24 Jul 14 05:31:46 PM PDT 24 2650767491 ps
T429 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3649471019 Jul 14 05:31:56 PM PDT 24 Jul 14 05:32:00 PM PDT 24 2095353532 ps
T430 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1928938117 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:42 PM PDT 24 16747369164 ps
T431 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.198709104 Jul 14 05:31:25 PM PDT 24 Jul 14 05:31:28 PM PDT 24 106981699 ps
T432 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.617755594 Jul 14 05:32:00 PM PDT 24 Jul 14 05:32:03 PM PDT 24 178172515 ps
T433 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1786235014 Jul 14 05:31:34 PM PDT 24 Jul 14 05:31:41 PM PDT 24 849612446 ps
T434 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3448220304 Jul 14 05:31:25 PM PDT 24 Jul 14 05:31:30 PM PDT 24 2467364607 ps
T182 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2415222632 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:51 PM PDT 24 3741477421 ps
T435 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1465154877 Jul 14 05:31:22 PM PDT 24 Jul 14 05:31:26 PM PDT 24 184843421 ps
T436 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2673620331 Jul 14 05:32:08 PM PDT 24 Jul 14 05:32:17 PM PDT 24 5345050757 ps
T437 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3968092389 Jul 14 05:31:46 PM PDT 24 Jul 14 05:31:50 PM PDT 24 1714564549 ps
T438 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1683775524 Jul 14 05:31:25 PM PDT 24 Jul 14 05:31:30 PM PDT 24 236997725 ps
T439 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2720658865 Jul 14 05:31:55 PM PDT 24 Jul 14 05:32:04 PM PDT 24 3178438675 ps
T440 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1870023235 Jul 14 05:31:31 PM PDT 24 Jul 14 05:31:37 PM PDT 24 1956618510 ps
T441 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3067390562 Jul 14 05:31:33 PM PDT 24 Jul 14 05:31:43 PM PDT 24 296669237 ps
T442 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4092062394 Jul 14 05:31:56 PM PDT 24 Jul 14 05:31:58 PM PDT 24 94890419 ps
T443 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2226724022 Jul 14 05:31:38 PM PDT 24 Jul 14 05:31:41 PM PDT 24 249900367 ps
T444 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1575317156 Jul 14 05:31:32 PM PDT 24 Jul 14 05:32:12 PM PDT 24 55395571371 ps
T445 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3385249407 Jul 14 05:31:32 PM PDT 24 Jul 14 05:31:48 PM PDT 24 3438794832 ps

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1631796951
Short name T15
Test name
Test status
Simulation time 11087679527 ps
CPU time 11.18 seconds
Started Jul 14 05:32:22 PM PDT 24
Finished Jul 14 05:32:34 PM PDT 24
Peak memory 213748 kb
Host smart-3fdfb34d-c051-4400-8ac8-fc0f0cbb2f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631796951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1631796951
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.713000901
Short name T34
Test name
Test status
Simulation time 2829890753 ps
CPU time 2.56 seconds
Started Jul 14 05:32:23 PM PDT 24
Finished Jul 14 05:32:26 PM PDT 24
Peak memory 205372 kb
Host smart-a75c1b42-3fd3-42db-948e-50c6fcd515d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713000901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.713000901
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1083781180
Short name T84
Test name
Test status
Simulation time 342572433 ps
CPU time 4.06 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:31:40 PM PDT 24
Peak memory 213216 kb
Host smart-5d422e61-10a3-450c-818e-b28f6b210de2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083781180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1083781180
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.643217536
Short name T6
Test name
Test status
Simulation time 12681612299 ps
CPU time 32.08 seconds
Started Jul 14 05:32:49 PM PDT 24
Finished Jul 14 05:33:23 PM PDT 24
Peak memory 205464 kb
Host smart-f3d9aac5-be91-4c27-9d45-13b8b5683611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643217536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.643217536
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1499956508
Short name T86
Test name
Test status
Simulation time 3206379224 ps
CPU time 22.03 seconds
Started Jul 14 05:31:28 PM PDT 24
Finished Jul 14 05:31:53 PM PDT 24
Peak memory 213180 kb
Host smart-07f18e9b-2032-43b8-97b5-373b0b33adf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499956508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1499956508
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3797279367
Short name T47
Test name
Test status
Simulation time 51486777795 ps
CPU time 77.91 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:32:54 PM PDT 24
Peak memory 221240 kb
Host smart-bbc48730-6804-4f2d-b491-621cfdc8745c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797279367 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3797279367
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2260775960
Short name T2
Test name
Test status
Simulation time 70445686 ps
CPU time 0.77 seconds
Started Jul 14 05:32:47 PM PDT 24
Finished Jul 14 05:32:48 PM PDT 24
Peak memory 205100 kb
Host smart-788cba16-3dc1-442f-9952-fc7809357522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260775960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2260775960
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.1364284260
Short name T13
Test name
Test status
Simulation time 3354940083 ps
CPU time 8.99 seconds
Started Jul 14 05:32:50 PM PDT 24
Finished Jul 14 05:33:02 PM PDT 24
Peak memory 214512 kb
Host smart-a946c65a-a2fd-4d37-973c-545032699d1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364284260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.1364284260
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3474085559
Short name T140
Test name
Test status
Simulation time 79237884280 ps
CPU time 93.92 seconds
Started Jul 14 05:32:19 PM PDT 24
Finished Jul 14 05:33:55 PM PDT 24
Peak memory 215460 kb
Host smart-96933788-e0b8-4328-a9cb-32e60a5cf938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474085559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3474085559
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3211824374
Short name T93
Test name
Test status
Simulation time 5305972892 ps
CPU time 38.2 seconds
Started Jul 14 05:31:33 PM PDT 24
Finished Jul 14 05:32:16 PM PDT 24
Peak memory 205100 kb
Host smart-595cd552-48ff-47e6-b3fa-7d39191ba467
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211824374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3211824374
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2063242347
Short name T17
Test name
Test status
Simulation time 287384006 ps
CPU time 1.45 seconds
Started Jul 14 05:32:11 PM PDT 24
Finished Jul 14 05:32:15 PM PDT 24
Peak memory 205104 kb
Host smart-cfb0e4ce-d3a1-49ef-bbca-4aaf3c6f541d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063242347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2063242347
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.3000040438
Short name T10
Test name
Test status
Simulation time 1609173271 ps
CPU time 3.74 seconds
Started Jul 14 05:32:18 PM PDT 24
Finished Jul 14 05:32:24 PM PDT 24
Peak memory 205272 kb
Host smart-582722e4-4a6e-45fd-8b7b-0fcedcaac240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000040438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3000040438
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.4134918648
Short name T57
Test name
Test status
Simulation time 44274301 ps
CPU time 0.89 seconds
Started Jul 14 05:32:12 PM PDT 24
Finished Jul 14 05:32:15 PM PDT 24
Peak memory 215496 kb
Host smart-51e50fc2-bb75-4a63-a674-85958df0fe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134918648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.4134918648
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2259689638
Short name T83
Test name
Test status
Simulation time 1552137415 ps
CPU time 5.36 seconds
Started Jul 14 05:32:13 PM PDT 24
Finished Jul 14 05:32:20 PM PDT 24
Peak memory 205400 kb
Host smart-66b0509d-5163-40ef-905c-728c74132420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259689638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2259689638
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.673400358
Short name T38
Test name
Test status
Simulation time 314284394 ps
CPU time 1.64 seconds
Started Jul 14 05:32:14 PM PDT 24
Finished Jul 14 05:32:17 PM PDT 24
Peak memory 204964 kb
Host smart-7090dc99-cea0-406a-bb6f-68b9ef2206ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673400358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.673400358
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.1106236982
Short name T31
Test name
Test status
Simulation time 2487113937 ps
CPU time 7.51 seconds
Started Jul 14 05:32:46 PM PDT 24
Finished Jul 14 05:32:55 PM PDT 24
Peak memory 205340 kb
Host smart-f1a75f50-47bb-4399-a982-ae25c56b419a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106236982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.1106236982
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.3673245239
Short name T49
Test name
Test status
Simulation time 378549786 ps
CPU time 0.91 seconds
Started Jul 14 05:32:14 PM PDT 24
Finished Jul 14 05:32:17 PM PDT 24
Peak memory 205096 kb
Host smart-b8095437-bb07-4356-88b1-b5fec0476f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673245239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.3673245239
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.256939293
Short name T71
Test name
Test status
Simulation time 346968289 ps
CPU time 1.87 seconds
Started Jul 14 05:32:18 PM PDT 24
Finished Jul 14 05:32:22 PM PDT 24
Peak memory 228848 kb
Host smart-14f2f566-0d00-4de9-beaa-0ee2d39f2821
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256939293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.256939293
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3696633226
Short name T51
Test name
Test status
Simulation time 1998130428 ps
CPU time 2.61 seconds
Started Jul 14 05:32:34 PM PDT 24
Finished Jul 14 05:32:37 PM PDT 24
Peak memory 205524 kb
Host smart-14c079e2-9ec0-45a0-9683-3aea404be39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696633226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3696633226
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3444231580
Short name T128
Test name
Test status
Simulation time 11847209559 ps
CPU time 31.08 seconds
Started Jul 14 05:32:43 PM PDT 24
Finished Jul 14 05:33:15 PM PDT 24
Peak memory 215884 kb
Host smart-5e14ce78-20fd-4866-a445-ed1fd4e874f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444231580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3444231580
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1972533692
Short name T32
Test name
Test status
Simulation time 146800046 ps
CPU time 1.04 seconds
Started Jul 14 05:32:13 PM PDT 24
Finished Jul 14 05:32:16 PM PDT 24
Peak memory 213372 kb
Host smart-f968ed41-93c0-40ce-ae6e-b3ebbefc0e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972533692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1972533692
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3028721556
Short name T142
Test name
Test status
Simulation time 20346941397 ps
CPU time 17.76 seconds
Started Jul 14 05:32:43 PM PDT 24
Finished Jul 14 05:33:02 PM PDT 24
Peak memory 213292 kb
Host smart-d8531609-c209-4c57-8fc4-aca4c651c8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028721556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3028721556
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1297381059
Short name T116
Test name
Test status
Simulation time 61460821 ps
CPU time 2.13 seconds
Started Jul 14 05:32:08 PM PDT 24
Finished Jul 14 05:32:12 PM PDT 24
Peak memory 213080 kb
Host smart-5f489ecb-07a7-4142-9be5-b3a70505eeca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297381059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1297381059
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2789285933
Short name T46
Test name
Test status
Simulation time 39606872208 ps
CPU time 12.07 seconds
Started Jul 14 05:31:35 PM PDT 24
Finished Jul 14 05:31:50 PM PDT 24
Peak memory 217352 kb
Host smart-d596d3e0-a6f0-4302-9828-ee34c47dfb33
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789285933 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.2789285933
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.21155194
Short name T103
Test name
Test status
Simulation time 590201938 ps
CPU time 7.54 seconds
Started Jul 14 05:31:56 PM PDT 24
Finished Jul 14 05:32:04 PM PDT 24
Peak memory 204844 kb
Host smart-42a74d3a-b904-4946-95c4-053c1f6321db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21155194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_c
sr_outstanding.21155194
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2553138959
Short name T7
Test name
Test status
Simulation time 235394631 ps
CPU time 1.32 seconds
Started Jul 14 05:32:17 PM PDT 24
Finished Jul 14 05:32:21 PM PDT 24
Peak memory 205124 kb
Host smart-2d8496d8-f339-4026-914f-06e89645370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553138959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2553138959
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1541782802
Short name T132
Test name
Test status
Simulation time 4286794514 ps
CPU time 3.87 seconds
Started Jul 14 05:32:10 PM PDT 24
Finished Jul 14 05:32:15 PM PDT 24
Peak memory 204936 kb
Host smart-87bc8d09-f3ac-4a56-b13f-a0b2fde6be35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541782802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1541782802
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.916329628
Short name T22
Test name
Test status
Simulation time 2869460588 ps
CPU time 4.67 seconds
Started Jul 14 05:32:10 PM PDT 24
Finished Jul 14 05:32:17 PM PDT 24
Peak memory 205264 kb
Host smart-ff0d7e5d-bbc5-411b-8076-70d668f6660b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916329628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.916329628
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3558710994
Short name T180
Test name
Test status
Simulation time 3512542632 ps
CPU time 21.34 seconds
Started Jul 14 05:31:36 PM PDT 24
Finished Jul 14 05:32:00 PM PDT 24
Peak memory 213184 kb
Host smart-db4c8bde-5f87-41eb-ac9e-b1e7f879b9a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558710994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3558710994
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1079075528
Short name T138
Test name
Test status
Simulation time 1314602110 ps
CPU time 2.92 seconds
Started Jul 14 05:32:19 PM PDT 24
Finished Jul 14 05:32:24 PM PDT 24
Peak memory 205448 kb
Host smart-86c81273-39b4-4326-b8bd-ab40528402a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079075528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1079075528
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1623891680
Short name T58
Test name
Test status
Simulation time 4374846071 ps
CPU time 13.79 seconds
Started Jul 14 05:32:41 PM PDT 24
Finished Jul 14 05:32:55 PM PDT 24
Peak memory 213568 kb
Host smart-0a544621-d0ea-430c-91e8-8005b960987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623891680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1623891680
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3723315862
Short name T20
Test name
Test status
Simulation time 1172248440 ps
CPU time 1.48 seconds
Started Jul 14 05:32:11 PM PDT 24
Finished Jul 14 05:32:14 PM PDT 24
Peak memory 205104 kb
Host smart-76597661-7566-42f0-9801-6016f7cc177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723315862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3723315862
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.3646596763
Short name T14
Test name
Test status
Simulation time 10159816081 ps
CPU time 16.43 seconds
Started Jul 14 05:32:34 PM PDT 24
Finished Jul 14 05:32:52 PM PDT 24
Peak memory 213644 kb
Host smart-7c2108c7-5f67-40da-b256-f9735902e85e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646596763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3646596763
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3787923486
Short name T144
Test name
Test status
Simulation time 8510390684 ps
CPU time 12.67 seconds
Started Jul 14 05:32:45 PM PDT 24
Finished Jul 14 05:32:59 PM PDT 24
Peak memory 212928 kb
Host smart-eb9a3086-dc83-456c-9d1b-7e21586915ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787923486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3787923486
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.2774010456
Short name T25
Test name
Test status
Simulation time 6677475206 ps
CPU time 6.06 seconds
Started Jul 14 05:32:58 PM PDT 24
Finished Jul 14 05:33:06 PM PDT 24
Peak memory 213476 kb
Host smart-d05c0fd1-e830-4fec-b29a-b60f20989070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774010456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.2774010456
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2366585304
Short name T307
Test name
Test status
Simulation time 583170925 ps
CPU time 1.15 seconds
Started Jul 14 05:31:29 PM PDT 24
Finished Jul 14 05:31:33 PM PDT 24
Peak memory 204608 kb
Host smart-6c3e8b3e-76f3-4b11-935d-6795469ef235
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366585304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2366585304
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3050180755
Short name T168
Test name
Test status
Simulation time 3354581099 ps
CPU time 3.66 seconds
Started Jul 14 05:32:41 PM PDT 24
Finished Jul 14 05:32:46 PM PDT 24
Peak memory 205188 kb
Host smart-4fb64480-93be-4ce1-82d5-c965fb404360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050180755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3050180755
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2772766875
Short name T40
Test name
Test status
Simulation time 1801053930 ps
CPU time 6.54 seconds
Started Jul 14 05:32:42 PM PDT 24
Finished Jul 14 05:32:49 PM PDT 24
Peak memory 205196 kb
Host smart-f0ae351c-204d-4a9f-9e46-3f66571720cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772766875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2772766875
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.983822886
Short name T127
Test name
Test status
Simulation time 6124572633 ps
CPU time 4.73 seconds
Started Jul 14 05:32:45 PM PDT 24
Finished Jul 14 05:32:51 PM PDT 24
Peak memory 214312 kb
Host smart-2850ecd9-5eda-4adc-a8b9-f59935d3481c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983822886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.983822886
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.2163571402
Short name T153
Test name
Test status
Simulation time 3712322827 ps
CPU time 2.99 seconds
Started Jul 14 05:32:50 PM PDT 24
Finished Jul 14 05:32:55 PM PDT 24
Peak memory 205356 kb
Host smart-c61dd47a-672c-4ce7-a5a6-499dc576bd76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163571402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2163571402
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.537351328
Short name T101
Test name
Test status
Simulation time 4180494005 ps
CPU time 3.85 seconds
Started Jul 14 05:31:27 PM PDT 24
Finished Jul 14 05:31:33 PM PDT 24
Peak memory 204872 kb
Host smart-80934ca4-80d3-4384-8efb-341abbbe2a98
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537351328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.537351328
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.496114711
Short name T126
Test name
Test status
Simulation time 1777520205 ps
CPU time 8.73 seconds
Started Jul 14 05:31:27 PM PDT 24
Finished Jul 14 05:31:39 PM PDT 24
Peak memory 213136 kb
Host smart-20f6e939-1919-4e94-9d96-baaa539673c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496114711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.496114711
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3146363502
Short name T30
Test name
Test status
Simulation time 497544720 ps
CPU time 1.19 seconds
Started Jul 14 05:32:07 PM PDT 24
Finished Jul 14 05:32:10 PM PDT 24
Peak memory 205132 kb
Host smart-94539011-2b32-470e-81d2-289a93136d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146363502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3146363502
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1243611633
Short name T423
Test name
Test status
Simulation time 43695483939 ps
CPU time 39.34 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:32:07 PM PDT 24
Peak memory 221204 kb
Host smart-a7af0050-81b9-47f3-a90b-a126c307a8ff
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243611633 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1243611633
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.232848014
Short name T185
Test name
Test status
Simulation time 1238177975 ps
CPU time 11.02 seconds
Started Jul 14 05:31:42 PM PDT 24
Finished Jul 14 05:31:54 PM PDT 24
Peak memory 213124 kb
Host smart-2839a69d-2bcd-43fe-83ba-91d1c22fb454
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232848014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.232848014
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.125996942
Short name T183
Test name
Test status
Simulation time 3673511124 ps
CPU time 21.47 seconds
Started Jul 14 05:31:57 PM PDT 24
Finished Jul 14 05:32:19 PM PDT 24
Peak memory 213108 kb
Host smart-97a59e26-a7b0-4126-b763-1cde2e1d3239
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125996942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.125996942
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2415222632
Short name T182
Test name
Test status
Simulation time 3741477421 ps
CPU time 16.98 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:51 PM PDT 24
Peak memory 213132 kb
Host smart-8767069d-819d-4ac3-8f0c-b0cb867b01f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415222632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2415222632
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.315778233
Short name T27
Test name
Test status
Simulation time 36557033313 ps
CPU time 98.74 seconds
Started Jul 14 05:32:09 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 213724 kb
Host smart-baeb4cf4-e74c-4dea-a038-2395211802c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315778233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.315778233
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2523212072
Short name T135
Test name
Test status
Simulation time 92088272 ps
CPU time 0.8 seconds
Started Jul 14 05:32:07 PM PDT 24
Finished Jul 14 05:32:09 PM PDT 24
Peak memory 204964 kb
Host smart-18ac1f29-833c-42de-88c3-ceaab2246928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523212072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2523212072
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3104970067
Short name T262
Test name
Test status
Simulation time 3477229211 ps
CPU time 6.26 seconds
Started Jul 14 05:32:10 PM PDT 24
Finished Jul 14 05:32:18 PM PDT 24
Peak memory 205352 kb
Host smart-142979a1-bfa9-42b1-8a91-30c0188bcba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104970067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3104970067
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.445968557
Short name T174
Test name
Test status
Simulation time 2354524278 ps
CPU time 7.76 seconds
Started Jul 14 05:32:34 PM PDT 24
Finished Jul 14 05:32:43 PM PDT 24
Peak memory 205724 kb
Host smart-4345787b-f7e4-485c-8d08-24aca1acaa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445968557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.445968557
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2831380114
Short name T171
Test name
Test status
Simulation time 1473436659 ps
CPU time 2.23 seconds
Started Jul 14 05:32:37 PM PDT 24
Finished Jul 14 05:32:40 PM PDT 24
Peak memory 205236 kb
Host smart-28714fb1-df4a-4d6b-9825-f29f2eabe4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831380114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2831380114
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2183690872
Short name T141
Test name
Test status
Simulation time 23321406237 ps
CPU time 41.14 seconds
Started Jul 14 05:32:42 PM PDT 24
Finished Jul 14 05:33:23 PM PDT 24
Peak memory 213656 kb
Host smart-7b08793a-6e29-4001-9d9e-3507d2df6312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183690872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2183690872
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3692195730
Short name T143
Test name
Test status
Simulation time 7573660234 ps
CPU time 20.1 seconds
Started Jul 14 05:32:46 PM PDT 24
Finished Jul 14 05:33:07 PM PDT 24
Peak memory 213772 kb
Host smart-b7058904-d336-4e8c-9e2e-a792d3d0d3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692195730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3692195730
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.953754243
Short name T74
Test name
Test status
Simulation time 8357343991 ps
CPU time 3.52 seconds
Started Jul 14 05:32:49 PM PDT 24
Finished Jul 14 05:32:53 PM PDT 24
Peak memory 213736 kb
Host smart-aa5fb34d-fbfb-4239-afe7-a4a44e1773f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953754243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.953754243
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3278863784
Short name T170
Test name
Test status
Simulation time 1360522239 ps
CPU time 1.6 seconds
Started Jul 14 05:32:44 PM PDT 24
Finished Jul 14 05:32:47 PM PDT 24
Peak memory 213588 kb
Host smart-a920d35a-5300-48bb-95e7-0acd6569f599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278863784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3278863784
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.1412659356
Short name T162
Test name
Test status
Simulation time 2860929337 ps
CPU time 2.75 seconds
Started Jul 14 05:32:44 PM PDT 24
Finished Jul 14 05:32:48 PM PDT 24
Peak memory 213404 kb
Host smart-f545f0b3-c144-435a-810b-84b186154994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412659356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1412659356
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1552631634
Short name T159
Test name
Test status
Simulation time 269235944 ps
CPU time 0.84 seconds
Started Jul 14 05:32:18 PM PDT 24
Finished Jul 14 05:32:21 PM PDT 24
Peak memory 205088 kb
Host smart-ef9daa7f-6051-4bf1-87e6-0c5488a8ea33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552631634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1552631634
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3531148240
Short name T173
Test name
Test status
Simulation time 5053433870 ps
CPU time 4.31 seconds
Started Jul 14 05:32:18 PM PDT 24
Finished Jul 14 05:32:25 PM PDT 24
Peak memory 205408 kb
Host smart-513f56c9-c05c-4848-b81d-6f7699b6426c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531148240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3531148240
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.2451676109
Short name T154
Test name
Test status
Simulation time 4490819606 ps
CPU time 5.05 seconds
Started Jul 14 05:32:18 PM PDT 24
Finished Jul 14 05:32:25 PM PDT 24
Peak memory 205356 kb
Host smart-ea81222a-a63a-454e-8364-49b889a86392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451676109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.2451676109
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.2045422701
Short name T164
Test name
Test status
Simulation time 12681947166 ps
CPU time 12.31 seconds
Started Jul 14 05:33:01 PM PDT 24
Finished Jul 14 05:33:15 PM PDT 24
Peak memory 213600 kb
Host smart-69e007c9-d155-432b-aa4f-158bd96e8aaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045422701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2045422701
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.4280476644
Short name T175
Test name
Test status
Simulation time 2419244267 ps
CPU time 4.61 seconds
Started Jul 14 05:32:25 PM PDT 24
Finished Jul 14 05:32:30 PM PDT 24
Peak memory 214704 kb
Host smart-ac75145a-86db-423b-b432-a14436bf4ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280476644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.4280476644
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2652676445
Short name T130
Test name
Test status
Simulation time 3791336650 ps
CPU time 3.21 seconds
Started Jul 14 05:32:27 PM PDT 24
Finished Jul 14 05:32:31 PM PDT 24
Peak memory 213676 kb
Host smart-48bfa678-a598-4465-aba7-eb37acfbab1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652676445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2652676445
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3031065781
Short name T114
Test name
Test status
Simulation time 2091651970 ps
CPU time 27.13 seconds
Started Jul 14 05:31:29 PM PDT 24
Finished Jul 14 05:31:59 PM PDT 24
Peak memory 212816 kb
Host smart-6e90f9ba-311b-4f0e-8855-0a61caebf7d1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031065781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3031065781
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3229617903
Short name T404
Test name
Test status
Simulation time 1532230863 ps
CPU time 53.35 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:32:18 PM PDT 24
Peak memory 204828 kb
Host smart-2688ca64-e3ff-4f65-a3cf-e1a93a81d04b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229617903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3229617903
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1465154877
Short name T435
Test name
Test status
Simulation time 184843421 ps
CPU time 2.63 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:31:26 PM PDT 24
Peak memory 213228 kb
Host smart-93795537-edb8-45fd-964f-320e809a1872
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465154877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1465154877
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3198430495
Short name T418
Test name
Test status
Simulation time 3712042762 ps
CPU time 4.95 seconds
Started Jul 14 05:31:24 PM PDT 24
Finished Jul 14 05:31:30 PM PDT 24
Peak memory 215352 kb
Host smart-51164cb3-0bc6-4b99-8a3a-4d3930ee14dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198430495 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3198430495
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1764719703
Short name T98
Test name
Test status
Simulation time 189963218 ps
CPU time 1.7 seconds
Started Jul 14 05:31:27 PM PDT 24
Finished Jul 14 05:31:31 PM PDT 24
Peak memory 213144 kb
Host smart-4a5a6443-d681-49ca-877c-1fb93b129852
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764719703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1764719703
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1763259208
Short name T306
Test name
Test status
Simulation time 17927107485 ps
CPU time 18.75 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:31:43 PM PDT 24
Peak memory 204760 kb
Host smart-18519319-ed43-4549-90e6-4e3f28cd89a7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763259208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1763259208
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1478369488
Short name T296
Test name
Test status
Simulation time 10760824640 ps
CPU time 15.68 seconds
Started Jul 14 05:31:24 PM PDT 24
Finished Jul 14 05:31:41 PM PDT 24
Peak memory 204888 kb
Host smart-46e344e0-e1ae-4595-9759-a83bd782fbd9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478369488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.1478369488
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3217523093
Short name T349
Test name
Test status
Simulation time 1603106995 ps
CPU time 2.9 seconds
Started Jul 14 05:31:23 PM PDT 24
Finished Jul 14 05:31:28 PM PDT 24
Peak memory 204848 kb
Host smart-86c971da-63a2-4aba-85d5-cf588956978c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217523093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
217523093
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2276636969
Short name T359
Test name
Test status
Simulation time 197739778 ps
CPU time 0.81 seconds
Started Jul 14 05:31:23 PM PDT 24
Finished Jul 14 05:31:26 PM PDT 24
Peak memory 204624 kb
Host smart-f3810e37-d51a-4cb5-ab4a-737ca037247f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276636969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2276636969
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1658121426
Short name T357
Test name
Test status
Simulation time 11902777788 ps
CPU time 31.49 seconds
Started Jul 14 05:31:26 PM PDT 24
Finished Jul 14 05:31:59 PM PDT 24
Peak memory 204940 kb
Host smart-c3af09e1-3305-4202-8863-31e29effe094
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658121426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1658121426
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3528319661
Short name T409
Test name
Test status
Simulation time 146243417 ps
CPU time 0.85 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:31:25 PM PDT 24
Peak memory 204612 kb
Host smart-3b25915b-17dd-4ed5-90a3-5e209c1aa365
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528319661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3528319661
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1617264387
Short name T335
Test name
Test status
Simulation time 412454167 ps
CPU time 1.02 seconds
Started Jul 14 05:31:23 PM PDT 24
Finished Jul 14 05:31:26 PM PDT 24
Peak memory 204508 kb
Host smart-6e0613ba-0a7c-419f-9761-fce42a0500da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617264387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
617264387
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1250812801
Short name T401
Test name
Test status
Simulation time 176078482 ps
CPU time 0.68 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:31:25 PM PDT 24
Peak memory 204576 kb
Host smart-ba9cbdb1-faa1-4c6c-b408-6735084cdb56
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250812801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1250812801
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1319994989
Short name T297
Test name
Test status
Simulation time 136432858 ps
CPU time 0.97 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:31:27 PM PDT 24
Peak memory 204624 kb
Host smart-ef83f2c1-1d09-4f3b-a93a-21620390f4b4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319994989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1319994989
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2279440347
Short name T407
Test name
Test status
Simulation time 563396900 ps
CPU time 6.47 seconds
Started Jul 14 05:31:29 PM PDT 24
Finished Jul 14 05:31:38 PM PDT 24
Peak memory 204796 kb
Host smart-7e0a4def-86fa-4c3a-9081-491d34bf2dd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279440347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2279440347
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.217418316
Short name T177
Test name
Test status
Simulation time 178667218 ps
CPU time 4.12 seconds
Started Jul 14 05:31:29 PM PDT 24
Finished Jul 14 05:31:36 PM PDT 24
Peak memory 212940 kb
Host smart-490ef9d9-3843-4841-9447-ab0aee5fff8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217418316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.217418316
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.133765189
Short name T179
Test name
Test status
Simulation time 719953301 ps
CPU time 8.9 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:31:36 PM PDT 24
Peak memory 212924 kb
Host smart-e8a0df75-52c1-487f-8061-d6090871c73c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133765189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.133765189
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2599102381
Short name T117
Test name
Test status
Simulation time 8598066080 ps
CPU time 80.41 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:32:45 PM PDT 24
Peak memory 213108 kb
Host smart-fada7b7b-6f74-478d-9104-9e79415596b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599102381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2599102381
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4007443773
Short name T355
Test name
Test status
Simulation time 2459698183 ps
CPU time 33.03 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:31:57 PM PDT 24
Peak memory 213164 kb
Host smart-8576d511-4a1c-4dcb-ae3e-a54e0f00f76b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007443773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4007443773
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1683775524
Short name T438
Test name
Test status
Simulation time 236997725 ps
CPU time 2.53 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:31:30 PM PDT 24
Peak memory 213244 kb
Host smart-7472acc0-69fe-4fa9-982a-e715be77212a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683775524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1683775524
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4053849092
Short name T371
Test name
Test status
Simulation time 4750797866 ps
CPU time 10.95 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:31:38 PM PDT 24
Peak memory 220336 kb
Host smart-546a91a4-5a1f-43e6-995f-fca0d1e89c6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053849092 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.4053849092
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2201681031
Short name T380
Test name
Test status
Simulation time 90932349 ps
CPU time 1.5 seconds
Started Jul 14 05:31:26 PM PDT 24
Finished Jul 14 05:31:29 PM PDT 24
Peak memory 213028 kb
Host smart-64e4d0b0-f6a2-4b0f-8f7b-24eb680b9f9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201681031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2201681031
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.398131604
Short name T320
Test name
Test status
Simulation time 117602927758 ps
CPU time 185.71 seconds
Started Jul 14 05:31:24 PM PDT 24
Finished Jul 14 05:34:31 PM PDT 24
Peak memory 204724 kb
Host smart-0ca5f790-3432-4e51-b292-0db4f28b4f15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398131604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.398131604
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1838288737
Short name T326
Test name
Test status
Simulation time 152234137082 ps
CPU time 167.51 seconds
Started Jul 14 05:31:26 PM PDT 24
Finished Jul 14 05:34:15 PM PDT 24
Peak memory 205660 kb
Host smart-3cb58691-02e8-499f-ad8d-c4c13213c2a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838288737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1838288737
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.4201034476
Short name T300
Test name
Test status
Simulation time 3197653032 ps
CPU time 5.08 seconds
Started Jul 14 05:31:24 PM PDT 24
Finished Jul 14 05:31:31 PM PDT 24
Peak memory 204860 kb
Host smart-dcdd7446-61c0-4e87-a4dc-43bc1c6d4b1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201034476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.4201034476
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.733776186
Short name T316
Test name
Test status
Simulation time 2006626237 ps
CPU time 6.58 seconds
Started Jul 14 05:31:27 PM PDT 24
Finished Jul 14 05:31:36 PM PDT 24
Peak memory 204876 kb
Host smart-0acfccc1-bec0-466e-8917-acc59961e4c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733776186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.733776186
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2960387319
Short name T342
Test name
Test status
Simulation time 539142694 ps
CPU time 0.9 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:31:25 PM PDT 24
Peak memory 204484 kb
Host smart-de2945fc-35cc-41c1-bc1b-eaa152afaea5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960387319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2960387319
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3039730817
Short name T314
Test name
Test status
Simulation time 2652808789 ps
CPU time 7.59 seconds
Started Jul 14 05:31:23 PM PDT 24
Finished Jul 14 05:31:33 PM PDT 24
Peak memory 204888 kb
Host smart-071b68e0-47d5-4b71-abbe-2f8754f79d48
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039730817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3039730817
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1687722886
Short name T340
Test name
Test status
Simulation time 719631818 ps
CPU time 1.84 seconds
Started Jul 14 05:31:21 PM PDT 24
Finished Jul 14 05:31:25 PM PDT 24
Peak memory 204608 kb
Host smart-b137c34b-0f82-465c-b54f-0e515b970b91
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687722886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1687722886
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.48457737
Short name T378
Test name
Test status
Simulation time 435613385 ps
CPU time 1.21 seconds
Started Jul 14 05:31:27 PM PDT 24
Finished Jul 14 05:31:30 PM PDT 24
Peak memory 204620 kb
Host smart-3c400b42-ef6a-48fc-a1c3-714ebf01e846
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48457737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.48457737
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.388083017
Short name T396
Test name
Test status
Simulation time 36673443 ps
CPU time 0.73 seconds
Started Jul 14 05:31:27 PM PDT 24
Finished Jul 14 05:31:29 PM PDT 24
Peak memory 204508 kb
Host smart-b40c7f0f-68e9-48da-bde6-b038875b731a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388083017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.388083017
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3624707738
Short name T304
Test name
Test status
Simulation time 107746877 ps
CPU time 0.71 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:31:28 PM PDT 24
Peak memory 204616 kb
Host smart-980bbdac-d1bf-4f78-8008-1c4fda704bc0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624707738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3624707738
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2267491955
Short name T384
Test name
Test status
Simulation time 1010672579 ps
CPU time 7.5 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:42 PM PDT 24
Peak memory 204800 kb
Host smart-9b46f32f-f204-4652-a621-78bdcc9bd95b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267491955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2267491955
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3701344719
Short name T392
Test name
Test status
Simulation time 24157438103 ps
CPU time 21.14 seconds
Started Jul 14 05:31:27 PM PDT 24
Finished Jul 14 05:31:50 PM PDT 24
Peak memory 221400 kb
Host smart-7c25a779-de54-481a-a015-8b6bbe81bb5a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701344719 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3701344719
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2871423219
Short name T368
Test name
Test status
Simulation time 3834585188 ps
CPU time 4.19 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:31:31 PM PDT 24
Peak memory 213176 kb
Host smart-73b80188-a1ab-4a20-8840-7911101377d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871423219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2871423219
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.352034727
Short name T415
Test name
Test status
Simulation time 2293745955 ps
CPU time 2.64 seconds
Started Jul 14 05:31:43 PM PDT 24
Finished Jul 14 05:31:47 PM PDT 24
Peak memory 215792 kb
Host smart-05929d2e-bab7-42f3-8054-d194eb3b435b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352034727 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.352034727
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2375626067
Short name T360
Test name
Test status
Simulation time 171290798 ps
CPU time 1.56 seconds
Started Jul 14 05:31:39 PM PDT 24
Finished Jul 14 05:31:42 PM PDT 24
Peak memory 213152 kb
Host smart-40cfa695-cf0d-4147-9916-6975c372c7be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375626067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2375626067
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2652078723
Short name T372
Test name
Test status
Simulation time 10073850158 ps
CPU time 5.96 seconds
Started Jul 14 05:31:42 PM PDT 24
Finished Jul 14 05:31:48 PM PDT 24
Peak memory 204932 kb
Host smart-79dda4f3-5c8f-40c6-8aae-31f56086be76
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652078723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.2652078723
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1728978871
Short name T333
Test name
Test status
Simulation time 14017091202 ps
CPU time 38.55 seconds
Started Jul 14 05:31:39 PM PDT 24
Finished Jul 14 05:32:18 PM PDT 24
Peak memory 204940 kb
Host smart-ab070b2e-eadf-4b52-ac55-7ffcb0a33352
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728978871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1728978871
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2226724022
Short name T443
Test name
Test status
Simulation time 249900367 ps
CPU time 1.38 seconds
Started Jul 14 05:31:38 PM PDT 24
Finished Jul 14 05:31:41 PM PDT 24
Peak memory 204616 kb
Host smart-1bbee988-09ae-4d72-af94-ae79b39b38b5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226724022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2226724022
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.842127339
Short name T91
Test name
Test status
Simulation time 190848534 ps
CPU time 3.82 seconds
Started Jul 14 05:31:45 PM PDT 24
Finished Jul 14 05:31:50 PM PDT 24
Peak memory 204884 kb
Host smart-d3d41ac4-6397-401c-b602-2451b38cbdc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842127339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.842127339
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2618224312
Short name T402
Test name
Test status
Simulation time 62468248 ps
CPU time 2.71 seconds
Started Jul 14 05:31:44 PM PDT 24
Finished Jul 14 05:31:47 PM PDT 24
Peak memory 213268 kb
Host smart-7666ef75-7b2b-4b49-b6b4-3ba2b4fdb742
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618224312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2618224312
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3157874182
Short name T370
Test name
Test status
Simulation time 384627188 ps
CPU time 2.43 seconds
Started Jul 14 05:31:47 PM PDT 24
Finished Jul 14 05:31:50 PM PDT 24
Peak memory 216888 kb
Host smart-5d770bc5-65d8-486d-89ec-80662d72c808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157874182 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3157874182
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1556456142
Short name T354
Test name
Test status
Simulation time 187344802 ps
CPU time 1.77 seconds
Started Jul 14 05:31:48 PM PDT 24
Finished Jul 14 05:31:50 PM PDT 24
Peak memory 213072 kb
Host smart-91a13b8f-8040-4143-91a4-4d0f6eeb4f68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556456142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1556456142
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2134083430
Short name T322
Test name
Test status
Simulation time 23506821777 ps
CPU time 8.97 seconds
Started Jul 14 05:31:43 PM PDT 24
Finished Jul 14 05:31:53 PM PDT 24
Peak memory 204916 kb
Host smart-690967fb-c8aa-4e63-bd51-e0a27a163fe2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134083430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.2134083430
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3319693287
Short name T428
Test name
Test status
Simulation time 2650767491 ps
CPU time 2.82 seconds
Started Jul 14 05:31:43 PM PDT 24
Finished Jul 14 05:31:46 PM PDT 24
Peak memory 204880 kb
Host smart-162caa99-40e0-4963-9d26-292437505190
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319693287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3319693287
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1171222973
Short name T395
Test name
Test status
Simulation time 594755168 ps
CPU time 1.43 seconds
Started Jul 14 05:31:43 PM PDT 24
Finished Jul 14 05:31:45 PM PDT 24
Peak memory 204600 kb
Host smart-ed6e80f3-8a00-4dc5-83ce-abef3c4d7c97
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171222973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1171222973
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1856325866
Short name T403
Test name
Test status
Simulation time 374098033 ps
CPU time 3.84 seconds
Started Jul 14 05:31:44 PM PDT 24
Finished Jul 14 05:31:48 PM PDT 24
Peak memory 204900 kb
Host smart-ee368900-ed4d-476d-afae-3e2cb4b32b77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856325866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1856325866
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.172919114
Short name T313
Test name
Test status
Simulation time 216927575 ps
CPU time 3.3 seconds
Started Jul 14 05:31:44 PM PDT 24
Finished Jul 14 05:31:48 PM PDT 24
Peak memory 213188 kb
Host smart-c70fdabf-e470-486e-863f-346029438655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172919114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.172919114
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2007391755
Short name T178
Test name
Test status
Simulation time 4292765337 ps
CPU time 19 seconds
Started Jul 14 05:31:47 PM PDT 24
Finished Jul 14 05:32:06 PM PDT 24
Peak memory 213088 kb
Host smart-d371a893-36ee-4ea3-a08a-0354416cecca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007391755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
007391755
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2492463808
Short name T65
Test name
Test status
Simulation time 1095640641 ps
CPU time 2.61 seconds
Started Jul 14 05:31:54 PM PDT 24
Finished Jul 14 05:31:57 PM PDT 24
Peak memory 217792 kb
Host smart-07e71173-43fb-4b5e-9c82-d304f0717a65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492463808 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2492463808
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4092062394
Short name T442
Test name
Test status
Simulation time 94890419 ps
CPU time 1.53 seconds
Started Jul 14 05:31:56 PM PDT 24
Finished Jul 14 05:31:58 PM PDT 24
Peak memory 213096 kb
Host smart-fb8c45e3-a727-429f-8322-a6cfe8e529d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092062394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.4092062394
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1192667033
Short name T351
Test name
Test status
Simulation time 17436952389 ps
CPU time 9.39 seconds
Started Jul 14 05:31:48 PM PDT 24
Finished Jul 14 05:31:58 PM PDT 24
Peak memory 204776 kb
Host smart-1a8061c7-b94f-424f-9499-7329ab50866a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192667033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.1192667033
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3968092389
Short name T437
Test name
Test status
Simulation time 1714564549 ps
CPU time 3.44 seconds
Started Jul 14 05:31:46 PM PDT 24
Finished Jul 14 05:31:50 PM PDT 24
Peak memory 204708 kb
Host smart-c3b107f0-3588-4a9e-8add-5ed6b0392a16
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968092389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3968092389
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1696815858
Short name T298
Test name
Test status
Simulation time 216549647 ps
CPU time 0.73 seconds
Started Jul 14 05:31:46 PM PDT 24
Finished Jul 14 05:31:47 PM PDT 24
Peak memory 204616 kb
Host smart-be070d89-b2ae-462e-84fe-4ba2d3416014
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696815858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1696815858
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2252198674
Short name T120
Test name
Test status
Simulation time 171282887 ps
CPU time 3.64 seconds
Started Jul 14 05:31:54 PM PDT 24
Finished Jul 14 05:31:58 PM PDT 24
Peak memory 204944 kb
Host smart-5adb35a0-274c-4698-8828-64d4fec3bbc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252198674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2252198674
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3416222073
Short name T394
Test name
Test status
Simulation time 143853542 ps
CPU time 3.57 seconds
Started Jul 14 05:31:47 PM PDT 24
Finished Jul 14 05:31:51 PM PDT 24
Peak memory 213292 kb
Host smart-cf161d0b-8ade-45dc-aaff-928d569e6aef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416222073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3416222073
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2402825166
Short name T420
Test name
Test status
Simulation time 1815061338 ps
CPU time 14.08 seconds
Started Jul 14 05:31:56 PM PDT 24
Finished Jul 14 05:32:11 PM PDT 24
Peak memory 213124 kb
Host smart-368c5cf1-7560-44db-bf4e-ede7e4980b82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402825166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
402825166
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3772732710
Short name T426
Test name
Test status
Simulation time 1399038914 ps
CPU time 2.82 seconds
Started Jul 14 05:31:59 PM PDT 24
Finished Jul 14 05:32:02 PM PDT 24
Peak memory 217264 kb
Host smart-24f9015e-7f3a-4f29-aef6-6b3d0a9ba2a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772732710 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3772732710
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2517650415
Short name T408
Test name
Test status
Simulation time 452311362 ps
CPU time 2.42 seconds
Started Jul 14 05:31:55 PM PDT 24
Finished Jul 14 05:31:58 PM PDT 24
Peak memory 213096 kb
Host smart-5887b058-e1ff-40a1-b1d8-f928c447d922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517650415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2517650415
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1744703978
Short name T361
Test name
Test status
Simulation time 9223040552 ps
CPU time 8.54 seconds
Started Jul 14 05:31:54 PM PDT 24
Finished Jul 14 05:32:03 PM PDT 24
Peak memory 204752 kb
Host smart-5c9dad63-cf40-4fac-9658-f3339f12f19a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744703978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.1744703978
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2720658865
Short name T439
Test name
Test status
Simulation time 3178438675 ps
CPU time 8.4 seconds
Started Jul 14 05:31:55 PM PDT 24
Finished Jul 14 05:32:04 PM PDT 24
Peak memory 204920 kb
Host smart-a2e8d2f3-5453-4a1b-9227-571636b6ea05
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720658865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2720658865
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3929604127
Short name T417
Test name
Test status
Simulation time 441879997 ps
CPU time 1.36 seconds
Started Jul 14 05:31:56 PM PDT 24
Finished Jul 14 05:31:58 PM PDT 24
Peak memory 204508 kb
Host smart-5e6da680-99b7-4a50-9947-d11da369c4ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929604127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3929604127
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3649471019
Short name T429
Test name
Test status
Simulation time 2095353532 ps
CPU time 4.49 seconds
Started Jul 14 05:31:56 PM PDT 24
Finished Jul 14 05:32:00 PM PDT 24
Peak memory 213152 kb
Host smart-a4621088-8355-4944-a6ea-c8e48404497b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649471019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3649471019
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3396126478
Short name T399
Test name
Test status
Simulation time 3189940854 ps
CPU time 7.08 seconds
Started Jul 14 05:32:00 PM PDT 24
Finished Jul 14 05:32:08 PM PDT 24
Peak memory 221304 kb
Host smart-cb1b551d-6255-47c0-9992-c6954bbdf42f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396126478 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3396126478
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3081910648
Short name T113
Test name
Test status
Simulation time 76768204 ps
CPU time 1.74 seconds
Started Jul 14 05:32:00 PM PDT 24
Finished Jul 14 05:32:03 PM PDT 24
Peak memory 213072 kb
Host smart-b9547c77-6e01-493e-b409-3f41afca3741
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081910648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3081910648
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3092777058
Short name T318
Test name
Test status
Simulation time 24578050004 ps
CPU time 19.62 seconds
Started Jul 14 05:32:00 PM PDT 24
Finished Jul 14 05:32:21 PM PDT 24
Peak memory 204860 kb
Host smart-fd4e8e68-a593-43ec-aa3f-bf906551fe36
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092777058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.3092777058
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1128804572
Short name T319
Test name
Test status
Simulation time 2313200762 ps
CPU time 2.58 seconds
Started Jul 14 05:32:03 PM PDT 24
Finished Jul 14 05:32:07 PM PDT 24
Peak memory 204884 kb
Host smart-845d411d-c5b0-4b2c-a1c4-b805a7a6a4c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128804572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1128804572
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2314888668
Short name T346
Test name
Test status
Simulation time 164570027 ps
CPU time 0.71 seconds
Started Jul 14 05:32:04 PM PDT 24
Finished Jul 14 05:32:05 PM PDT 24
Peak memory 204456 kb
Host smart-fb51ef2a-8254-4884-a25a-7e59380abd16
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314888668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2314888668
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2733370109
Short name T106
Test name
Test status
Simulation time 272361527 ps
CPU time 7.16 seconds
Started Jul 14 05:31:59 PM PDT 24
Finished Jul 14 05:32:06 PM PDT 24
Peak memory 204820 kb
Host smart-ee3c5f76-6cd4-472d-8a21-68ca7dc6af96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733370109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2733370109
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2603038112
Short name T89
Test name
Test status
Simulation time 681569976 ps
CPU time 3 seconds
Started Jul 14 05:32:01 PM PDT 24
Finished Jul 14 05:32:04 PM PDT 24
Peak memory 213244 kb
Host smart-591a3e37-9268-4e3f-ba1f-1917f5dd0370
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603038112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2603038112
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.220301481
Short name T184
Test name
Test status
Simulation time 6453003200 ps
CPU time 25.77 seconds
Started Jul 14 05:31:59 PM PDT 24
Finished Jul 14 05:32:25 PM PDT 24
Peak memory 213204 kb
Host smart-0b44161d-5efe-4690-aef7-dcce897b2877
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220301481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.220301481
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2666126475
Short name T343
Test name
Test status
Simulation time 277927038 ps
CPU time 2.69 seconds
Started Jul 14 05:32:02 PM PDT 24
Finished Jul 14 05:32:05 PM PDT 24
Peak memory 215024 kb
Host smart-609ff6e1-1883-46f1-868e-1e68105c8f2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666126475 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2666126475
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.617755594
Short name T432
Test name
Test status
Simulation time 178172515 ps
CPU time 2.53 seconds
Started Jul 14 05:32:00 PM PDT 24
Finished Jul 14 05:32:03 PM PDT 24
Peak memory 213164 kb
Host smart-6635c4bd-3197-4857-aa2c-5309e5ea2584
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617755594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.617755594
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.390669322
Short name T312
Test name
Test status
Simulation time 20652628540 ps
CPU time 16.77 seconds
Started Jul 14 05:32:02 PM PDT 24
Finished Jul 14 05:32:20 PM PDT 24
Peak memory 204928 kb
Host smart-44248b5f-ebf8-4a88-b4b3-59b517c4f79b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390669322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rv_dm_jtag_dmi_csr_bit_bash.390669322
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3245334530
Short name T362
Test name
Test status
Simulation time 5291421705 ps
CPU time 4.67 seconds
Started Jul 14 05:32:00 PM PDT 24
Finished Jul 14 05:32:05 PM PDT 24
Peak memory 204880 kb
Host smart-d881cf0d-d232-4a58-a4c7-aabf07485699
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245334530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3245334530
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1082197369
Short name T327
Test name
Test status
Simulation time 218479812 ps
CPU time 1.01 seconds
Started Jul 14 05:32:01 PM PDT 24
Finished Jul 14 05:32:02 PM PDT 24
Peak memory 204508 kb
Host smart-7c03c35c-3618-4b6a-b295-1fbf9f1fc5c0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082197369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1082197369
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.290456187
Short name T393
Test name
Test status
Simulation time 185857627 ps
CPU time 6.56 seconds
Started Jul 14 05:32:00 PM PDT 24
Finished Jul 14 05:32:07 PM PDT 24
Peak memory 204928 kb
Host smart-1f52b50e-9d8b-4adc-b5c7-6e5084eec3fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290456187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_
csr_outstanding.290456187
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1354092475
Short name T412
Test name
Test status
Simulation time 89760963 ps
CPU time 2.02 seconds
Started Jul 14 05:32:02 PM PDT 24
Finished Jul 14 05:32:05 PM PDT 24
Peak memory 213236 kb
Host smart-80e8d397-31c8-48c9-895c-4b804541a9c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354092475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1354092475
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2916941769
Short name T329
Test name
Test status
Simulation time 1574133960 ps
CPU time 8.91 seconds
Started Jul 14 05:32:02 PM PDT 24
Finished Jul 14 05:32:11 PM PDT 24
Peak memory 213148 kb
Host smart-2fd4d06f-b56e-41e4-9e4d-a1132992b6a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916941769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
916941769
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3605296098
Short name T88
Test name
Test status
Simulation time 145438519 ps
CPU time 2.66 seconds
Started Jul 14 05:32:08 PM PDT 24
Finished Jul 14 05:32:12 PM PDT 24
Peak memory 217304 kb
Host smart-40c697f7-8d72-49cd-9058-cac10ebcf7ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605296098 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3605296098
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1269030954
Short name T367
Test name
Test status
Simulation time 19717006668 ps
CPU time 35.36 seconds
Started Jul 14 05:32:04 PM PDT 24
Finished Jul 14 05:32:40 PM PDT 24
Peak memory 204888 kb
Host smart-eb603928-129a-4a18-a2ff-0a730c8f46c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269030954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.1269030954
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1889030493
Short name T414
Test name
Test status
Simulation time 1207931730 ps
CPU time 1.86 seconds
Started Jul 14 05:32:02 PM PDT 24
Finished Jul 14 05:32:05 PM PDT 24
Peak memory 204724 kb
Host smart-4ed28d26-397a-444b-afbb-3469fd839ee1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889030493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1889030493
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.106212530
Short name T336
Test name
Test status
Simulation time 512534091 ps
CPU time 2.07 seconds
Started Jul 14 05:32:00 PM PDT 24
Finished Jul 14 05:32:03 PM PDT 24
Peak memory 204608 kb
Host smart-52ac66c5-1f17-41ae-8823-0e595ee95a21
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106212530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.106212530
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.704036697
Short name T104
Test name
Test status
Simulation time 1362100522 ps
CPU time 8.22 seconds
Started Jul 14 05:32:05 PM PDT 24
Finished Jul 14 05:32:13 PM PDT 24
Peak memory 204948 kb
Host smart-804fa70c-fd58-4e9b-8f2f-c148dcb0535f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704036697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.704036697
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.4108530386
Short name T68
Test name
Test status
Simulation time 260007421 ps
CPU time 5.14 seconds
Started Jul 14 05:32:08 PM PDT 24
Finished Jul 14 05:32:15 PM PDT 24
Peak memory 213260 kb
Host smart-b29b4df7-22c8-417a-9659-01c7dcab74e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108530386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.4108530386
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.499037742
Short name T125
Test name
Test status
Simulation time 1755226773 ps
CPU time 10.7 seconds
Started Jul 14 05:32:06 PM PDT 24
Finished Jul 14 05:32:19 PM PDT 24
Peak memory 213140 kb
Host smart-dd75aab1-073d-49a9-a092-b87010a6baa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499037742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.499037742
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4038466146
Short name T356
Test name
Test status
Simulation time 4914276047 ps
CPU time 2.68 seconds
Started Jul 14 05:32:07 PM PDT 24
Finished Jul 14 05:32:12 PM PDT 24
Peak memory 213204 kb
Host smart-74e6c627-b47b-48ac-ad2d-a7d4b45d4c08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038466146 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.4038466146
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2685288513
Short name T110
Test name
Test status
Simulation time 156994416 ps
CPU time 1.67 seconds
Started Jul 14 05:32:06 PM PDT 24
Finished Jul 14 05:32:09 PM PDT 24
Peak memory 213080 kb
Host smart-4cc8d0ab-f452-4f84-8354-524d4c6c211a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685288513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2685288513
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.297492713
Short name T382
Test name
Test status
Simulation time 4828238238 ps
CPU time 11.11 seconds
Started Jul 14 05:32:06 PM PDT 24
Finished Jul 14 05:32:18 PM PDT 24
Peak memory 204872 kb
Host smart-a7d1cfb1-44de-47cf-aac5-5e81c523d3da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297492713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.297492713
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1707094603
Short name T358
Test name
Test status
Simulation time 6035285874 ps
CPU time 5.44 seconds
Started Jul 14 05:32:09 PM PDT 24
Finished Jul 14 05:32:17 PM PDT 24
Peak memory 204928 kb
Host smart-b5c03ac0-2766-4a16-831b-e892965bc3ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707094603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1707094603
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2033768035
Short name T80
Test name
Test status
Simulation time 459990291 ps
CPU time 1.68 seconds
Started Jul 14 05:32:07 PM PDT 24
Finished Jul 14 05:32:10 PM PDT 24
Peak memory 204404 kb
Host smart-5ee7cf18-5bd7-46c6-a6e6-2c56800a8ccd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033768035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2033768035
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3008494860
Short name T121
Test name
Test status
Simulation time 466596055 ps
CPU time 7.99 seconds
Started Jul 14 05:32:06 PM PDT 24
Finished Jul 14 05:32:15 PM PDT 24
Peak memory 204936 kb
Host smart-cc4cdb04-c44d-4a4d-ac75-76233f6f62c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008494860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3008494860
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3749336841
Short name T377
Test name
Test status
Simulation time 246511138 ps
CPU time 5.14 seconds
Started Jul 14 05:32:07 PM PDT 24
Finished Jul 14 05:32:14 PM PDT 24
Peak memory 213520 kb
Host smart-a9d6e78c-5eb2-4526-bf64-3e912ac51bca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749336841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3749336841
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.487750168
Short name T123
Test name
Test status
Simulation time 861581517 ps
CPU time 10.3 seconds
Started Jul 14 05:32:08 PM PDT 24
Finished Jul 14 05:32:20 PM PDT 24
Peak memory 213116 kb
Host smart-38b20faa-0069-436a-936e-1e71bf1ee41f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487750168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.487750168
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1412192260
Short name T347
Test name
Test status
Simulation time 3222512859 ps
CPU time 7.79 seconds
Started Jul 14 05:32:06 PM PDT 24
Finished Jul 14 05:32:16 PM PDT 24
Peak memory 213280 kb
Host smart-331ac6e9-7519-4ea4-85d4-a997169665f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412192260 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1412192260
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4176411529
Short name T118
Test name
Test status
Simulation time 193646130 ps
CPU time 2.09 seconds
Started Jul 14 05:32:08 PM PDT 24
Finished Jul 14 05:32:12 PM PDT 24
Peak memory 213168 kb
Host smart-91337c34-ff5a-4103-bf25-8e7ebaad75a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176411529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.4176411529
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1462965799
Short name T348
Test name
Test status
Simulation time 49382618760 ps
CPU time 58.79 seconds
Started Jul 14 05:32:07 PM PDT 24
Finished Jul 14 05:33:08 PM PDT 24
Peak memory 204796 kb
Host smart-137b97e4-5a23-44fb-806e-7d7c7f4454c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462965799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.1462965799
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2673620331
Short name T436
Test name
Test status
Simulation time 5345050757 ps
CPU time 7.91 seconds
Started Jul 14 05:32:08 PM PDT 24
Finished Jul 14 05:32:17 PM PDT 24
Peak memory 204936 kb
Host smart-1da513f8-e14a-4d75-b5c1-213f54abe222
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673620331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2673620331
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2082098587
Short name T325
Test name
Test status
Simulation time 634490947 ps
CPU time 2.45 seconds
Started Jul 14 05:32:05 PM PDT 24
Finished Jul 14 05:32:08 PM PDT 24
Peak memory 204480 kb
Host smart-431f7cac-9cb3-4068-8340-f08faba4c913
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082098587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2082098587
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1186454246
Short name T105
Test name
Test status
Simulation time 324866403 ps
CPU time 3.64 seconds
Started Jul 14 05:32:09 PM PDT 24
Finished Jul 14 05:32:14 PM PDT 24
Peak memory 204884 kb
Host smart-4c21b52c-647b-42af-a6db-2b762edbc4c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186454246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1186454246
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2585580264
Short name T338
Test name
Test status
Simulation time 1210929747 ps
CPU time 4.47 seconds
Started Jul 14 05:32:08 PM PDT 24
Finished Jul 14 05:32:14 PM PDT 24
Peak memory 213016 kb
Host smart-53b7ac3b-4018-45d8-bcef-0545273b3f4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585580264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2585580264
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2001745650
Short name T187
Test name
Test status
Simulation time 1490505246 ps
CPU time 10.57 seconds
Started Jul 14 05:32:11 PM PDT 24
Finished Jul 14 05:32:24 PM PDT 24
Peak memory 213020 kb
Host smart-555bdd0a-6f6f-471b-a191-58a7616a8a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001745650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
001745650
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2389959593
Short name T341
Test name
Test status
Simulation time 118407389 ps
CPU time 2.68 seconds
Started Jul 14 05:32:06 PM PDT 24
Finished Jul 14 05:32:11 PM PDT 24
Peak memory 221272 kb
Host smart-f6aa2fa9-5a9b-45c3-8079-4b9260fbf483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389959593 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2389959593
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.824109681
Short name T398
Test name
Test status
Simulation time 157053140 ps
CPU time 2.23 seconds
Started Jul 14 05:32:05 PM PDT 24
Finished Jul 14 05:32:08 PM PDT 24
Peak memory 213088 kb
Host smart-f5c1dd2d-c442-4b58-9927-1e7bfe9d5c1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824109681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.824109681
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2763655698
Short name T294
Test name
Test status
Simulation time 10100507476 ps
CPU time 18.39 seconds
Started Jul 14 05:32:06 PM PDT 24
Finished Jul 14 05:32:25 PM PDT 24
Peak memory 204876 kb
Host smart-4862f41d-7b94-46ac-bb04-1f7fd7e72d73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763655698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2763655698
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1429623226
Short name T328
Test name
Test status
Simulation time 1105081323 ps
CPU time 3.34 seconds
Started Jul 14 05:32:12 PM PDT 24
Finished Jul 14 05:32:17 PM PDT 24
Peak memory 204804 kb
Host smart-dffd702a-2a10-4164-9108-f84e9532074a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429623226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1429623226
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1317839855
Short name T387
Test name
Test status
Simulation time 263594871 ps
CPU time 1.27 seconds
Started Jul 14 05:32:06 PM PDT 24
Finished Jul 14 05:32:09 PM PDT 24
Peak memory 204516 kb
Host smart-ac93c763-c11c-47d7-9e9c-9d46633c8f3c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317839855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1317839855
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1408379226
Short name T109
Test name
Test status
Simulation time 1192245173 ps
CPU time 3.68 seconds
Started Jul 14 05:32:07 PM PDT 24
Finished Jul 14 05:32:12 PM PDT 24
Peak memory 204812 kb
Host smart-8e9c2929-805b-404c-b0a2-5d35ddb473ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408379226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1408379226
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.443932429
Short name T67
Test name
Test status
Simulation time 593452760 ps
CPU time 4.71 seconds
Started Jul 14 05:32:07 PM PDT 24
Finished Jul 14 05:32:14 PM PDT 24
Peak memory 213248 kb
Host smart-f753ae8d-d702-4063-8646-113af0c12cc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443932429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.443932429
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.668652369
Short name T416
Test name
Test status
Simulation time 1527628500 ps
CPU time 11.09 seconds
Started Jul 14 05:32:07 PM PDT 24
Finished Jul 14 05:32:19 PM PDT 24
Peak memory 213088 kb
Host smart-927f4162-1d06-45f1-b978-d9c177643cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668652369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.668652369
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1601752216
Short name T112
Test name
Test status
Simulation time 6888538913 ps
CPU time 74.95 seconds
Started Jul 14 05:31:28 PM PDT 24
Finished Jul 14 05:32:45 PM PDT 24
Peak memory 213140 kb
Host smart-b11b736c-8353-4e5c-bd20-1c674c95e608
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601752216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1601752216
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3352334071
Short name T115
Test name
Test status
Simulation time 3207996147 ps
CPU time 36.13 seconds
Started Jul 14 05:31:27 PM PDT 24
Finished Jul 14 05:32:05 PM PDT 24
Peak memory 213212 kb
Host smart-2dd628e9-8c60-47ae-999a-e5dc8541dcaa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352334071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3352334071
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3019165962
Short name T97
Test name
Test status
Simulation time 278276052 ps
CPU time 2.35 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:31:29 PM PDT 24
Peak memory 213484 kb
Host smart-5ad238d7-6244-4512-b71a-9574d98268ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019165962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3019165962
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3016326790
Short name T364
Test name
Test status
Simulation time 4508352503 ps
CPU time 3.85 seconds
Started Jul 14 05:31:34 PM PDT 24
Finished Jul 14 05:31:42 PM PDT 24
Peak memory 217440 kb
Host smart-834f41ff-4221-45a0-9b16-2d373567c11c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016326790 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3016326790
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2302774916
Short name T92
Test name
Test status
Simulation time 87959008 ps
CPU time 1.51 seconds
Started Jul 14 05:31:27 PM PDT 24
Finished Jul 14 05:31:31 PM PDT 24
Peak memory 213052 kb
Host smart-7f018f20-8ad6-4966-971b-7d697e86d91a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302774916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2302774916
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2944934379
Short name T388
Test name
Test status
Simulation time 45306736143 ps
CPU time 69.19 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:32:36 PM PDT 24
Peak memory 204884 kb
Host smart-efbb091c-441d-42e4-bda2-09a712bc9e6e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944934379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2944934379
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3448220304
Short name T434
Test name
Test status
Simulation time 2467364607 ps
CPU time 3.22 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:31:30 PM PDT 24
Peak memory 204772 kb
Host smart-0e16accf-be4f-4801-962b-96ad6919db9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448220304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.3448220304
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1368320551
Short name T102
Test name
Test status
Simulation time 1111026812 ps
CPU time 3.87 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:31:30 PM PDT 24
Peak memory 204948 kb
Host smart-b47f74d2-5a9e-4fe0-85e0-4eb3c012b546
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368320551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1368320551
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1147831218
Short name T391
Test name
Test status
Simulation time 941037640 ps
CPU time 2.09 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:31:29 PM PDT 24
Peak memory 204736 kb
Host smart-c0a02045-cfdf-488c-92c0-91e19bb000ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147831218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
147831218
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.731141719
Short name T79
Test name
Test status
Simulation time 570324677 ps
CPU time 2.24 seconds
Started Jul 14 05:31:26 PM PDT 24
Finished Jul 14 05:31:31 PM PDT 24
Peak memory 204492 kb
Host smart-7e3de61a-0427-46c8-aa51-af6a5503d67d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731141719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.731141719
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.841149725
Short name T301
Test name
Test status
Simulation time 41778497719 ps
CPU time 28.16 seconds
Started Jul 14 05:31:22 PM PDT 24
Finished Jul 14 05:31:52 PM PDT 24
Peak memory 204836 kb
Host smart-3e9fa5c8-440d-4605-8126-e7ef49a7c840
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841149725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.841149725
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.198709104
Short name T431
Test name
Test status
Simulation time 106981699 ps
CPU time 0.78 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:31:28 PM PDT 24
Peak memory 204608 kb
Host smart-fcd3af25-4336-441f-b57a-95a30ffae1cc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198709104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.198709104
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2663831054
Short name T331
Test name
Test status
Simulation time 161562250 ps
CPU time 0.7 seconds
Started Jul 14 05:31:26 PM PDT 24
Finished Jul 14 05:31:29 PM PDT 24
Peak memory 204488 kb
Host smart-77850d76-e646-4060-a971-16e871a1ed4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663831054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
663831054
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.945908858
Short name T373
Test name
Test status
Simulation time 40585473 ps
CPU time 0.72 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:35 PM PDT 24
Peak memory 204636 kb
Host smart-4c117780-d5b2-4401-ab09-cfd9247559e1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945908858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.945908858
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4077093048
Short name T410
Test name
Test status
Simulation time 250448732 ps
CPU time 0.7 seconds
Started Jul 14 05:31:29 PM PDT 24
Finished Jul 14 05:31:32 PM PDT 24
Peak memory 204580 kb
Host smart-53a562d5-6ce0-43e2-8dfa-4e0f5d592ddb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077093048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.4077093048
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3529645085
Short name T419
Test name
Test status
Simulation time 308424857 ps
CPU time 3.34 seconds
Started Jul 14 05:31:27 PM PDT 24
Finished Jul 14 05:31:32 PM PDT 24
Peak memory 204844 kb
Host smart-41e6317d-d070-4fba-b47e-9dd241dbd640
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529645085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3529645085
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1870023235
Short name T440
Test name
Test status
Simulation time 1956618510 ps
CPU time 3.42 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:37 PM PDT 24
Peak memory 213176 kb
Host smart-5a13ea90-c59e-48ce-98a7-1815aa463a89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870023235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1870023235
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3871424953
Short name T344
Test name
Test status
Simulation time 4798585726 ps
CPU time 63.65 seconds
Started Jul 14 05:31:29 PM PDT 24
Finished Jul 14 05:32:35 PM PDT 24
Peak memory 213020 kb
Host smart-06a870d0-e7b9-444a-86ec-9eac9f2362d2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871424953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3871424953
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3615812216
Short name T386
Test name
Test status
Simulation time 1550668532 ps
CPU time 52.11 seconds
Started Jul 14 05:31:29 PM PDT 24
Finished Jul 14 05:32:24 PM PDT 24
Peak memory 204788 kb
Host smart-41ebf704-18ce-4974-9b16-50607882ab24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615812216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3615812216
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3507228070
Short name T70
Test name
Test status
Simulation time 150332348 ps
CPU time 1.67 seconds
Started Jul 14 05:31:34 PM PDT 24
Finished Jul 14 05:31:40 PM PDT 24
Peak memory 213124 kb
Host smart-ce3a1b2a-dbda-4b66-bf5b-da3014613626
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507228070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3507228070
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2766901872
Short name T413
Test name
Test status
Simulation time 748823732 ps
CPU time 2.61 seconds
Started Jul 14 05:31:24 PM PDT 24
Finished Jul 14 05:31:29 PM PDT 24
Peak memory 218080 kb
Host smart-b8d1602d-4728-4bc8-9215-0b7f950ee5d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766901872 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2766901872
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2227888544
Short name T96
Test name
Test status
Simulation time 285451096 ps
CPU time 1.62 seconds
Started Jul 14 05:31:34 PM PDT 24
Finished Jul 14 05:31:39 PM PDT 24
Peak memory 212744 kb
Host smart-31c00137-dc1e-4609-975b-4a23756f1ecd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227888544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2227888544
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1575317156
Short name T444
Test name
Test status
Simulation time 55395571371 ps
CPU time 35.7 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:32:12 PM PDT 24
Peak memory 204672 kb
Host smart-999a90cb-2ecf-409b-a5c8-03f4f5f76042
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575317156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1575317156
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2195079191
Short name T299
Test name
Test status
Simulation time 14000573742 ps
CPU time 36.43 seconds
Started Jul 14 05:31:29 PM PDT 24
Finished Jul 14 05:32:07 PM PDT 24
Peak memory 204868 kb
Host smart-599ebdc3-5dc1-45b7-b148-13408cf6adb2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195079191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.2195079191
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3007861046
Short name T100
Test name
Test status
Simulation time 9115222329 ps
CPU time 25.12 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:32:01 PM PDT 24
Peak memory 204752 kb
Host smart-99d89d98-16a2-4754-8caf-4809aed5f18a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007861046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3007861046
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2175768050
Short name T427
Test name
Test status
Simulation time 6622159672 ps
CPU time 10.41 seconds
Started Jul 14 05:31:28 PM PDT 24
Finished Jul 14 05:31:40 PM PDT 24
Peak memory 204924 kb
Host smart-802b8066-60f8-463b-ad14-189376e78d65
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175768050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
175768050
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2497216828
Short name T317
Test name
Test status
Simulation time 286704983 ps
CPU time 0.87 seconds
Started Jul 14 05:31:29 PM PDT 24
Finished Jul 14 05:31:33 PM PDT 24
Peak memory 204608 kb
Host smart-1f6f545a-2839-46b8-844b-0f168a730b95
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497216828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2497216828
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.863480181
Short name T405
Test name
Test status
Simulation time 40300076026 ps
CPU time 110.11 seconds
Started Jul 14 05:31:25 PM PDT 24
Finished Jul 14 05:33:16 PM PDT 24
Peak memory 204780 kb
Host smart-e09f8561-622c-4c45-acf0-04cbf358b3bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863480181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.863480181
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1121397296
Short name T321
Test name
Test status
Simulation time 237574381 ps
CPU time 1.05 seconds
Started Jul 14 05:31:28 PM PDT 24
Finished Jul 14 05:31:32 PM PDT 24
Peak memory 204596 kb
Host smart-2bd489d8-c38a-4c5c-b0bf-c0c533f503ab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121397296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
121397296
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3527533742
Short name T311
Test name
Test status
Simulation time 122359165 ps
CPU time 0.73 seconds
Started Jul 14 05:31:29 PM PDT 24
Finished Jul 14 05:31:32 PM PDT 24
Peak memory 204604 kb
Host smart-1bd7dfc3-180c-4634-a682-7df582c2144f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527533742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3527533742
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1595076592
Short name T369
Test name
Test status
Simulation time 133873938 ps
CPU time 0.96 seconds
Started Jul 14 05:31:27 PM PDT 24
Finished Jul 14 05:31:31 PM PDT 24
Peak memory 204608 kb
Host smart-461f9c49-0c92-4dc4-b1e9-ee32d721d521
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595076592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1595076592
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1610948935
Short name T379
Test name
Test status
Simulation time 335070673 ps
CPU time 3.74 seconds
Started Jul 14 05:31:26 PM PDT 24
Finished Jul 14 05:31:31 PM PDT 24
Peak memory 204944 kb
Host smart-164291d9-3f9c-4570-87ce-57aa4d8e65ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610948935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1610948935
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2981307479
Short name T324
Test name
Test status
Simulation time 272950693 ps
CPU time 3.14 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:37 PM PDT 24
Peak memory 213252 kb
Host smart-d7f066c9-2af9-460f-93a1-dca112441bc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981307479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2981307479
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1947001547
Short name T425
Test name
Test status
Simulation time 1291609160 ps
CPU time 8.54 seconds
Started Jul 14 05:31:28 PM PDT 24
Finished Jul 14 05:31:39 PM PDT 24
Peak memory 213080 kb
Host smart-8685c5d0-3704-47d5-a878-df6dcd2bcc8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947001547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1947001547
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3137916872
Short name T107
Test name
Test status
Simulation time 3792069889 ps
CPU time 72.44 seconds
Started Jul 14 05:31:34 PM PDT 24
Finished Jul 14 05:32:50 PM PDT 24
Peak memory 204976 kb
Host smart-fff43a4c-2c9e-46c3-94af-3630c698e2f1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137916872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3137916872
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2858467323
Short name T108
Test name
Test status
Simulation time 496225460 ps
CPU time 2.25 seconds
Started Jul 14 05:31:34 PM PDT 24
Finished Jul 14 05:31:40 PM PDT 24
Peak memory 213240 kb
Host smart-8b285d84-8d05-4cba-b2df-b4631beb1b71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858467323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2858467323
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2516527147
Short name T315
Test name
Test status
Simulation time 3643802254 ps
CPU time 8.64 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:42 PM PDT 24
Peak memory 219428 kb
Host smart-104b7418-c938-4f6e-b505-44c4bbf3716f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516527147 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2516527147
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.239599474
Short name T111
Test name
Test status
Simulation time 201721629 ps
CPU time 1.44 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:31:37 PM PDT 24
Peak memory 213100 kb
Host smart-3d081cfc-8e5a-450f-a4c9-6a31a617fe97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239599474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.239599474
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1506218588
Short name T400
Test name
Test status
Simulation time 108794997048 ps
CPU time 204.26 seconds
Started Jul 14 05:31:26 PM PDT 24
Finished Jul 14 05:34:52 PM PDT 24
Peak memory 204948 kb
Host smart-aeb11066-5374-4306-8f71-17eb1db9032f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506218588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1506218588
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.485299584
Short name T303
Test name
Test status
Simulation time 35386998611 ps
CPU time 87.47 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:33:01 PM PDT 24
Peak memory 204940 kb
Host smart-3dc3e8b2-5c29-40ae-8906-6806417b4daf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485299584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.485299584
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2108395827
Short name T99
Test name
Test status
Simulation time 10384960032 ps
CPU time 6.14 seconds
Started Jul 14 05:31:33 PM PDT 24
Finished Jul 14 05:31:44 PM PDT 24
Peak memory 204684 kb
Host smart-e95bbb26-a94f-4b15-9a59-f2aa8c89cc23
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108395827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2108395827
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3900533670
Short name T334
Test name
Test status
Simulation time 7364137869 ps
CPU time 18.39 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:31:54 PM PDT 24
Peak memory 204916 kb
Host smart-7b9f8ec0-3adc-448b-aa77-9998ab16456d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900533670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
900533670
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3807007217
Short name T308
Test name
Test status
Simulation time 2497526534 ps
CPU time 2.48 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:36 PM PDT 24
Peak memory 204676 kb
Host smart-2ad17591-a0a7-4793-8e37-3b7bb65fb840
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807007217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3807007217
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1928938117
Short name T430
Test name
Test status
Simulation time 16747369164 ps
CPU time 6.28 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:42 PM PDT 24
Peak memory 204200 kb
Host smart-c9ee73f0-391c-45f5-9ea2-c41372096d15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928938117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1928938117
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1786235014
Short name T433
Test name
Test status
Simulation time 849612446 ps
CPU time 2.75 seconds
Started Jul 14 05:31:34 PM PDT 24
Finished Jul 14 05:31:41 PM PDT 24
Peak memory 204252 kb
Host smart-fdfa4377-8aaa-41b2-a331-215b1eceb59c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786235014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1786235014
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.773253943
Short name T339
Test name
Test status
Simulation time 374850115 ps
CPU time 1.12 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:35 PM PDT 24
Peak memory 204504 kb
Host smart-8bf9e48a-a310-4719-be42-37478d352d8f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773253943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.773253943
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3660365281
Short name T345
Test name
Test status
Simulation time 64742150 ps
CPU time 0.67 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:36 PM PDT 24
Peak memory 204616 kb
Host smart-650f67cf-3d80-4e15-b91d-bcddf1245151
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660365281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3660365281
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2139425530
Short name T295
Test name
Test status
Simulation time 221504679 ps
CPU time 0.66 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:31:37 PM PDT 24
Peak memory 204244 kb
Host smart-ff152b55-d7e0-4308-861c-45add468cd90
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139425530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2139425530
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3067390562
Short name T441
Test name
Test status
Simulation time 296669237 ps
CPU time 6.31 seconds
Started Jul 14 05:31:33 PM PDT 24
Finished Jul 14 05:31:43 PM PDT 24
Peak memory 204892 kb
Host smart-d48da5ab-b3e7-436f-ac92-dc7d9bc61692
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067390562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3067390562
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.692662644
Short name T421
Test name
Test status
Simulation time 247529669 ps
CPU time 5.1 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:31:41 PM PDT 24
Peak memory 213016 kb
Host smart-592b2b3d-a68d-4827-9bfa-a1db1be281d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692662644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.692662644
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2624227519
Short name T124
Test name
Test status
Simulation time 462060258 ps
CPU time 2.58 seconds
Started Jul 14 05:31:33 PM PDT 24
Finished Jul 14 05:31:40 PM PDT 24
Peak memory 220728 kb
Host smart-e2815b5f-3de7-485a-9aec-142a95238a02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624227519 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2624227519
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1266015466
Short name T411
Test name
Test status
Simulation time 297062696 ps
CPU time 2.06 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:37 PM PDT 24
Peak memory 213144 kb
Host smart-7dc4867c-ec62-476f-8e4d-19be46a039e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266015466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1266015466
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.124801760
Short name T309
Test name
Test status
Simulation time 12941213859 ps
CPU time 32.87 seconds
Started Jul 14 05:31:33 PM PDT 24
Finished Jul 14 05:32:10 PM PDT 24
Peak memory 204800 kb
Host smart-c319cbf2-5764-46ce-963b-a02a4af8723f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124801760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r
v_dm_jtag_dmi_csr_bit_bash.124801760
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1150510964
Short name T330
Test name
Test status
Simulation time 2667976408 ps
CPU time 7.17 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:42 PM PDT 24
Peak memory 204804 kb
Host smart-85af2202-e2b4-4676-acf8-0932354b9f39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150510964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
150510964
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1988699514
Short name T350
Test name
Test status
Simulation time 136728865 ps
CPU time 0.73 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:36 PM PDT 24
Peak memory 203828 kb
Host smart-7b87b77e-6879-475a-a473-2135dad22093
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988699514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
988699514
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2454516619
Short name T376
Test name
Test status
Simulation time 1410965896 ps
CPU time 8.31 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:42 PM PDT 24
Peak memory 204800 kb
Host smart-db6ef3a0-0704-4e4d-bbd5-da78c4b865cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454516619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2454516619
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2447796711
Short name T424
Test name
Test status
Simulation time 68665673768 ps
CPU time 39.23 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:32:16 PM PDT 24
Peak memory 229652 kb
Host smart-44433a5c-7c4c-41a2-8d6a-678afdaa7be7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447796711 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2447796711
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1660837723
Short name T176
Test name
Test status
Simulation time 158589567 ps
CPU time 3.28 seconds
Started Jul 14 05:31:33 PM PDT 24
Finished Jul 14 05:31:41 PM PDT 24
Peak memory 212824 kb
Host smart-369f5c38-412c-4e9e-ba64-2c2f6c6f405e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660837723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1660837723
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3385249407
Short name T445
Test name
Test status
Simulation time 3438794832 ps
CPU time 12.16 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:31:48 PM PDT 24
Peak memory 213216 kb
Host smart-fcef5d59-e980-4681-80ce-c6b6f2487f61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385249407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3385249407
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2472349136
Short name T406
Test name
Test status
Simulation time 130216947 ps
CPU time 2.87 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:31:39 PM PDT 24
Peak memory 218388 kb
Host smart-97580de3-d088-4082-8c83-81356fb1791a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472349136 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2472349136
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2060777189
Short name T337
Test name
Test status
Simulation time 143231694 ps
CPU time 2.42 seconds
Started Jul 14 05:31:35 PM PDT 24
Finished Jul 14 05:31:41 PM PDT 24
Peak memory 212972 kb
Host smart-6338495e-3d24-4e3e-8b61-33b74ed789ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060777189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2060777189
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3497356228
Short name T365
Test name
Test status
Simulation time 2027725643 ps
CPU time 5.87 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:31:42 PM PDT 24
Peak memory 204744 kb
Host smart-a90d69e7-4db1-4cc3-abc9-feca372b3c89
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497356228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.3497356228
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.4226043345
Short name T305
Test name
Test status
Simulation time 9026055970 ps
CPU time 25.51 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:32:02 PM PDT 24
Peak memory 204872 kb
Host smart-4edefc87-2309-484d-91b1-533c6b1d79e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226043345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.4
226043345
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4138097724
Short name T332
Test name
Test status
Simulation time 198424281 ps
CPU time 0.77 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:31:37 PM PDT 24
Peak memory 204584 kb
Host smart-d0e36b46-c2f9-46cd-958b-c8758d78d7d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138097724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.4
138097724
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1881734931
Short name T119
Test name
Test status
Simulation time 1382010646 ps
CPU time 6.86 seconds
Started Jul 14 05:31:34 PM PDT 24
Finished Jul 14 05:31:45 PM PDT 24
Peak memory 204804 kb
Host smart-71b5f117-37cb-402c-a79a-c6fd95edda7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881734931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1881734931
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3630539951
Short name T422
Test name
Test status
Simulation time 378349196 ps
CPU time 4.97 seconds
Started Jul 14 05:31:33 PM PDT 24
Finished Jul 14 05:31:42 PM PDT 24
Peak memory 213264 kb
Host smart-70f45c21-54a8-4d4e-b009-958a0d4a740a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630539951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3630539951
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1746445453
Short name T181
Test name
Test status
Simulation time 3660627218 ps
CPU time 19.11 seconds
Started Jul 14 05:31:34 PM PDT 24
Finished Jul 14 05:31:57 PM PDT 24
Peak memory 213096 kb
Host smart-79635b3a-d38e-4880-8684-9084a7c4fac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746445453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1746445453
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2755572287
Short name T64
Test name
Test status
Simulation time 195874122 ps
CPU time 3.87 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:39 PM PDT 24
Peak memory 221368 kb
Host smart-7b94f85c-1ade-417d-ae59-1864fcfea6f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755572287 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2755572287
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3071422288
Short name T374
Test name
Test status
Simulation time 166970310 ps
CPU time 1.5 seconds
Started Jul 14 05:31:33 PM PDT 24
Finished Jul 14 05:31:39 PM PDT 24
Peak memory 213140 kb
Host smart-cb467502-f3cb-4af1-ba45-75aad7af54f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071422288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3071422288
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.4163018656
Short name T397
Test name
Test status
Simulation time 7460892193 ps
CPU time 22.06 seconds
Started Jul 14 05:31:30 PM PDT 24
Finished Jul 14 05:31:55 PM PDT 24
Peak memory 204852 kb
Host smart-7fa8e919-58a8-4830-bd18-8fc3c8be01d9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163018656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.4163018656
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3424615701
Short name T363
Test name
Test status
Simulation time 2293730740 ps
CPU time 7.09 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:42 PM PDT 24
Peak memory 204932 kb
Host smart-0d613dd2-070b-4395-8f2e-2dc6dc025e72
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424615701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
424615701
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4285052693
Short name T81
Test name
Test status
Simulation time 879336687 ps
CPU time 1.31 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:31:37 PM PDT 24
Peak memory 204572 kb
Host smart-c7446d47-0a4b-4369-b1a9-6a04959b9965
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285052693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.4
285052693
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2285460858
Short name T69
Test name
Test status
Simulation time 463908702 ps
CPU time 6.22 seconds
Started Jul 14 05:31:33 PM PDT 24
Finished Jul 14 05:31:43 PM PDT 24
Peak memory 204876 kb
Host smart-04c4dd73-abf8-4df9-ba0b-213d39b6ff41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285460858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2285460858
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2145266526
Short name T385
Test name
Test status
Simulation time 29785001995 ps
CPU time 80.81 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:32:57 PM PDT 24
Peak memory 221392 kb
Host smart-49fe8501-c990-4ca7-b7f0-384774491802
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145266526 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2145266526
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2756194513
Short name T87
Test name
Test status
Simulation time 805578697 ps
CPU time 4.62 seconds
Started Jul 14 05:31:31 PM PDT 24
Finished Jul 14 05:31:40 PM PDT 24
Peak memory 221436 kb
Host smart-228d8498-09c1-49c2-ac1d-e6422d01b5d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756194513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2756194513
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2379992262
Short name T186
Test name
Test status
Simulation time 1278276714 ps
CPU time 10.01 seconds
Started Jul 14 05:31:33 PM PDT 24
Finished Jul 14 05:31:48 PM PDT 24
Peak memory 213032 kb
Host smart-6fdb3da9-e899-47ef-a737-b5f9832d6cfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379992262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2379992262
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1283573815
Short name T352
Test name
Test status
Simulation time 644002805 ps
CPU time 2.45 seconds
Started Jul 14 05:31:30 PM PDT 24
Finished Jul 14 05:31:35 PM PDT 24
Peak memory 217828 kb
Host smart-a2e9b426-7222-4fd8-9585-fa0a89d1222e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283573815 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1283573815
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2987983988
Short name T390
Test name
Test status
Simulation time 174343621 ps
CPU time 2.18 seconds
Started Jul 14 05:31:34 PM PDT 24
Finished Jul 14 05:31:40 PM PDT 24
Peak memory 213088 kb
Host smart-5b1beaa5-6224-4b78-939b-25097114aad8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987983988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2987983988
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1196269778
Short name T389
Test name
Test status
Simulation time 11898145311 ps
CPU time 18.72 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:31:54 PM PDT 24
Peak memory 204780 kb
Host smart-36639a8e-c234-466c-8c21-cb0c8c1b32bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196269778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.1196269778
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2126088524
Short name T302
Test name
Test status
Simulation time 2596077058 ps
CPU time 4.79 seconds
Started Jul 14 05:31:35 PM PDT 24
Finished Jul 14 05:31:43 PM PDT 24
Peak memory 204912 kb
Host smart-bf58d511-766c-4189-b898-8e17b6bb7db1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126088524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2
126088524
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2677645330
Short name T366
Test name
Test status
Simulation time 732449420 ps
CPU time 1.03 seconds
Started Jul 14 05:31:33 PM PDT 24
Finished Jul 14 05:31:39 PM PDT 24
Peak memory 204540 kb
Host smart-4a538ad8-7c7f-4e70-8164-8131c6bf4054
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677645330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
677645330
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.774458652
Short name T353
Test name
Test status
Simulation time 612011295 ps
CPU time 4.7 seconds
Started Jul 14 05:31:32 PM PDT 24
Finished Jul 14 05:31:41 PM PDT 24
Peak memory 204880 kb
Host smart-cbfd24ae-699c-4ab0-b4da-54bd41a47361
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774458652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.774458652
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.387228026
Short name T188
Test name
Test status
Simulation time 41983269670 ps
CPU time 44.5 seconds
Started Jul 14 05:31:33 PM PDT 24
Finished Jul 14 05:32:22 PM PDT 24
Peak memory 221332 kb
Host smart-78b9f608-2e8a-4a5a-abd2-4c3be1ac1ed9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387228026 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.387228026
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.477608794
Short name T66
Test name
Test status
Simulation time 277018658 ps
CPU time 2.77 seconds
Started Jul 14 05:31:39 PM PDT 24
Finished Jul 14 05:31:43 PM PDT 24
Peak memory 214944 kb
Host smart-bc9f009a-a4d7-46e5-b41d-4aaad34e8f77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477608794 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.477608794
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1685727419
Short name T95
Test name
Test status
Simulation time 144990446 ps
CPU time 2.46 seconds
Started Jul 14 05:31:40 PM PDT 24
Finished Jul 14 05:31:43 PM PDT 24
Peak memory 213064 kb
Host smart-644f8ba0-3973-4e78-ab74-fc5d5b27dea4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685727419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1685727419
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1512308714
Short name T383
Test name
Test status
Simulation time 1981666640 ps
CPU time 6.68 seconds
Started Jul 14 05:31:39 PM PDT 24
Finished Jul 14 05:31:47 PM PDT 24
Peak memory 204740 kb
Host smart-c8d7b711-5934-4b64-b00a-e3f7dcd6b05b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512308714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.1512308714
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.307589531
Short name T323
Test name
Test status
Simulation time 2869088448 ps
CPU time 3.96 seconds
Started Jul 14 05:31:38 PM PDT 24
Finished Jul 14 05:31:43 PM PDT 24
Peak memory 204724 kb
Host smart-adb87fbe-2a38-4bda-936f-d91e0dcd1ce0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307589531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.307589531
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.370931096
Short name T310
Test name
Test status
Simulation time 306114915 ps
CPU time 0.85 seconds
Started Jul 14 05:31:41 PM PDT 24
Finished Jul 14 05:31:42 PM PDT 24
Peak memory 204612 kb
Host smart-e0ca72e8-11de-4a4e-ab7e-db1c942e5f39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370931096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.370931096
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1507013564
Short name T94
Test name
Test status
Simulation time 428067797 ps
CPU time 7.3 seconds
Started Jul 14 05:31:38 PM PDT 24
Finished Jul 14 05:31:46 PM PDT 24
Peak memory 204908 kb
Host smart-9e3f5db1-b350-4141-a27b-1857826c1cdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507013564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1507013564
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3758510040
Short name T375
Test name
Test status
Simulation time 50635019799 ps
CPU time 137.24 seconds
Started Jul 14 05:31:37 PM PDT 24
Finished Jul 14 05:33:56 PM PDT 24
Peak memory 220028 kb
Host smart-e333c870-1a7f-4a3a-ba9d-bdd791f9ff1a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758510040 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3758510040
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2318488616
Short name T381
Test name
Test status
Simulation time 242615336 ps
CPU time 5.1 seconds
Started Jul 14 05:31:38 PM PDT 24
Finished Jul 14 05:31:44 PM PDT 24
Peak memory 213220 kb
Host smart-f24be71e-ac30-4356-aa10-b4d2013cfab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318488616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2318488616
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.151268357
Short name T85
Test name
Test status
Simulation time 1585948298 ps
CPU time 10.94 seconds
Started Jul 14 05:31:37 PM PDT 24
Finished Jul 14 05:31:50 PM PDT 24
Peak memory 213152 kb
Host smart-8df90f9d-d360-4028-b3ef-6725ed008dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151268357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.151268357
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.4274681980
Short name T76
Test name
Test status
Simulation time 46337683 ps
CPU time 0.79 seconds
Started Jul 14 05:32:11 PM PDT 24
Finished Jul 14 05:32:14 PM PDT 24
Peak memory 205008 kb
Host smart-b9870e91-9021-4927-858c-27d96c95c80d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274681980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.4274681980
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2637151084
Short name T16
Test name
Test status
Simulation time 2837565888 ps
CPU time 1.86 seconds
Started Jul 14 05:32:11 PM PDT 24
Finished Jul 14 05:32:14 PM PDT 24
Peak memory 205120 kb
Host smart-a0e2c28f-6f92-4522-b616-883d0fd40d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637151084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2637151084
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1793118676
Short name T131
Test name
Test status
Simulation time 293762530 ps
CPU time 0.88 seconds
Started Jul 14 05:32:09 PM PDT 24
Finished Jul 14 05:32:11 PM PDT 24
Peak memory 205116 kb
Host smart-630a676d-3130-48fd-abc2-1e97f112c4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793118676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1793118676
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1767720750
Short name T145
Test name
Test status
Simulation time 5245054969 ps
CPU time 15.01 seconds
Started Jul 14 05:32:10 PM PDT 24
Finished Jul 14 05:32:27 PM PDT 24
Peak memory 205356 kb
Host smart-0aaa5fe8-fb25-4cda-9073-324beaa95786
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767720750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1767720750
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1856979196
Short name T4
Test name
Test status
Simulation time 318463371 ps
CPU time 1.22 seconds
Started Jul 14 05:32:11 PM PDT 24
Finished Jul 14 05:32:15 PM PDT 24
Peak memory 205092 kb
Host smart-a297ae37-a697-45cc-a8c3-fe61818b4559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856979196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1856979196
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2233673893
Short name T269
Test name
Test status
Simulation time 185403374 ps
CPU time 0.92 seconds
Started Jul 14 05:32:07 PM PDT 24
Finished Jul 14 05:32:10 PM PDT 24
Peak memory 205312 kb
Host smart-f66dda47-1789-4fcb-8410-b1b5c3009571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233673893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2233673893
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1870906477
Short name T61
Test name
Test status
Simulation time 542800240 ps
CPU time 1.07 seconds
Started Jul 14 05:32:10 PM PDT 24
Finished Jul 14 05:32:13 PM PDT 24
Peak memory 204996 kb
Host smart-d4cabc35-3ea6-4e1a-878f-9cdf88e9b4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870906477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1870906477
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4294866601
Short name T271
Test name
Test status
Simulation time 2553294656 ps
CPU time 3.84 seconds
Started Jul 14 05:32:12 PM PDT 24
Finished Jul 14 05:32:18 PM PDT 24
Peak memory 204976 kb
Host smart-8b3f5547-7b01-47d4-9948-98b575200367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294866601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4294866601
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.629667963
Short name T264
Test name
Test status
Simulation time 1487492460 ps
CPU time 1.73 seconds
Started Jul 14 05:32:15 PM PDT 24
Finished Jul 14 05:32:18 PM PDT 24
Peak memory 205132 kb
Host smart-6252c669-eb83-43e9-8b77-2e16d5047d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629667963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.629667963
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2994615367
Short name T275
Test name
Test status
Simulation time 449326150 ps
CPU time 1.26 seconds
Started Jul 14 05:32:12 PM PDT 24
Finished Jul 14 05:32:15 PM PDT 24
Peak memory 205020 kb
Host smart-335663a7-498f-4b71-a8c6-5a1535ba762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994615367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2994615367
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3490637060
Short name T60
Test name
Test status
Simulation time 951881723 ps
CPU time 1.86 seconds
Started Jul 14 05:32:10 PM PDT 24
Finished Jul 14 05:32:13 PM PDT 24
Peak memory 204540 kb
Host smart-774d8fd3-b797-4e76-83c4-f16310047de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490637060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3490637060
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3757197684
Short name T198
Test name
Test status
Simulation time 1318892621 ps
CPU time 2.02 seconds
Started Jul 14 05:32:06 PM PDT 24
Finished Jul 14 05:32:08 PM PDT 24
Peak memory 205216 kb
Host smart-4ac282fd-7106-4448-ac0e-da6b8abbe149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757197684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3757197684
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1134840245
Short name T199
Test name
Test status
Simulation time 556703644 ps
CPU time 1.97 seconds
Started Jul 14 05:32:13 PM PDT 24
Finished Jul 14 05:32:17 PM PDT 24
Peak memory 205004 kb
Host smart-299284e6-58f7-4ebf-aa73-3692da1bf87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134840245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1134840245
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.956723195
Short name T37
Test name
Test status
Simulation time 219285842 ps
CPU time 0.81 seconds
Started Jul 14 05:32:14 PM PDT 24
Finished Jul 14 05:32:17 PM PDT 24
Peak memory 205124 kb
Host smart-ac009a65-0dd3-48a0-830a-2db283fa8643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956723195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.956723195
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3175500328
Short name T43
Test name
Test status
Simulation time 1520625890 ps
CPU time 2.68 seconds
Started Jul 14 05:32:14 PM PDT 24
Finished Jul 14 05:32:19 PM PDT 24
Peak memory 228792 kb
Host smart-0211402c-ad12-44f9-bc3a-47770a53a455
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175500328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3175500328
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2689779164
Short name T255
Test name
Test status
Simulation time 3017428596 ps
CPU time 5.68 seconds
Started Jul 14 05:32:09 PM PDT 24
Finished Jul 14 05:32:17 PM PDT 24
Peak memory 205164 kb
Host smart-64003790-21bf-421a-b0d8-09b946918d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689779164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2689779164
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.909819892
Short name T193
Test name
Test status
Simulation time 4284888113 ps
CPU time 6.03 seconds
Started Jul 14 05:32:11 PM PDT 24
Finished Jul 14 05:32:19 PM PDT 24
Peak memory 213544 kb
Host smart-2beebeb4-745f-4e8f-8c91-eef6ff6519ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909819892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.909819892
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2483611929
Short name T45
Test name
Test status
Simulation time 9336567753 ps
CPU time 14.98 seconds
Started Jul 14 05:32:10 PM PDT 24
Finished Jul 14 05:32:26 PM PDT 24
Peak memory 205308 kb
Host smart-191d9c05-2bca-40f2-bd03-11c5f4c361ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483611929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2483611929
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.678071375
Short name T35
Test name
Test status
Simulation time 269220053 ps
CPU time 0.89 seconds
Started Jul 14 05:32:20 PM PDT 24
Finished Jul 14 05:32:23 PM PDT 24
Peak memory 205132 kb
Host smart-6fef13c5-4980-48ff-8830-761dc0644033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678071375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.678071375
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.4109633686
Short name T233
Test name
Test status
Simulation time 136189252 ps
CPU time 1.01 seconds
Started Jul 14 05:32:19 PM PDT 24
Finished Jul 14 05:32:22 PM PDT 24
Peak memory 205052 kb
Host smart-6c855447-24b3-4650-8d1c-ccca3b37fa3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109633686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4109633686
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2437708878
Short name T256
Test name
Test status
Simulation time 6892499955 ps
CPU time 5.18 seconds
Started Jul 14 05:32:12 PM PDT 24
Finished Jul 14 05:32:19 PM PDT 24
Peak memory 205628 kb
Host smart-d5c4711c-586e-4530-9632-9436a584deb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437708878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2437708878
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.679684273
Short name T289
Test name
Test status
Simulation time 902207339 ps
CPU time 2.28 seconds
Started Jul 14 05:32:11 PM PDT 24
Finished Jul 14 05:32:16 PM PDT 24
Peak memory 205300 kb
Host smart-7f2e8e0d-d51b-4c27-9666-961367351d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679684273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.679684273
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.108541235
Short name T19
Test name
Test status
Simulation time 508695849 ps
CPU time 0.91 seconds
Started Jul 14 05:32:12 PM PDT 24
Finished Jul 14 05:32:15 PM PDT 24
Peak memory 205096 kb
Host smart-381ec5d6-5752-4a4b-8c24-dbee47f4118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108541235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.108541235
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2894857258
Short name T8
Test name
Test status
Simulation time 438121667 ps
CPU time 0.94 seconds
Started Jul 14 05:32:11 PM PDT 24
Finished Jul 14 05:32:14 PM PDT 24
Peak memory 205184 kb
Host smart-ef7e2c64-f4c5-4c9b-83ea-c4b5c478f196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894857258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2894857258
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.963487939
Short name T55
Test name
Test status
Simulation time 215458423 ps
CPU time 0.88 seconds
Started Jul 14 05:32:14 PM PDT 24
Finished Jul 14 05:32:17 PM PDT 24
Peak memory 205100 kb
Host smart-80b1a9c9-0e8c-4518-a79a-807a26c6e5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963487939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.963487939
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2436364917
Short name T197
Test name
Test status
Simulation time 184228619 ps
CPU time 0.75 seconds
Started Jul 14 05:32:12 PM PDT 24
Finished Jul 14 05:32:15 PM PDT 24
Peak memory 205112 kb
Host smart-4e235f35-3ba2-46a5-afe3-5af57643759c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436364917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2436364917
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.1942093258
Short name T63
Test name
Test status
Simulation time 117524453 ps
CPU time 0.88 seconds
Started Jul 14 05:32:18 PM PDT 24
Finished Jul 14 05:32:21 PM PDT 24
Peak memory 215376 kb
Host smart-3a1fc2a4-aa0c-4222-97e0-4fad3044b43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942093258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1942093258
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3377744102
Short name T250
Test name
Test status
Simulation time 2763191388 ps
CPU time 3.21 seconds
Started Jul 14 05:32:12 PM PDT 24
Finished Jul 14 05:32:18 PM PDT 24
Peak memory 213664 kb
Host smart-88bcc31c-32ab-42da-b010-0182ad517a8d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3377744102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3377744102
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.2384551833
Short name T50
Test name
Test status
Simulation time 75297666 ps
CPU time 0.8 seconds
Started Jul 14 05:32:21 PM PDT 24
Finished Jul 14 05:32:23 PM PDT 24
Peak memory 204888 kb
Host smart-508b1ddb-9b44-4199-8f48-0eb6460fc03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384551833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2384551833
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3853134675
Short name T137
Test name
Test status
Simulation time 434332716 ps
CPU time 1.94 seconds
Started Jul 14 05:32:14 PM PDT 24
Finished Jul 14 05:32:18 PM PDT 24
Peak memory 205060 kb
Host smart-a2ca0e46-4602-480d-8d8b-4e42d5517a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853134675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3853134675
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2858615818
Short name T206
Test name
Test status
Simulation time 172268730 ps
CPU time 1.01 seconds
Started Jul 14 05:32:12 PM PDT 24
Finished Jul 14 05:32:16 PM PDT 24
Peak memory 205088 kb
Host smart-934fafa0-bb58-4a85-a9a6-be81c90d1ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858615818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2858615818
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.470758374
Short name T282
Test name
Test status
Simulation time 225960461 ps
CPU time 0.76 seconds
Started Jul 14 05:32:18 PM PDT 24
Finished Jul 14 05:32:21 PM PDT 24
Peak memory 205312 kb
Host smart-aebcfd9f-f88b-47dc-9d9d-90bb430dffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470758374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.470758374
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2553699254
Short name T26
Test name
Test status
Simulation time 1390028912 ps
CPU time 4.51 seconds
Started Jul 14 05:32:17 PM PDT 24
Finished Jul 14 05:32:24 PM PDT 24
Peak memory 205060 kb
Host smart-160bad5c-0f33-4ddf-bb5b-f1c40ba00814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553699254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2553699254
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.861463678
Short name T136
Test name
Test status
Simulation time 161412328 ps
CPU time 1.1 seconds
Started Jul 14 05:32:16 PM PDT 24
Finished Jul 14 05:32:19 PM PDT 24
Peak memory 205132 kb
Host smart-f0446af9-ecd4-421f-a811-4c84fcd19779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861463678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.861463678
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2013054882
Short name T48
Test name
Test status
Simulation time 739731661 ps
CPU time 1.63 seconds
Started Jul 14 05:32:13 PM PDT 24
Finished Jul 14 05:32:17 PM PDT 24
Peak memory 205088 kb
Host smart-a2bf89cc-cb78-44e4-bead-805502157377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013054882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2013054882
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2747530142
Short name T220
Test name
Test status
Simulation time 1751180807 ps
CPU time 5.65 seconds
Started Jul 14 05:32:09 PM PDT 24
Finished Jul 14 05:32:17 PM PDT 24
Peak memory 204988 kb
Host smart-daee64a9-e582-40b1-985c-a1fb7a244487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747530142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2747530142
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1878998127
Short name T248
Test name
Test status
Simulation time 296876753 ps
CPU time 1.5 seconds
Started Jul 14 05:32:09 PM PDT 24
Finished Jul 14 05:32:12 PM PDT 24
Peak memory 205132 kb
Host smart-6a38f26d-e36f-49cc-8d81-da0148499160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878998127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1878998127
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.427582580
Short name T200
Test name
Test status
Simulation time 430599624 ps
CPU time 1.8 seconds
Started Jul 14 05:32:14 PM PDT 24
Finished Jul 14 05:32:18 PM PDT 24
Peak memory 205136 kb
Host smart-01b4e61c-d5ec-4db0-81bf-f9d5bdf026a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427582580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.427582580
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.577150564
Short name T18
Test name
Test status
Simulation time 1129435033 ps
CPU time 1.36 seconds
Started Jul 14 05:32:16 PM PDT 24
Finished Jul 14 05:32:19 PM PDT 24
Peak memory 205112 kb
Host smart-cc741936-03ab-40d8-af6c-4f5baf122a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577150564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.577150564
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1414675943
Short name T33
Test name
Test status
Simulation time 51492761 ps
CPU time 0.89 seconds
Started Jul 14 05:32:17 PM PDT 24
Finished Jul 14 05:32:20 PM PDT 24
Peak memory 213396 kb
Host smart-47f9ac8a-5043-499e-abab-444023eeb533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414675943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1414675943
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2023504609
Short name T82
Test name
Test status
Simulation time 3853542125 ps
CPU time 3.25 seconds
Started Jul 14 05:32:14 PM PDT 24
Finished Jul 14 05:32:19 PM PDT 24
Peak memory 205304 kb
Host smart-f09ec75b-1963-4be5-a832-9d1e4be66a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023504609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2023504609
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.235844906
Short name T53
Test name
Test status
Simulation time 5313260224 ps
CPU time 16.04 seconds
Started Jul 14 05:32:10 PM PDT 24
Finished Jul 14 05:32:28 PM PDT 24
Peak memory 205280 kb
Host smart-d1f11c17-1a77-4394-b302-fcdca2751642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235844906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.235844906
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.605602784
Short name T44
Test name
Test status
Simulation time 476164245 ps
CPU time 2.49 seconds
Started Jul 14 05:32:17 PM PDT 24
Finished Jul 14 05:32:22 PM PDT 24
Peak memory 228812 kb
Host smart-4d0c33b1-7eba-4e4d-a9f1-d135168ec74d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605602784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.605602784
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1016917755
Short name T165
Test name
Test status
Simulation time 1134307401 ps
CPU time 2.17 seconds
Started Jul 14 05:32:09 PM PDT 24
Finished Jul 14 05:32:13 PM PDT 24
Peak memory 205092 kb
Host smart-8fb8fa47-514a-447e-8673-6946f4dc037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016917755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1016917755
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1349464682
Short name T212
Test name
Test status
Simulation time 67885416 ps
CPU time 0.87 seconds
Started Jul 14 05:32:35 PM PDT 24
Finished Jul 14 05:32:36 PM PDT 24
Peak memory 205092 kb
Host smart-914f88f0-050b-4d7d-99bb-e8bccf4a2969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349464682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1349464682
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.981609586
Short name T237
Test name
Test status
Simulation time 55557786701 ps
CPU time 53.27 seconds
Started Jul 14 05:32:28 PM PDT 24
Finished Jul 14 05:33:22 PM PDT 24
Peak memory 213672 kb
Host smart-4c01db7a-744c-45d6-b085-60229b9dc7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981609586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.981609586
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2211926629
Short name T238
Test name
Test status
Simulation time 11274192511 ps
CPU time 5.5 seconds
Started Jul 14 05:32:30 PM PDT 24
Finished Jul 14 05:32:36 PM PDT 24
Peak memory 213772 kb
Host smart-382ee436-f139-4edf-a0e8-fa9c133b1aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211926629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2211926629
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2111915031
Short name T247
Test name
Test status
Simulation time 1387358435 ps
CPU time 4.98 seconds
Started Jul 14 05:32:30 PM PDT 24
Finished Jul 14 05:32:36 PM PDT 24
Peak memory 205380 kb
Host smart-5823443d-5e48-4e9a-8a5a-0ada3e13e0f4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2111915031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2111915031
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.979991865
Short name T253
Test name
Test status
Simulation time 1076206975 ps
CPU time 1.4 seconds
Started Jul 14 05:32:31 PM PDT 24
Finished Jul 14 05:32:34 PM PDT 24
Peak memory 205432 kb
Host smart-ac2797bf-790c-473b-927d-70c60aee351b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979991865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.979991865
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.3581251797
Short name T194
Test name
Test status
Simulation time 11986903955 ps
CPU time 37.95 seconds
Started Jul 14 05:32:28 PM PDT 24
Finished Jul 14 05:33:06 PM PDT 24
Peak memory 221724 kb
Host smart-7c537aae-6faf-4478-afad-2afd91e0a240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581251797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3581251797
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1173885117
Short name T277
Test name
Test status
Simulation time 77663116 ps
CPU time 0.85 seconds
Started Jul 14 05:32:33 PM PDT 24
Finished Jul 14 05:32:35 PM PDT 24
Peak memory 205112 kb
Host smart-bc9d66f7-8534-499c-b06b-33e2db03f3d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173885117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1173885117
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3268543257
Short name T284
Test name
Test status
Simulation time 41453191640 ps
CPU time 32.98 seconds
Started Jul 14 05:32:32 PM PDT 24
Finished Jul 14 05:33:06 PM PDT 24
Peak memory 213640 kb
Host smart-f7ddb6e1-0590-43f1-a3ec-57162c1e3337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268543257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3268543257
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3773750811
Short name T56
Test name
Test status
Simulation time 5528278799 ps
CPU time 15.86 seconds
Started Jul 14 05:32:36 PM PDT 24
Finished Jul 14 05:32:52 PM PDT 24
Peak memory 213588 kb
Host smart-03a9068c-226b-45a2-9f64-4cd7d9d1180e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3773750811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3773750811
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.448622215
Short name T213
Test name
Test status
Simulation time 66159983 ps
CPU time 0.85 seconds
Started Jul 14 05:32:35 PM PDT 24
Finished Jul 14 05:32:36 PM PDT 24
Peak memory 205076 kb
Host smart-b59a0871-c722-4dff-8e60-c579d8d9a614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448622215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.448622215
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.1148939868
Short name T62
Test name
Test status
Simulation time 8416377728 ps
CPU time 14.08 seconds
Started Jul 14 05:32:36 PM PDT 24
Finished Jul 14 05:32:51 PM PDT 24
Peak memory 213684 kb
Host smart-02a24229-e499-4fae-bf57-965ca9663622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148939868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1148939868
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3261546452
Short name T9
Test name
Test status
Simulation time 6243878518 ps
CPU time 16.29 seconds
Started Jul 14 05:32:32 PM PDT 24
Finished Jul 14 05:32:49 PM PDT 24
Peak memory 205528 kb
Host smart-61d916ea-200c-4748-a5f9-5e8eeb34dbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261546452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3261546452
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2553433356
Short name T270
Test name
Test status
Simulation time 2776493777 ps
CPU time 3.56 seconds
Started Jul 14 05:32:34 PM PDT 24
Finished Jul 14 05:32:39 PM PDT 24
Peak memory 213676 kb
Host smart-2807bb17-2ad4-4042-80ac-e04c85f025f1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2553433356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2553433356
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.1076871369
Short name T129
Test name
Test status
Simulation time 1114645515 ps
CPU time 4.07 seconds
Started Jul 14 05:32:37 PM PDT 24
Finished Jul 14 05:32:42 PM PDT 24
Peak memory 205216 kb
Host smart-a8b3c415-be42-40a1-8732-4a06328333f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076871369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1076871369
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.2395590014
Short name T12
Test name
Test status
Simulation time 10470745561 ps
CPU time 11.05 seconds
Started Jul 14 05:32:33 PM PDT 24
Finished Jul 14 05:32:45 PM PDT 24
Peak memory 213572 kb
Host smart-1c0cbe69-369f-42f0-8a31-3c42c127001b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395590014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2395590014
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2290490681
Short name T286
Test name
Test status
Simulation time 119529110 ps
CPU time 0.84 seconds
Started Jul 14 05:32:46 PM PDT 24
Finished Jul 14 05:32:48 PM PDT 24
Peak memory 205108 kb
Host smart-7af79946-789f-4352-83e0-c8443b29cffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290490681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2290490681
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.833289003
Short name T227
Test name
Test status
Simulation time 5220770501 ps
CPU time 7.12 seconds
Started Jul 14 05:32:48 PM PDT 24
Finished Jul 14 05:32:55 PM PDT 24
Peak memory 213684 kb
Host smart-a8f0f7e5-c892-4d23-8a38-0282fa599ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833289003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.833289003
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3445661826
Short name T265
Test name
Test status
Simulation time 8752235720 ps
CPU time 24.11 seconds
Started Jul 14 05:32:34 PM PDT 24
Finished Jul 14 05:33:00 PM PDT 24
Peak memory 213640 kb
Host smart-97005e0d-39ea-4160-9545-109f01e01dd0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445661826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3445661826
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.3275323871
Short name T189
Test name
Test status
Simulation time 6519643197 ps
CPU time 19.02 seconds
Started Jul 14 05:32:41 PM PDT 24
Finished Jul 14 05:33:01 PM PDT 24
Peak memory 213476 kb
Host smart-560e6ac0-be34-435d-909f-32f16f373dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275323871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3275323871
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3193935459
Short name T210
Test name
Test status
Simulation time 57024041 ps
CPU time 0.74 seconds
Started Jul 14 05:32:40 PM PDT 24
Finished Jul 14 05:32:41 PM PDT 24
Peak memory 205108 kb
Host smart-6d5b496a-8409-4bf1-93b4-b699da6c1eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193935459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3193935459
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2587578474
Short name T216
Test name
Test status
Simulation time 3596117091 ps
CPU time 7.43 seconds
Started Jul 14 05:32:48 PM PDT 24
Finished Jul 14 05:32:56 PM PDT 24
Peak memory 213696 kb
Host smart-df2a9ddf-6a49-46a3-a9d5-0d3e7c3e4a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587578474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2587578474
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3156238328
Short name T258
Test name
Test status
Simulation time 5839827156 ps
CPU time 18.63 seconds
Started Jul 14 05:32:44 PM PDT 24
Finished Jul 14 05:33:03 PM PDT 24
Peak memory 205320 kb
Host smart-cffe23e0-294a-4289-b16b-3df7252eed98
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156238328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3156238328
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.345819072
Short name T59
Test name
Test status
Simulation time 4325165271 ps
CPU time 11.12 seconds
Started Jul 14 05:32:41 PM PDT 24
Finished Jul 14 05:32:53 PM PDT 24
Peak memory 205364 kb
Host smart-9f33c05f-e36e-4b60-90c3-7a6b9d45465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345819072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.345819072
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2137871325
Short name T251
Test name
Test status
Simulation time 104989583 ps
CPU time 0.72 seconds
Started Jul 14 05:32:46 PM PDT 24
Finished Jul 14 05:32:48 PM PDT 24
Peak memory 205104 kb
Host smart-fa14d5af-1071-440c-9f50-1acbe2828adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137871325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2137871325
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3800438761
Short name T263
Test name
Test status
Simulation time 2850945616 ps
CPU time 4.84 seconds
Started Jul 14 05:32:41 PM PDT 24
Finished Jul 14 05:32:46 PM PDT 24
Peak memory 213728 kb
Host smart-3c1f702d-b61e-4c49-823b-14d6e8bb1002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800438761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3800438761
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3586883547
Short name T1
Test name
Test status
Simulation time 2098783963 ps
CPU time 7.45 seconds
Started Jul 14 05:32:40 PM PDT 24
Finished Jul 14 05:32:48 PM PDT 24
Peak memory 213600 kb
Host smart-dc7e2f83-4e8e-4aba-bd8e-73a0e0f47f14
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586883547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3586883547
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2775212689
Short name T75
Test name
Test status
Simulation time 4893458520 ps
CPU time 14.71 seconds
Started Jul 14 05:32:39 PM PDT 24
Finished Jul 14 05:32:54 PM PDT 24
Peak memory 213760 kb
Host smart-f00fbb17-0512-466a-893b-499e86644847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775212689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2775212689
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.2739796268
Short name T158
Test name
Test status
Simulation time 3512912151 ps
CPU time 1.93 seconds
Started Jul 14 05:32:43 PM PDT 24
Finished Jul 14 05:32:45 PM PDT 24
Peak memory 205344 kb
Host smart-7a243511-0d8c-49d3-b95e-e21885c6a67b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739796268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.2739796268
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.849195494
Short name T203
Test name
Test status
Simulation time 113980636 ps
CPU time 0.86 seconds
Started Jul 14 05:32:44 PM PDT 24
Finished Jul 14 05:32:46 PM PDT 24
Peak memory 204980 kb
Host smart-4d22ed6c-70a5-4576-979c-652c4a2d9a89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849195494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.849195494
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3946880671
Short name T222
Test name
Test status
Simulation time 33463907182 ps
CPU time 13.4 seconds
Started Jul 14 05:32:41 PM PDT 24
Finished Jul 14 05:32:55 PM PDT 24
Peak memory 213476 kb
Host smart-129c376b-3214-4ba1-8bc0-204b0777f690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946880671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3946880671
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2237776007
Short name T279
Test name
Test status
Simulation time 2000015258 ps
CPU time 2.22 seconds
Started Jul 14 05:32:45 PM PDT 24
Finished Jul 14 05:32:49 PM PDT 24
Peak memory 205472 kb
Host smart-ad5d7a66-6b3c-4e0b-ad33-2a8b3893bce4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2237776007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2237776007
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.4124485991
Short name T274
Test name
Test status
Simulation time 1661970531 ps
CPU time 2.19 seconds
Started Jul 14 05:32:40 PM PDT 24
Finished Jul 14 05:32:43 PM PDT 24
Peak memory 205296 kb
Host smart-c94ce559-68de-4a37-8892-e355aaf520e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124485991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.4124485991
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.422104475
Short name T272
Test name
Test status
Simulation time 88894226 ps
CPU time 0.72 seconds
Started Jul 14 05:32:44 PM PDT 24
Finished Jul 14 05:32:46 PM PDT 24
Peak memory 205124 kb
Host smart-3aeb6d87-ab26-4912-bef9-ff28f64e84ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422104475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.422104475
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3956470820
Short name T257
Test name
Test status
Simulation time 5575629234 ps
CPU time 16.18 seconds
Started Jul 14 05:32:44 PM PDT 24
Finished Jul 14 05:33:02 PM PDT 24
Peak memory 213728 kb
Host smart-51bf2053-cfaa-439b-bcc7-9b4cb8ff1ca9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3956470820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3956470820
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3236544870
Short name T77
Test name
Test status
Simulation time 2395154179 ps
CPU time 2.7 seconds
Started Jul 14 05:32:41 PM PDT 24
Finished Jul 14 05:32:45 PM PDT 24
Peak memory 205560 kb
Host smart-fb1819e9-8032-4631-b2c8-80941e87bb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236544870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3236544870
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.2738552593
Short name T163
Test name
Test status
Simulation time 1394815753 ps
CPU time 1.89 seconds
Started Jul 14 05:32:45 PM PDT 24
Finished Jul 14 05:32:49 PM PDT 24
Peak memory 205244 kb
Host smart-c5c8cc3e-db18-45f5-bdac-ab796ecaab01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738552593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2738552593
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1979040769
Short name T230
Test name
Test status
Simulation time 63854782 ps
CPU time 0.72 seconds
Started Jul 14 05:32:44 PM PDT 24
Finished Jul 14 05:32:47 PM PDT 24
Peak memory 205112 kb
Host smart-5f80e681-0e73-4337-8e4f-504f017c89f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979040769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1979040769
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3294410121
Short name T28
Test name
Test status
Simulation time 5444259845 ps
CPU time 3.89 seconds
Started Jul 14 05:32:44 PM PDT 24
Finished Jul 14 05:32:49 PM PDT 24
Peak memory 215704 kb
Host smart-c4c52267-dc27-4b9a-ab31-3d5713781670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294410121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3294410121
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.620134578
Short name T268
Test name
Test status
Simulation time 1270381254 ps
CPU time 2.71 seconds
Started Jul 14 05:32:49 PM PDT 24
Finished Jul 14 05:32:52 PM PDT 24
Peak memory 205388 kb
Host smart-35d0471c-85ed-4767-8e6a-c0bf5edff1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620134578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.620134578
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.556454515
Short name T78
Test name
Test status
Simulation time 4176147637 ps
CPU time 7.27 seconds
Started Jul 14 05:32:45 PM PDT 24
Finished Jul 14 05:32:54 PM PDT 24
Peak memory 212980 kb
Host smart-846accff-0791-4fc3-9379-476ef9f87478
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=556454515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.556454515
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.4242734688
Short name T172
Test name
Test status
Simulation time 1253707357 ps
CPU time 4.35 seconds
Started Jul 14 05:32:45 PM PDT 24
Finished Jul 14 05:32:51 PM PDT 24
Peak memory 213700 kb
Host smart-41fac966-dfb8-4d44-baa3-fc242a693cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242734688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.4242734688
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1563763275
Short name T122
Test name
Test status
Simulation time 114663793 ps
CPU time 0.83 seconds
Started Jul 14 05:32:48 PM PDT 24
Finished Jul 14 05:32:50 PM PDT 24
Peak memory 205092 kb
Host smart-6180eb86-94f7-495e-af64-9b920ee2a2ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563763275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1563763275
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1500946548
Short name T239
Test name
Test status
Simulation time 1962986895 ps
CPU time 3.07 seconds
Started Jul 14 05:32:45 PM PDT 24
Finished Jul 14 05:32:50 PM PDT 24
Peak memory 213540 kb
Host smart-968d1bf2-5f68-4b2a-af84-a5e51884a20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500946548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1500946548
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1353387673
Short name T149
Test name
Test status
Simulation time 2129659736 ps
CPU time 7.09 seconds
Started Jul 14 05:32:45 PM PDT 24
Finished Jul 14 05:32:53 PM PDT 24
Peak memory 205412 kb
Host smart-05179951-eceb-4c5a-a76b-e15630c09b5d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1353387673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1353387673
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.3016809654
Short name T36
Test name
Test status
Simulation time 4257045219 ps
CPU time 6.23 seconds
Started Jul 14 05:32:48 PM PDT 24
Finished Jul 14 05:32:55 PM PDT 24
Peak memory 205424 kb
Host smart-c7772a5b-6458-4719-8854-bb91042dd090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016809654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3016809654
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2179256909
Short name T259
Test name
Test status
Simulation time 68931154 ps
CPU time 0.79 seconds
Started Jul 14 05:32:27 PM PDT 24
Finished Jul 14 05:32:29 PM PDT 24
Peak memory 205008 kb
Host smart-36b32807-39f1-490e-8400-f2a2176a4b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179256909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2179256909
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3881437983
Short name T52
Test name
Test status
Simulation time 14781388501 ps
CPU time 24.87 seconds
Started Jul 14 05:32:26 PM PDT 24
Finished Jul 14 05:32:52 PM PDT 24
Peak memory 213608 kb
Host smart-009ff1ae-aba8-4b79-9c7b-2f8944bfea60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881437983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3881437983
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2912899058
Short name T267
Test name
Test status
Simulation time 7670891903 ps
CPU time 4.74 seconds
Started Jul 14 05:32:19 PM PDT 24
Finished Jul 14 05:32:26 PM PDT 24
Peak memory 213740 kb
Host smart-cb967f10-43e0-40de-b803-a0986a419b26
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2912899058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2912899058
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1940207890
Short name T224
Test name
Test status
Simulation time 530374055 ps
CPU time 0.83 seconds
Started Jul 14 05:32:19 PM PDT 24
Finished Jul 14 05:32:22 PM PDT 24
Peak memory 204992 kb
Host smart-5da5422a-50d1-47eb-89af-99194abebd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940207890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1940207890
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.111032915
Short name T226
Test name
Test status
Simulation time 3835542599 ps
CPU time 5.93 seconds
Started Jul 14 05:32:17 PM PDT 24
Finished Jul 14 05:32:25 PM PDT 24
Peak memory 213712 kb
Host smart-335b6193-a3d0-41e6-b469-f73b5feabe32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111032915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.111032915
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2396205774
Short name T207
Test name
Test status
Simulation time 66088370 ps
CPU time 0.82 seconds
Started Jul 14 05:32:44 PM PDT 24
Finished Jul 14 05:32:46 PM PDT 24
Peak memory 205096 kb
Host smart-62c3e516-c904-42e4-b184-ceb587b8640f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396205774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2396205774
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1813712783
Short name T202
Test name
Test status
Simulation time 66759718 ps
CPU time 0.73 seconds
Started Jul 14 05:32:45 PM PDT 24
Finished Jul 14 05:32:47 PM PDT 24
Peak memory 205108 kb
Host smart-554ca6e9-be0a-4bde-b567-fa929044226e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813712783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1813712783
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.1859731903
Short name T190
Test name
Test status
Simulation time 4408632134 ps
CPU time 12.1 seconds
Started Jul 14 05:32:43 PM PDT 24
Finished Jul 14 05:32:55 PM PDT 24
Peak memory 213524 kb
Host smart-ef184d01-e346-41c7-9bff-88bdd478edc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859731903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1859731903
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3892596631
Short name T201
Test name
Test status
Simulation time 105648879 ps
CPU time 0.8 seconds
Started Jul 14 05:32:50 PM PDT 24
Finished Jul 14 05:32:53 PM PDT 24
Peak memory 205140 kb
Host smart-623363dd-618d-43c5-a98c-291a2fb0ecbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892596631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3892596631
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.853275288
Short name T3
Test name
Test status
Simulation time 47671276 ps
CPU time 0.78 seconds
Started Jul 14 05:32:50 PM PDT 24
Finished Jul 14 05:32:52 PM PDT 24
Peak memory 205096 kb
Host smart-c0a3d420-b940-4874-a098-6f9a5d9a3023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853275288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.853275288
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.2688665774
Short name T11
Test name
Test status
Simulation time 7381325510 ps
CPU time 6.59 seconds
Started Jul 14 05:32:48 PM PDT 24
Finished Jul 14 05:32:55 PM PDT 24
Peak memory 205240 kb
Host smart-181cd4aa-a3fc-4e94-bfeb-3a9baaad1f31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688665774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2688665774
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.968676000
Short name T211
Test name
Test status
Simulation time 61952361 ps
CPU time 0.77 seconds
Started Jul 14 05:32:50 PM PDT 24
Finished Jul 14 05:32:53 PM PDT 24
Peak memory 205324 kb
Host smart-ae212523-8b01-4afc-ba2f-cc01afe1a3d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968676000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.968676000
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2552489020
Short name T73
Test name
Test status
Simulation time 62421007 ps
CPU time 0.8 seconds
Started Jul 14 05:32:53 PM PDT 24
Finished Jul 14 05:32:55 PM PDT 24
Peak memory 205116 kb
Host smart-dc077327-26e0-48cf-8e3c-8818cb51ea24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552489020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2552489020
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.545026119
Short name T156
Test name
Test status
Simulation time 3374502105 ps
CPU time 3.95 seconds
Started Jul 14 05:32:50 PM PDT 24
Finished Jul 14 05:32:56 PM PDT 24
Peak memory 205204 kb
Host smart-e0df9467-2a00-4fc9-8b77-889c577a5395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545026119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.545026119
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1667827112
Short name T219
Test name
Test status
Simulation time 171507328 ps
CPU time 0.76 seconds
Started Jul 14 05:32:58 PM PDT 24
Finished Jul 14 05:33:00 PM PDT 24
Peak memory 205000 kb
Host smart-d16c6c82-546d-4c91-a542-42e53cecabb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667827112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1667827112
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1268162906
Short name T242
Test name
Test status
Simulation time 82794006 ps
CPU time 0.77 seconds
Started Jul 14 05:32:48 PM PDT 24
Finished Jul 14 05:32:50 PM PDT 24
Peak memory 205100 kb
Host smart-6a512a92-b49b-4bdd-917a-ae9acecee5ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268162906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1268162906
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.2714914613
Short name T191
Test name
Test status
Simulation time 2850520940 ps
CPU time 7.08 seconds
Started Jul 14 05:32:50 PM PDT 24
Finished Jul 14 05:32:59 PM PDT 24
Peak memory 205360 kb
Host smart-e10badf2-51d9-4e5d-9582-2432268e2389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714914613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2714914613
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.29106968
Short name T288
Test name
Test status
Simulation time 64717629 ps
CPU time 0.83 seconds
Started Jul 14 05:32:48 PM PDT 24
Finished Jul 14 05:32:50 PM PDT 24
Peak memory 205052 kb
Host smart-eff1dfc1-fbb8-4a17-a6cc-6ab88e734a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29106968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.29106968
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.430865933
Short name T254
Test name
Test status
Simulation time 221464695 ps
CPU time 0.77 seconds
Started Jul 14 05:32:19 PM PDT 24
Finished Jul 14 05:32:22 PM PDT 24
Peak memory 204976 kb
Host smart-584faa0e-47d2-4512-8061-d3661620504e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430865933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.430865933
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1292392981
Short name T266
Test name
Test status
Simulation time 923791218 ps
CPU time 2.14 seconds
Started Jul 14 05:32:17 PM PDT 24
Finished Jul 14 05:32:22 PM PDT 24
Peak memory 205508 kb
Host smart-391e2fd2-d8b1-4a86-a2cb-ed0a64962fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292392981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1292392981
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1049204700
Short name T39
Test name
Test status
Simulation time 5838495070 ps
CPU time 5.01 seconds
Started Jul 14 05:32:21 PM PDT 24
Finished Jul 14 05:32:27 PM PDT 24
Peak memory 205300 kb
Host smart-5e258cfb-5bd5-49bf-85e4-5ed8efeef345
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049204700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1049204700
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3930475931
Short name T228
Test name
Test status
Simulation time 5500334568 ps
CPU time 14.94 seconds
Started Jul 14 05:32:18 PM PDT 24
Finished Jul 14 05:32:35 PM PDT 24
Peak memory 213684 kb
Host smart-0d9955cf-4e99-4eed-910e-351d79a9cacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930475931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3930475931
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2895235458
Short name T42
Test name
Test status
Simulation time 1009518380 ps
CPU time 2.51 seconds
Started Jul 14 05:32:19 PM PDT 24
Finished Jul 14 05:32:24 PM PDT 24
Peak memory 229116 kb
Host smart-8ef9c094-a7af-4556-824c-9472741c1201
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895235458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2895235458
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.809943363
Short name T157
Test name
Test status
Simulation time 4450462099 ps
CPU time 4.11 seconds
Started Jul 14 05:32:18 PM PDT 24
Finished Jul 14 05:32:24 PM PDT 24
Peak memory 213640 kb
Host smart-489ab003-1709-402a-86dd-1230878dac91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809943363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.809943363
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.86638515
Short name T209
Test name
Test status
Simulation time 39183141 ps
CPU time 0.77 seconds
Started Jul 14 05:32:51 PM PDT 24
Finished Jul 14 05:32:54 PM PDT 24
Peak memory 204932 kb
Host smart-3e303888-9d27-4c2e-9435-f0b9efafc959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86638515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.86638515
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2346375924
Short name T232
Test name
Test status
Simulation time 39600446 ps
CPU time 0.71 seconds
Started Jul 14 05:32:51 PM PDT 24
Finished Jul 14 05:32:53 PM PDT 24
Peak memory 205104 kb
Host smart-f47e4ae9-b2be-4f64-8910-cc095746d609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346375924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2346375924
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.2777036204
Short name T196
Test name
Test status
Simulation time 3817973366 ps
CPU time 5.76 seconds
Started Jul 14 05:32:51 PM PDT 24
Finished Jul 14 05:32:59 PM PDT 24
Peak memory 213592 kb
Host smart-71714317-d76c-4572-9b31-3bbd5bf5437f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777036204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2777036204
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1381313565
Short name T261
Test name
Test status
Simulation time 118503007 ps
CPU time 0.97 seconds
Started Jul 14 05:32:54 PM PDT 24
Finished Jul 14 05:32:56 PM PDT 24
Peak memory 204916 kb
Host smart-6cedbe28-be66-4e01-aafc-2f1942ef769c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381313565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1381313565
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.734167354
Short name T155
Test name
Test status
Simulation time 1513311068 ps
CPU time 2.85 seconds
Started Jul 14 05:32:52 PM PDT 24
Finished Jul 14 05:32:57 PM PDT 24
Peak memory 205328 kb
Host smart-98812b38-36d2-491b-bd38-49a21bd4f807
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734167354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.734167354
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3001673780
Short name T293
Test name
Test status
Simulation time 64936935 ps
CPU time 0.83 seconds
Started Jul 14 05:32:58 PM PDT 24
Finished Jul 14 05:33:01 PM PDT 24
Peak memory 205004 kb
Host smart-e10339b3-c8f6-4152-9106-4e7c970826db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001673780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3001673780
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.2205558345
Short name T21
Test name
Test status
Simulation time 5385466464 ps
CPU time 15.73 seconds
Started Jul 14 05:32:50 PM PDT 24
Finished Jul 14 05:33:08 PM PDT 24
Peak memory 205392 kb
Host smart-cb655e36-b3cd-48b6-babf-8b11558ed03c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205558345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2205558345
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1783461007
Short name T225
Test name
Test status
Simulation time 86892550 ps
CPU time 0.75 seconds
Started Jul 14 05:32:49 PM PDT 24
Finished Jul 14 05:32:52 PM PDT 24
Peak memory 205008 kb
Host smart-cc596759-e005-4be3-91bf-ca6d3fb42bfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783461007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1783461007
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2838548842
Short name T150
Test name
Test status
Simulation time 10851253987 ps
CPU time 14.25 seconds
Started Jul 14 05:32:58 PM PDT 24
Finished Jul 14 05:33:15 PM PDT 24
Peak memory 214192 kb
Host smart-fb915b8f-f438-413c-9f39-c60b9ea81f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838548842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2838548842
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.4144526981
Short name T204
Test name
Test status
Simulation time 188222848 ps
CPU time 0.74 seconds
Started Jul 14 05:32:52 PM PDT 24
Finished Jul 14 05:32:54 PM PDT 24
Peak memory 204912 kb
Host smart-6aa15a7c-8615-42ef-b933-abf6e03246be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144526981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.4144526981
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.3457971171
Short name T151
Test name
Test status
Simulation time 3994216897 ps
CPU time 6.37 seconds
Started Jul 14 05:32:59 PM PDT 24
Finished Jul 14 05:33:07 PM PDT 24
Peak memory 213444 kb
Host smart-8d823a47-cb5e-42cc-800f-c2581385dcad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457971171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3457971171
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.363223517
Short name T285
Test name
Test status
Simulation time 52662003 ps
CPU time 0.75 seconds
Started Jul 14 05:32:52 PM PDT 24
Finished Jul 14 05:32:54 PM PDT 24
Peak memory 204912 kb
Host smart-9e0a26d0-5a2f-44f3-b32d-cda169fbec65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363223517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.363223517
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2395044663
Short name T292
Test name
Test status
Simulation time 205494760 ps
CPU time 0.79 seconds
Started Jul 14 05:32:50 PM PDT 24
Finished Jul 14 05:32:52 PM PDT 24
Peak memory 205324 kb
Host smart-cd8850f7-8c03-46bf-88ce-e0c2256a81f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395044663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2395044663
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.374795318
Short name T235
Test name
Test status
Simulation time 85679688 ps
CPU time 0.73 seconds
Started Jul 14 05:32:50 PM PDT 24
Finished Jul 14 05:32:52 PM PDT 24
Peak memory 205024 kb
Host smart-e39f7611-081a-4045-9406-61e12bbd5469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374795318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.374795318
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.657147510
Short name T260
Test name
Test status
Simulation time 167132602 ps
CPU time 0.78 seconds
Started Jul 14 05:32:50 PM PDT 24
Finished Jul 14 05:32:52 PM PDT 24
Peak memory 205112 kb
Host smart-7415ebc4-43a6-448f-9207-4783c2731152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657147510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.657147510
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.2399156301
Short name T90
Test name
Test status
Simulation time 4562421524 ps
CPU time 14.33 seconds
Started Jul 14 05:32:49 PM PDT 24
Finished Jul 14 05:33:04 PM PDT 24
Peak memory 213552 kb
Host smart-3ba0aa10-5cf0-4d5e-99fd-ae8b4487e6bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399156301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.2399156301
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2118492431
Short name T205
Test name
Test status
Simulation time 54434328 ps
CPU time 0.74 seconds
Started Jul 14 05:32:18 PM PDT 24
Finished Jul 14 05:32:21 PM PDT 24
Peak memory 205112 kb
Host smart-888edb20-5379-41b6-9e50-44153adbbdc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118492431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2118492431
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2435815535
Short name T139
Test name
Test status
Simulation time 20496077806 ps
CPU time 10.18 seconds
Started Jul 14 05:32:18 PM PDT 24
Finished Jul 14 05:32:30 PM PDT 24
Peak memory 205556 kb
Host smart-28fd81ca-aa5a-4637-a183-0a5c91e30ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435815535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2435815535
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.4249999379
Short name T133
Test name
Test status
Simulation time 9065433438 ps
CPU time 12.82 seconds
Started Jul 14 05:32:19 PM PDT 24
Finished Jul 14 05:32:34 PM PDT 24
Peak memory 213764 kb
Host smart-589c172f-c5a2-4392-8086-398066b36e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249999379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.4249999379
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3770667782
Short name T287
Test name
Test status
Simulation time 4727780736 ps
CPU time 7.4 seconds
Started Jul 14 05:32:20 PM PDT 24
Finished Jul 14 05:32:29 PM PDT 24
Peak memory 213680 kb
Host smart-0ee561aa-1c2e-4e7f-b477-784d050a213b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770667782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3770667782
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3940878145
Short name T161
Test name
Test status
Simulation time 199906414 ps
CPU time 0.79 seconds
Started Jul 14 05:32:17 PM PDT 24
Finished Jul 14 05:32:21 PM PDT 24
Peak memory 205080 kb
Host smart-b904f12a-a5b6-400b-a656-e1ee7e4bffc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940878145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3940878145
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1204987946
Short name T72
Test name
Test status
Simulation time 752322793 ps
CPU time 1.54 seconds
Started Jul 14 05:32:27 PM PDT 24
Finished Jul 14 05:32:29 PM PDT 24
Peak memory 228732 kb
Host smart-b9f4d989-a7c5-49d2-b68b-0af94cc19fa9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204987946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1204987946
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3208141757
Short name T236
Test name
Test status
Simulation time 104584157 ps
CPU time 0.73 seconds
Started Jul 14 05:32:51 PM PDT 24
Finished Jul 14 05:32:53 PM PDT 24
Peak memory 205124 kb
Host smart-ff611361-f013-4ce0-af6a-30fa41573d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208141757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3208141757
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.3247668457
Short name T280
Test name
Test status
Simulation time 4459725117 ps
CPU time 4.33 seconds
Started Jul 14 05:32:51 PM PDT 24
Finished Jul 14 05:32:57 PM PDT 24
Peak memory 205336 kb
Host smart-50cc013e-7b96-4ede-8955-86dddb45ac9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247668457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3247668457
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.4037099758
Short name T252
Test name
Test status
Simulation time 150826371 ps
CPU time 0.71 seconds
Started Jul 14 05:32:53 PM PDT 24
Finished Jul 14 05:32:55 PM PDT 24
Peak memory 205116 kb
Host smart-ff59fe28-3a09-47b0-9e3a-ed4abb46bd1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037099758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.4037099758
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.2606452992
Short name T195
Test name
Test status
Simulation time 6737787654 ps
CPU time 6.54 seconds
Started Jul 14 05:32:52 PM PDT 24
Finished Jul 14 05:33:00 PM PDT 24
Peak memory 214444 kb
Host smart-2d04907d-27e9-4abb-8aa5-25e43c143954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606452992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.2606452992
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.2438951030
Short name T231
Test name
Test status
Simulation time 78492275 ps
CPU time 0.71 seconds
Started Jul 14 05:32:51 PM PDT 24
Finished Jul 14 05:32:54 PM PDT 24
Peak memory 205124 kb
Host smart-71468195-3a1d-4d46-8e88-a0af5f2104fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438951030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2438951030
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.290341399
Short name T215
Test name
Test status
Simulation time 164292289 ps
CPU time 0.93 seconds
Started Jul 14 05:32:56 PM PDT 24
Finished Jul 14 05:32:58 PM PDT 24
Peak memory 205100 kb
Host smart-51952c5b-1afb-4cc5-b350-cf97b7b600f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290341399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.290341399
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.719603983
Short name T152
Test name
Test status
Simulation time 3658678630 ps
CPU time 8.15 seconds
Started Jul 14 05:32:57 PM PDT 24
Finished Jul 14 05:33:07 PM PDT 24
Peak memory 205436 kb
Host smart-acf5925e-8e5c-4e6e-b6c5-99a4ec9bc8bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719603983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.719603983
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.4285520833
Short name T243
Test name
Test status
Simulation time 75771217 ps
CPU time 0.75 seconds
Started Jul 14 05:32:54 PM PDT 24
Finished Jul 14 05:32:56 PM PDT 24
Peak memory 205132 kb
Host smart-b3dbcabc-3ac5-4e42-8877-1d6331dc68c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285520833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.4285520833
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.184765580
Short name T23
Test name
Test status
Simulation time 1141127802 ps
CPU time 2.3 seconds
Started Jul 14 05:33:01 PM PDT 24
Finished Jul 14 05:33:06 PM PDT 24
Peak memory 205268 kb
Host smart-c7fc8278-8b0e-4ca8-8bd7-bcf5817e4400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184765580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.184765580
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.314682868
Short name T218
Test name
Test status
Simulation time 61183621 ps
CPU time 0.83 seconds
Started Jul 14 05:32:57 PM PDT 24
Finished Jul 14 05:33:00 PM PDT 24
Peak memory 205032 kb
Host smart-da78f8bc-dba8-4c2a-9289-a29e17fbc2fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314682868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.314682868
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.17241950
Short name T160
Test name
Test status
Simulation time 6821188344 ps
CPU time 16.57 seconds
Started Jul 14 05:33:00 PM PDT 24
Finished Jul 14 05:33:19 PM PDT 24
Peak memory 213576 kb
Host smart-af2ca239-d6ff-4396-afac-f25df4de28d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17241950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.17241950
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2481029790
Short name T234
Test name
Test status
Simulation time 176136062 ps
CPU time 0.7 seconds
Started Jul 14 05:32:59 PM PDT 24
Finished Jul 14 05:33:02 PM PDT 24
Peak memory 205128 kb
Host smart-39573329-1e46-45ed-949d-08b83f577ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481029790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2481029790
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.573680092
Short name T29
Test name
Test status
Simulation time 3398168736 ps
CPU time 9.86 seconds
Started Jul 14 05:32:57 PM PDT 24
Finished Jul 14 05:33:07 PM PDT 24
Peak memory 205436 kb
Host smart-b265aa2b-a02c-4137-a4d1-a65ce0ae74c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573680092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.573680092
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1418895454
Short name T244
Test name
Test status
Simulation time 152032702 ps
CPU time 0.78 seconds
Started Jul 14 05:32:56 PM PDT 24
Finished Jul 14 05:32:57 PM PDT 24
Peak memory 205124 kb
Host smart-a1f79bed-30f1-4304-8db7-197db185214d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418895454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1418895454
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.2398870752
Short name T166
Test name
Test status
Simulation time 3886305268 ps
CPU time 5.82 seconds
Started Jul 14 05:32:55 PM PDT 24
Finished Jul 14 05:33:02 PM PDT 24
Peak memory 205392 kb
Host smart-2da6d8fc-d9fe-4049-8f03-19dabed39b54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398870752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2398870752
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3751597346
Short name T273
Test name
Test status
Simulation time 60558699 ps
CPU time 0.84 seconds
Started Jul 14 05:32:55 PM PDT 24
Finished Jul 14 05:32:57 PM PDT 24
Peak memory 205000 kb
Host smart-5e54db81-1381-4639-ad65-af55cecdaf4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751597346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3751597346
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.969986605
Short name T229
Test name
Test status
Simulation time 132050091 ps
CPU time 0.84 seconds
Started Jul 14 05:33:00 PM PDT 24
Finished Jul 14 05:33:02 PM PDT 24
Peak memory 205132 kb
Host smart-2324df2b-f0dc-4cb1-b736-04f519a1e97a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969986605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.969986605
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.3642580059
Short name T5
Test name
Test status
Simulation time 8782915735 ps
CPU time 13.73 seconds
Started Jul 14 05:32:56 PM PDT 24
Finished Jul 14 05:33:10 PM PDT 24
Peak memory 213472 kb
Host smart-74ba95ed-ee61-405d-afa7-dbac4a1526ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642580059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3642580059
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3321405554
Short name T241
Test name
Test status
Simulation time 146661675 ps
CPU time 0.75 seconds
Started Jul 14 05:32:23 PM PDT 24
Finished Jul 14 05:32:25 PM PDT 24
Peak memory 205112 kb
Host smart-3aabc026-c3cb-4074-b33b-d43b836d9fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321405554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3321405554
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3950544430
Short name T276
Test name
Test status
Simulation time 8857443499 ps
CPU time 14.96 seconds
Started Jul 14 05:32:21 PM PDT 24
Finished Jul 14 05:32:37 PM PDT 24
Peak memory 213724 kb
Host smart-6b1be809-748e-43d6-ad17-61625b3c2a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950544430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3950544430
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3510826248
Short name T24
Test name
Test status
Simulation time 6330132063 ps
CPU time 17.09 seconds
Started Jul 14 05:32:27 PM PDT 24
Finished Jul 14 05:32:45 PM PDT 24
Peak memory 213580 kb
Host smart-41bc2a2b-2370-4463-be06-ae4fd45e707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510826248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3510826248
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3255059049
Short name T278
Test name
Test status
Simulation time 4576439194 ps
CPU time 13.55 seconds
Started Jul 14 05:32:19 PM PDT 24
Finished Jul 14 05:32:34 PM PDT 24
Peak memory 213720 kb
Host smart-7486dfdc-2608-42bc-931c-ffe961e77a40
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3255059049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3255059049
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2350204017
Short name T221
Test name
Test status
Simulation time 14653524108 ps
CPU time 17.48 seconds
Started Jul 14 05:32:16 PM PDT 24
Finished Jul 14 05:32:35 PM PDT 24
Peak memory 213652 kb
Host smart-36f0fabb-2147-4fa2-ba12-ddd021e535f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350204017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2350204017
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.1417870924
Short name T169
Test name
Test status
Simulation time 5000694522 ps
CPU time 4.8 seconds
Started Jul 14 05:32:23 PM PDT 24
Finished Jul 14 05:32:29 PM PDT 24
Peak memory 214616 kb
Host smart-af97ad92-862e-4606-b5a2-d7358f985739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417870924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1417870924
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.485609078
Short name T214
Test name
Test status
Simulation time 78320486 ps
CPU time 0.83 seconds
Started Jul 14 05:32:22 PM PDT 24
Finished Jul 14 05:32:23 PM PDT 24
Peak memory 205096 kb
Host smart-4ccb341a-02f9-4e95-8e3d-ac7bf30ecc5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485609078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.485609078
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3453193737
Short name T223
Test name
Test status
Simulation time 17486496155 ps
CPU time 54.51 seconds
Started Jul 14 05:32:22 PM PDT 24
Finished Jul 14 05:33:17 PM PDT 24
Peak memory 217812 kb
Host smart-e3075890-ab65-4794-b44c-b0650133d13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453193737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3453193737
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1601991907
Short name T283
Test name
Test status
Simulation time 4013485258 ps
CPU time 2.78 seconds
Started Jul 14 05:32:22 PM PDT 24
Finished Jul 14 05:32:26 PM PDT 24
Peak memory 213712 kb
Host smart-444478d5-1030-42bd-a1b6-afc8d9a3fc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601991907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1601991907
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3229872640
Short name T146
Test name
Test status
Simulation time 999254220 ps
CPU time 3.69 seconds
Started Jul 14 05:32:24 PM PDT 24
Finished Jul 14 05:32:29 PM PDT 24
Peak memory 213496 kb
Host smart-1e662d29-5dbd-4a55-947d-0306ef5f4c83
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229872640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3229872640
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.256104029
Short name T290
Test name
Test status
Simulation time 1890801338 ps
CPU time 5.47 seconds
Started Jul 14 05:32:25 PM PDT 24
Finished Jul 14 05:32:31 PM PDT 24
Peak memory 205328 kb
Host smart-e03dade7-ebea-49ed-969f-826c8fd91fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256104029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.256104029
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.38629967
Short name T41
Test name
Test status
Simulation time 66310350 ps
CPU time 0.73 seconds
Started Jul 14 05:32:24 PM PDT 24
Finished Jul 14 05:32:26 PM PDT 24
Peak memory 205132 kb
Host smart-d304e899-d2aa-44a2-92d5-556c0eb2bcba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38629967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.38629967
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.4174559091
Short name T134
Test name
Test status
Simulation time 5189493798 ps
CPU time 4.87 seconds
Started Jul 14 05:32:26 PM PDT 24
Finished Jul 14 05:32:32 PM PDT 24
Peak memory 214836 kb
Host smart-57cb52bf-8353-4e29-b414-3ad387066a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174559091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.4174559091
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3032421918
Short name T148
Test name
Test status
Simulation time 11739432332 ps
CPU time 17.21 seconds
Started Jul 14 05:32:24 PM PDT 24
Finished Jul 14 05:32:42 PM PDT 24
Peak memory 215060 kb
Host smart-befc53d6-bbb3-46bc-a215-bd950c337c9d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3032421918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3032421918
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.2884755097
Short name T167
Test name
Test status
Simulation time 6902226997 ps
CPU time 20.66 seconds
Started Jul 14 05:32:25 PM PDT 24
Finished Jul 14 05:32:46 PM PDT 24
Peak memory 213400 kb
Host smart-42252f89-4ed6-43f9-a8ed-aed56e29d830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884755097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2884755097
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1437373767
Short name T217
Test name
Test status
Simulation time 38090732 ps
CPU time 0.74 seconds
Started Jul 14 05:32:29 PM PDT 24
Finished Jul 14 05:32:30 PM PDT 24
Peak memory 205136 kb
Host smart-d70915fc-49fd-4278-ab53-d3a971c6b84a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437373767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1437373767
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.268966741
Short name T240
Test name
Test status
Simulation time 1169364217 ps
CPU time 1.69 seconds
Started Jul 14 05:32:31 PM PDT 24
Finished Jul 14 05:32:34 PM PDT 24
Peak memory 213580 kb
Host smart-57a70efc-8a91-413b-9531-1a58bbcd7879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268966741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.268966741
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3218718540
Short name T246
Test name
Test status
Simulation time 7572159942 ps
CPU time 4.97 seconds
Started Jul 14 05:32:28 PM PDT 24
Finished Jul 14 05:32:34 PM PDT 24
Peak memory 213752 kb
Host smart-a63355c0-36e1-4a0b-a3d5-2a2397a01bbc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218718540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3218718540
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.190897408
Short name T208
Test name
Test status
Simulation time 1109830861 ps
CPU time 2.8 seconds
Started Jul 14 05:32:23 PM PDT 24
Finished Jul 14 05:32:27 PM PDT 24
Peak memory 205300 kb
Host smart-1573ef54-7b97-4636-8a71-e6ddf1c4bf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190897408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.190897408
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.3445930746
Short name T192
Test name
Test status
Simulation time 3062326731 ps
CPU time 9.92 seconds
Started Jul 14 05:32:26 PM PDT 24
Finished Jul 14 05:32:37 PM PDT 24
Peak memory 205396 kb
Host smart-43f57c8e-c2b1-4127-8f22-2b4b99d5c255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445930746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3445930746
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3887453615
Short name T54
Test name
Test status
Simulation time 36315960 ps
CPU time 0.68 seconds
Started Jul 14 05:32:26 PM PDT 24
Finished Jul 14 05:32:27 PM PDT 24
Peak memory 205120 kb
Host smart-7b637101-b144-44c9-bd3a-0f2ea8b19154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887453615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3887453615
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.875706303
Short name T147
Test name
Test status
Simulation time 5054645858 ps
CPU time 8.24 seconds
Started Jul 14 05:32:28 PM PDT 24
Finished Jul 14 05:32:37 PM PDT 24
Peak memory 213708 kb
Host smart-6626a3eb-3fb9-40f1-be0c-e9ee7a6e340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875706303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.875706303
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3300288748
Short name T281
Test name
Test status
Simulation time 2110286488 ps
CPU time 4.22 seconds
Started Jul 14 05:32:30 PM PDT 24
Finished Jul 14 05:32:35 PM PDT 24
Peak memory 213672 kb
Host smart-db3d0aec-d675-4f90-861f-91bb608fd7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300288748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3300288748
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.290683812
Short name T249
Test name
Test status
Simulation time 920966050 ps
CPU time 3.6 seconds
Started Jul 14 05:32:29 PM PDT 24
Finished Jul 14 05:32:33 PM PDT 24
Peak memory 205344 kb
Host smart-d22d7ff2-839d-4865-b674-de164e19daac
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=290683812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.290683812
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3389997601
Short name T291
Test name
Test status
Simulation time 653511803 ps
CPU time 1.75 seconds
Started Jul 14 05:32:26 PM PDT 24
Finished Jul 14 05:32:28 PM PDT 24
Peak memory 205376 kb
Host smart-e40160b8-8d37-4ab9-9446-97be43b269ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389997601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3389997601
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.1942482066
Short name T245
Test name
Test status
Simulation time 4239949163 ps
CPU time 8.86 seconds
Started Jul 14 05:32:26 PM PDT 24
Finished Jul 14 05:32:36 PM PDT 24
Peak memory 213568 kb
Host smart-f02ebd35-8b0b-481a-80f9-a4e810944069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942482066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1942482066
Directory /workspace/9.rv_dm_stress_all/latest
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