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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.58 95.42 80.97 89.91 75.00 85.83 98.00 52.94


Total test records in report: 440
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T78 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1533844528 Jul 15 06:15:07 PM PDT 24 Jul 15 06:15:39 PM PDT 24 33818414160 ps
T98 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3839385309 Jul 15 06:14:52 PM PDT 24 Jul 15 06:15:04 PM PDT 24 1538561494 ps
T97 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.935557251 Jul 15 06:15:20 PM PDT 24 Jul 15 06:15:39 PM PDT 24 2233292879 ps
T99 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4259990351 Jul 15 06:15:24 PM PDT 24 Jul 15 06:15:28 PM PDT 24 845607321 ps
T96 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.93425505 Jul 15 06:14:58 PM PDT 24 Jul 15 06:15:02 PM PDT 24 157412129 ps
T118 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2905331014 Jul 15 06:14:49 PM PDT 24 Jul 15 06:14:54 PM PDT 24 304527025 ps
T292 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2102946573 Jul 15 06:15:24 PM PDT 24 Jul 15 06:15:41 PM PDT 24 5680270550 ps
T126 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3608857653 Jul 15 06:14:52 PM PDT 24 Jul 15 06:14:56 PM PDT 24 1152622023 ps
T81 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.61643876 Jul 15 06:14:56 PM PDT 24 Jul 15 06:14:59 PM PDT 24 267933439 ps
T293 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3206684597 Jul 15 06:15:06 PM PDT 24 Jul 15 06:15:16 PM PDT 24 2893390775 ps
T101 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2052965868 Jul 15 06:14:56 PM PDT 24 Jul 15 06:15:01 PM PDT 24 2683740590 ps
T82 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1992405401 Jul 15 06:15:13 PM PDT 24 Jul 15 06:15:14 PM PDT 24 156489903 ps
T294 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4258196361 Jul 15 06:14:55 PM PDT 24 Jul 15 06:14:57 PM PDT 24 67463674 ps
T119 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.4054817905 Jul 15 06:15:15 PM PDT 24 Jul 15 06:15:23 PM PDT 24 254999748 ps
T295 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.99469496 Jul 15 06:14:58 PM PDT 24 Jul 15 06:15:00 PM PDT 24 470017184 ps
T296 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3176087093 Jul 15 06:15:15 PM PDT 24 Jul 15 06:15:23 PM PDT 24 14410679514 ps
T239 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3984366179 Jul 15 06:15:08 PM PDT 24 Jul 15 06:15:15 PM PDT 24 755075446 ps
T297 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1258665387 Jul 15 06:14:52 PM PDT 24 Jul 15 06:15:19 PM PDT 24 40571973901 ps
T176 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4274580942 Jul 15 06:14:53 PM PDT 24 Jul 15 06:15:12 PM PDT 24 1392213681 ps
T120 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2068051086 Jul 15 06:15:17 PM PDT 24 Jul 15 06:15:24 PM PDT 24 158745412 ps
T298 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3709448853 Jul 15 06:15:20 PM PDT 24 Jul 15 06:15:26 PM PDT 24 1254362495 ps
T299 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1890821899 Jul 15 06:14:53 PM PDT 24 Jul 15 06:14:58 PM PDT 24 2070703662 ps
T300 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1079664320 Jul 15 06:14:53 PM PDT 24 Jul 15 06:15:00 PM PDT 24 4615627576 ps
T301 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1579322398 Jul 15 06:15:21 PM PDT 24 Jul 15 06:15:28 PM PDT 24 7545009737 ps
T127 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2895532648 Jul 15 06:15:13 PM PDT 24 Jul 15 06:15:16 PM PDT 24 360347866 ps
T105 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3278946594 Jul 15 06:14:55 PM PDT 24 Jul 15 06:16:09 PM PDT 24 3500995101 ps
T302 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3919882087 Jul 15 06:14:59 PM PDT 24 Jul 15 06:15:02 PM PDT 24 1202335376 ps
T106 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.284528747 Jul 15 06:14:52 PM PDT 24 Jul 15 06:15:00 PM PDT 24 224563213 ps
T303 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1924422043 Jul 15 06:15:07 PM PDT 24 Jul 15 06:15:12 PM PDT 24 5244608297 ps
T304 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3265756499 Jul 15 06:15:12 PM PDT 24 Jul 15 06:15:16 PM PDT 24 274395577 ps
T107 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.148483849 Jul 15 06:15:06 PM PDT 24 Jul 15 06:15:14 PM PDT 24 543426395 ps
T108 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1971782555 Jul 15 06:15:16 PM PDT 24 Jul 15 06:15:19 PM PDT 24 122883937 ps
T305 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2538931070 Jul 15 06:14:54 PM PDT 24 Jul 15 06:15:10 PM PDT 24 4508919948 ps
T123 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2210429376 Jul 15 06:15:05 PM PDT 24 Jul 15 06:15:08 PM PDT 24 163959626 ps
T306 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3217017445 Jul 15 06:15:03 PM PDT 24 Jul 15 06:15:22 PM PDT 24 7021636404 ps
T307 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1575365870 Jul 15 06:15:05 PM PDT 24 Jul 15 06:15:16 PM PDT 24 4580762093 ps
T308 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2091296186 Jul 15 06:14:53 PM PDT 24 Jul 15 06:14:56 PM PDT 24 443872853 ps
T309 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2035930681 Jul 15 06:14:51 PM PDT 24 Jul 15 06:14:54 PM PDT 24 193509618 ps
T310 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1268071220 Jul 15 06:15:08 PM PDT 24 Jul 15 06:15:10 PM PDT 24 186893742 ps
T175 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1122403320 Jul 15 06:15:22 PM PDT 24 Jul 15 06:15:27 PM PDT 24 89467639 ps
T128 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.64781895 Jul 15 06:15:12 PM PDT 24 Jul 15 06:15:18 PM PDT 24 1855223360 ps
T114 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4113482833 Jul 15 06:15:14 PM PDT 24 Jul 15 06:15:18 PM PDT 24 213241808 ps
T121 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2982231037 Jul 15 06:15:16 PM PDT 24 Jul 15 06:15:23 PM PDT 24 603893133 ps
T311 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2474433541 Jul 15 06:14:59 PM PDT 24 Jul 15 06:15:15 PM PDT 24 7743603397 ps
T312 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.890283162 Jul 15 06:15:19 PM PDT 24 Jul 15 06:15:24 PM PDT 24 2367410098 ps
T313 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2828029273 Jul 15 06:15:20 PM PDT 24 Jul 15 06:15:26 PM PDT 24 284598701 ps
T314 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1201430779 Jul 15 06:15:22 PM PDT 24 Jul 15 06:15:24 PM PDT 24 348339931 ps
T102 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2712958995 Jul 15 06:14:56 PM PDT 24 Jul 15 06:15:09 PM PDT 24 3473896125 ps
T79 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3744846933 Jul 15 06:15:07 PM PDT 24 Jul 15 06:15:44 PM PDT 24 41257414806 ps
T315 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.740232231 Jul 15 06:14:59 PM PDT 24 Jul 15 06:15:09 PM PDT 24 5491118408 ps
T316 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3956957042 Jul 15 06:15:02 PM PDT 24 Jul 15 06:15:07 PM PDT 24 4395319615 ps
T109 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1388983440 Jul 15 06:14:55 PM PDT 24 Jul 15 06:14:58 PM PDT 24 103715165 ps
T122 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3762386 Jul 15 06:15:12 PM PDT 24 Jul 15 06:15:17 PM PDT 24 233337970 ps
T110 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2447943896 Jul 15 06:14:53 PM PDT 24 Jul 15 06:14:57 PM PDT 24 309514673 ps
T317 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3499791144 Jul 15 06:15:21 PM PDT 24 Jul 15 06:15:24 PM PDT 24 644869652 ps
T318 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1823566411 Jul 15 06:15:19 PM PDT 24 Jul 15 06:15:20 PM PDT 24 266232324 ps
T319 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3460162351 Jul 15 06:15:07 PM PDT 24 Jul 15 06:15:36 PM PDT 24 9642731622 ps
T320 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2987225966 Jul 15 06:14:52 PM PDT 24 Jul 15 06:15:36 PM PDT 24 51352658399 ps
T321 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3041292277 Jul 15 06:14:54 PM PDT 24 Jul 15 06:15:19 PM PDT 24 14631917910 ps
T322 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2151208533 Jul 15 06:14:54 PM PDT 24 Jul 15 06:14:57 PM PDT 24 225574726 ps
T323 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1262253553 Jul 15 06:15:07 PM PDT 24 Jul 15 06:15:09 PM PDT 24 78010677 ps
T324 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2495446168 Jul 15 06:15:14 PM PDT 24 Jul 15 06:15:15 PM PDT 24 620126379 ps
T325 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.429242335 Jul 15 06:14:53 PM PDT 24 Jul 15 06:14:58 PM PDT 24 1604402337 ps
T326 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.994311374 Jul 15 06:14:59 PM PDT 24 Jul 15 06:15:34 PM PDT 24 9424941571 ps
T327 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3626518925 Jul 15 06:14:52 PM PDT 24 Jul 15 06:14:55 PM PDT 24 395792246 ps
T115 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2909409022 Jul 15 06:14:53 PM PDT 24 Jul 15 06:15:34 PM PDT 24 63481892561 ps
T116 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2693754118 Jul 15 06:15:26 PM PDT 24 Jul 15 06:15:29 PM PDT 24 232912903 ps
T328 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.790849325 Jul 15 06:14:58 PM PDT 24 Jul 15 06:15:00 PM PDT 24 176994377 ps
T329 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.653042695 Jul 15 06:15:12 PM PDT 24 Jul 15 06:16:31 PM PDT 24 28767951184 ps
T330 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.161046034 Jul 15 06:15:26 PM PDT 24 Jul 15 06:15:32 PM PDT 24 5881085192 ps
T177 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2488139394 Jul 15 06:15:17 PM PDT 24 Jul 15 06:15:49 PM PDT 24 5763434982 ps
T331 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3961730894 Jul 15 06:14:59 PM PDT 24 Jul 15 06:15:09 PM PDT 24 3423770942 ps
T332 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3988383695 Jul 15 06:15:00 PM PDT 24 Jul 15 06:15:32 PM PDT 24 37209531626 ps
T111 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1322834149 Jul 15 06:14:57 PM PDT 24 Jul 15 06:15:06 PM PDT 24 879737889 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1277840899 Jul 15 06:14:59 PM PDT 24 Jul 15 06:15:34 PM PDT 24 32332578662 ps
T334 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1619579505 Jul 15 06:15:06 PM PDT 24 Jul 15 06:15:09 PM PDT 24 999358153 ps
T335 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.986963853 Jul 15 06:15:24 PM PDT 24 Jul 15 06:15:44 PM PDT 24 7085381132 ps
T336 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3764306106 Jul 15 06:14:49 PM PDT 24 Jul 15 06:15:17 PM PDT 24 4516683882 ps
T337 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.526215714 Jul 15 06:15:00 PM PDT 24 Jul 15 06:15:03 PM PDT 24 275905997 ps
T338 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3946029862 Jul 15 06:14:58 PM PDT 24 Jul 15 06:15:04 PM PDT 24 4552075265 ps
T339 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.209670887 Jul 15 06:14:53 PM PDT 24 Jul 15 06:14:59 PM PDT 24 2479771380 ps
T340 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1615954618 Jul 15 06:14:58 PM PDT 24 Jul 15 06:15:00 PM PDT 24 162271501 ps
T178 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3219292574 Jul 15 06:15:15 PM PDT 24 Jul 15 06:15:27 PM PDT 24 3007313917 ps
T341 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2852390088 Jul 15 06:15:06 PM PDT 24 Jul 15 06:15:11 PM PDT 24 1134380920 ps
T342 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4066337615 Jul 15 06:14:56 PM PDT 24 Jul 15 06:15:01 PM PDT 24 1107923873 ps
T343 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1716128956 Jul 15 06:15:00 PM PDT 24 Jul 15 06:15:05 PM PDT 24 2544908062 ps
T344 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1886019731 Jul 15 06:14:50 PM PDT 24 Jul 15 06:14:54 PM PDT 24 221645944 ps
T180 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.921277429 Jul 15 06:15:20 PM PDT 24 Jul 15 06:15:44 PM PDT 24 3217149012 ps
T345 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.367120417 Jul 15 06:14:59 PM PDT 24 Jul 15 06:15:16 PM PDT 24 5893390078 ps
T346 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1297996271 Jul 15 06:15:11 PM PDT 24 Jul 15 06:15:19 PM PDT 24 360748553 ps
T347 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1972209033 Jul 15 06:15:24 PM PDT 24 Jul 15 06:15:27 PM PDT 24 412980276 ps
T348 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2346591962 Jul 15 06:15:05 PM PDT 24 Jul 15 06:15:06 PM PDT 24 298607046 ps
T349 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3846494987 Jul 15 06:14:50 PM PDT 24 Jul 15 06:18:51 PM PDT 24 99506400240 ps
T350 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.689549388 Jul 15 06:14:55 PM PDT 24 Jul 15 06:14:57 PM PDT 24 37564670 ps
T351 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2740081401 Jul 15 06:15:21 PM PDT 24 Jul 15 06:15:25 PM PDT 24 545832561 ps
T352 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1778458355 Jul 15 06:15:13 PM PDT 24 Jul 15 06:15:18 PM PDT 24 1067516110 ps
T353 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1330581956 Jul 15 06:14:52 PM PDT 24 Jul 15 06:14:55 PM PDT 24 692055310 ps
T354 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1084192164 Jul 15 06:14:51 PM PDT 24 Jul 15 06:15:17 PM PDT 24 18045470834 ps
T355 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4152000077 Jul 15 06:15:07 PM PDT 24 Jul 15 06:15:47 PM PDT 24 44999122666 ps
T356 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3989100633 Jul 15 06:15:14 PM PDT 24 Jul 15 06:15:17 PM PDT 24 87343467 ps
T357 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3654827303 Jul 15 06:14:58 PM PDT 24 Jul 15 06:15:00 PM PDT 24 629468513 ps
T358 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4120190573 Jul 15 06:15:16 PM PDT 24 Jul 15 06:15:22 PM PDT 24 5333479963 ps
T181 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2541640411 Jul 15 06:15:22 PM PDT 24 Jul 15 06:15:39 PM PDT 24 5821388555 ps
T103 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.742253859 Jul 15 06:14:55 PM PDT 24 Jul 15 06:15:13 PM PDT 24 8752808657 ps
T359 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.396923717 Jul 15 06:14:57 PM PDT 24 Jul 15 06:14:59 PM PDT 24 51642521 ps
T112 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1481126828 Jul 15 06:15:14 PM PDT 24 Jul 15 06:15:17 PM PDT 24 184928072 ps
T360 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.793276751 Jul 15 06:15:11 PM PDT 24 Jul 15 06:15:17 PM PDT 24 761271794 ps
T361 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.323410799 Jul 15 06:15:07 PM PDT 24 Jul 15 06:15:12 PM PDT 24 2510192020 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.499100022 Jul 15 06:14:59 PM PDT 24 Jul 15 06:15:01 PM PDT 24 243176842 ps
T363 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3050401734 Jul 15 06:14:57 PM PDT 24 Jul 15 06:15:02 PM PDT 24 216066318 ps
T364 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2370050105 Jul 15 06:14:54 PM PDT 24 Jul 15 06:14:57 PM PDT 24 133612637 ps
T117 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3502604033 Jul 15 06:15:07 PM PDT 24 Jul 15 06:15:10 PM PDT 24 187390748 ps
T365 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.552519407 Jul 15 06:14:51 PM PDT 24 Jul 15 06:14:52 PM PDT 24 305203382 ps
T179 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2438970371 Jul 15 06:14:57 PM PDT 24 Jul 15 06:15:18 PM PDT 24 2603407535 ps
T366 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3045239565 Jul 15 06:14:58 PM PDT 24 Jul 15 06:15:08 PM PDT 24 14851932503 ps
T367 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1194035116 Jul 15 06:15:21 PM PDT 24 Jul 15 06:15:33 PM PDT 24 3453273558 ps
T368 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3268909683 Jul 15 06:14:52 PM PDT 24 Jul 15 06:14:54 PM PDT 24 44573919 ps
T113 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.608983657 Jul 15 06:14:53 PM PDT 24 Jul 15 06:15:01 PM PDT 24 176841851 ps
T369 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.332566974 Jul 15 06:15:13 PM PDT 24 Jul 15 06:15:16 PM PDT 24 103714167 ps
T370 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3028082810 Jul 15 06:14:59 PM PDT 24 Jul 15 06:15:07 PM PDT 24 5678376151 ps
T371 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4091154795 Jul 15 06:14:53 PM PDT 24 Jul 15 06:14:56 PM PDT 24 472225975 ps
T372 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3515586083 Jul 15 06:15:14 PM PDT 24 Jul 15 06:15:25 PM PDT 24 1027286566 ps
T373 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4222739770 Jul 15 06:14:55 PM PDT 24 Jul 15 06:15:06 PM PDT 24 5135763682 ps
T374 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2836664215 Jul 15 06:15:15 PM PDT 24 Jul 15 06:15:20 PM PDT 24 311653878 ps
T375 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3735931083 Jul 15 06:15:14 PM PDT 24 Jul 15 06:15:27 PM PDT 24 4694278931 ps
T376 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2471560744 Jul 15 06:15:25 PM PDT 24 Jul 15 06:15:29 PM PDT 24 855993106 ps
T377 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3830604451 Jul 15 06:15:20 PM PDT 24 Jul 15 06:15:24 PM PDT 24 550073803 ps
T378 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2104965921 Jul 15 06:15:20 PM PDT 24 Jul 15 06:15:23 PM PDT 24 126553250 ps
T379 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2970952141 Jul 15 06:14:51 PM PDT 24 Jul 15 06:14:53 PM PDT 24 553142677 ps
T380 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4220190855 Jul 15 06:15:00 PM PDT 24 Jul 15 06:16:06 PM PDT 24 10288570003 ps
T381 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2469866522 Jul 15 06:15:08 PM PDT 24 Jul 15 06:15:15 PM PDT 24 3945339396 ps
T382 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1187293894 Jul 15 06:15:05 PM PDT 24 Jul 15 06:15:13 PM PDT 24 1872638308 ps
T383 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3198971774 Jul 15 06:14:51 PM PDT 24 Jul 15 06:15:39 PM PDT 24 54955699485 ps
T384 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.86055560 Jul 15 06:14:52 PM PDT 24 Jul 15 06:15:14 PM PDT 24 18798964636 ps
T385 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3630581313 Jul 15 06:15:22 PM PDT 24 Jul 15 06:15:29 PM PDT 24 703157416 ps
T386 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.683977661 Jul 15 06:14:58 PM PDT 24 Jul 15 06:15:00 PM PDT 24 92801197 ps
T387 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2513650635 Jul 15 06:15:05 PM PDT 24 Jul 15 06:15:13 PM PDT 24 1666500352 ps
T388 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1508397552 Jul 15 06:15:06 PM PDT 24 Jul 15 06:15:17 PM PDT 24 3555507067 ps
T389 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3041924147 Jul 15 06:14:52 PM PDT 24 Jul 15 06:14:56 PM PDT 24 207187532 ps
T390 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2172768521 Jul 15 06:15:08 PM PDT 24 Jul 15 06:15:16 PM PDT 24 4216473183 ps
T391 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1486647947 Jul 15 06:14:52 PM PDT 24 Jul 15 06:14:56 PM PDT 24 125979976 ps
T392 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1057679879 Jul 15 06:14:52 PM PDT 24 Jul 15 06:14:55 PM PDT 24 749951997 ps
T393 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.539831400 Jul 15 06:14:53 PM PDT 24 Jul 15 06:14:59 PM PDT 24 67148458 ps
T394 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.495093447 Jul 15 06:15:05 PM PDT 24 Jul 15 06:16:48 PM PDT 24 38278052937 ps
T395 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1455706889 Jul 15 06:15:19 PM PDT 24 Jul 15 06:15:20 PM PDT 24 615756347 ps
T396 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4080182481 Jul 15 06:15:07 PM PDT 24 Jul 15 06:15:15 PM PDT 24 4117719546 ps
T397 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1364535051 Jul 15 06:14:53 PM PDT 24 Jul 15 06:14:56 PM PDT 24 337150458 ps
T398 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3558121560 Jul 15 06:14:49 PM PDT 24 Jul 15 06:14:53 PM PDT 24 1138655126 ps
T399 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3890882228 Jul 15 06:15:15 PM PDT 24 Jul 15 06:15:19 PM PDT 24 168903567 ps
T400 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2244712556 Jul 15 06:15:16 PM PDT 24 Jul 15 06:16:50 PM PDT 24 64810577821 ps
T401 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2571067084 Jul 15 06:15:05 PM PDT 24 Jul 15 06:15:10 PM PDT 24 237111635 ps
T402 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4014121633 Jul 15 06:14:57 PM PDT 24 Jul 15 06:15:04 PM PDT 24 1263542466 ps
T403 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2012588631 Jul 15 06:15:25 PM PDT 24 Jul 15 06:15:27 PM PDT 24 1410662910 ps
T404 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.247596051 Jul 15 06:15:00 PM PDT 24 Jul 15 06:15:52 PM PDT 24 29200576294 ps
T405 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.283399899 Jul 15 06:14:54 PM PDT 24 Jul 15 06:14:58 PM PDT 24 1320866989 ps
T406 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1822359628 Jul 15 06:15:20 PM PDT 24 Jul 15 06:15:31 PM PDT 24 5927397696 ps
T407 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1385232627 Jul 15 06:14:58 PM PDT 24 Jul 15 06:15:03 PM PDT 24 166495149 ps
T408 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1269154422 Jul 15 06:14:52 PM PDT 24 Jul 15 06:15:45 PM PDT 24 2954856788 ps
T409 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1445259376 Jul 15 06:15:06 PM PDT 24 Jul 15 06:15:08 PM PDT 24 243872045 ps
T410 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3746825164 Jul 15 06:15:13 PM PDT 24 Jul 15 06:15:17 PM PDT 24 565432967 ps
T411 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2379095208 Jul 15 06:14:53 PM PDT 24 Jul 15 06:14:57 PM PDT 24 157751512 ps
T412 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1487663835 Jul 15 06:15:17 PM PDT 24 Jul 15 06:15:21 PM PDT 24 1621710386 ps
T413 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1656561725 Jul 15 06:15:16 PM PDT 24 Jul 15 06:15:18 PM PDT 24 185649178 ps
T414 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2503123369 Jul 15 06:15:24 PM PDT 24 Jul 15 06:15:30 PM PDT 24 233586463 ps
T415 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1689042060 Jul 15 06:15:13 PM PDT 24 Jul 15 06:15:29 PM PDT 24 2683432056 ps
T416 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3596166403 Jul 15 06:15:04 PM PDT 24 Jul 15 06:15:05 PM PDT 24 141804959 ps
T417 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2947997110 Jul 15 06:14:59 PM PDT 24 Jul 15 06:15:04 PM PDT 24 80230334 ps
T418 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3959754949 Jul 15 06:14:58 PM PDT 24 Jul 15 06:15:15 PM PDT 24 22824581913 ps
T419 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1794669577 Jul 15 06:15:17 PM PDT 24 Jul 15 06:15:22 PM PDT 24 2337572375 ps
T420 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1612993985 Jul 15 06:15:24 PM PDT 24 Jul 15 06:15:27 PM PDT 24 175965549 ps
T421 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3527405002 Jul 15 06:14:57 PM PDT 24 Jul 15 06:15:00 PM PDT 24 3196901770 ps
T422 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2210104759 Jul 15 06:15:04 PM PDT 24 Jul 15 06:15:11 PM PDT 24 4232233010 ps
T423 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2307994655 Jul 15 06:15:12 PM PDT 24 Jul 15 06:15:15 PM PDT 24 567459165 ps
T424 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.574576272 Jul 15 06:14:56 PM PDT 24 Jul 15 06:15:09 PM PDT 24 12907742375 ps
T425 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.717492848 Jul 15 06:15:08 PM PDT 24 Jul 15 06:15:15 PM PDT 24 641687454 ps
T426 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.159944372 Jul 15 06:15:20 PM PDT 24 Jul 15 06:15:23 PM PDT 24 1132679766 ps
T427 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1292280643 Jul 15 06:15:00 PM PDT 24 Jul 15 06:15:02 PM PDT 24 251299914 ps
T428 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3584834685 Jul 15 06:15:15 PM PDT 24 Jul 15 06:15:17 PM PDT 24 75774735 ps
T429 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1304073627 Jul 15 06:14:59 PM PDT 24 Jul 15 06:16:20 PM PDT 24 30415497900 ps
T430 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2990505532 Jul 15 06:14:56 PM PDT 24 Jul 15 06:15:04 PM PDT 24 571800568 ps
T431 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3412575087 Jul 15 06:15:21 PM PDT 24 Jul 15 06:15:30 PM PDT 24 1139567654 ps
T432 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1523224877 Jul 15 06:14:56 PM PDT 24 Jul 15 06:18:41 PM PDT 24 157537562400 ps
T433 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.944636195 Jul 15 06:14:56 PM PDT 24 Jul 15 06:14:58 PM PDT 24 143440389 ps
T434 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2949527488 Jul 15 06:15:23 PM PDT 24 Jul 15 06:15:25 PM PDT 24 165309696 ps
T435 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2274573272 Jul 15 06:15:00 PM PDT 24 Jul 15 06:15:12 PM PDT 24 832215390 ps
T436 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2089112361 Jul 15 06:14:59 PM PDT 24 Jul 15 06:15:06 PM PDT 24 187601887 ps
T437 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.687373565 Jul 15 06:14:52 PM PDT 24 Jul 15 06:14:54 PM PDT 24 93085455 ps
T438 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1511375161 Jul 15 06:14:55 PM PDT 24 Jul 15 06:14:57 PM PDT 24 147185823 ps
T439 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2938196068 Jul 15 06:14:53 PM PDT 24 Jul 15 06:16:02 PM PDT 24 1187848593 ps
T440 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1861586894 Jul 15 06:15:15 PM PDT 24 Jul 15 06:15:20 PM PDT 24 1156177272 ps

Test location /workspace/coverage/default/29.rv_dm_stress_all.3964588057
Short name T5
Test name
Test status
Simulation time 4515054290 ps
CPU time 13.12 seconds
Started Jul 15 06:22:25 PM PDT 24
Finished Jul 15 06:22:39 PM PDT 24
Peak memory 213036 kb
Host smart-745feb11-67ff-4911-af0b-eb1559ee53df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964588057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3964588057
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1664750386
Short name T25
Test name
Test status
Simulation time 8940229374 ps
CPU time 26.47 seconds
Started Jul 15 06:21:53 PM PDT 24
Finished Jul 15 06:22:20 PM PDT 24
Peak memory 213316 kb
Host smart-514df8bb-c437-44ef-9cca-a76d2eccd3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664750386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1664750386
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.965630095
Short name T77
Test name
Test status
Simulation time 51403780174 ps
CPU time 90.95 seconds
Started Jul 15 06:15:00 PM PDT 24
Finished Jul 15 06:16:32 PM PDT 24
Peak memory 221536 kb
Host smart-40588242-0876-436f-b3d7-867425c8e7cf
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965630095 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.965630095
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4118581888
Short name T61
Test name
Test status
Simulation time 975313409 ps
CPU time 16.54 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:15:09 PM PDT 24
Peak memory 213072 kb
Host smart-4c8623f7-771a-49dc-8b52-7f0f48e9e7b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118581888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.4118581888
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1772073045
Short name T56
Test name
Test status
Simulation time 58750802 ps
CPU time 0.74 seconds
Started Jul 15 06:22:24 PM PDT 24
Finished Jul 15 06:22:26 PM PDT 24
Peak memory 204780 kb
Host smart-0ca6756b-e48f-4b72-aa63-ec7e46c3db41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772073045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1772073045
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3623632197
Short name T86
Test name
Test status
Simulation time 314110966 ps
CPU time 5.05 seconds
Started Jul 15 06:15:26 PM PDT 24
Finished Jul 15 06:15:32 PM PDT 24
Peak memory 212808 kb
Host smart-71307603-0b5b-433d-b98d-5acdccd12924
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623632197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3623632197
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.2303423676
Short name T27
Test name
Test status
Simulation time 14364983328 ps
CPU time 13.64 seconds
Started Jul 15 06:22:27 PM PDT 24
Finished Jul 15 06:22:42 PM PDT 24
Peak memory 213304 kb
Host smart-aa9e4314-4890-4fd0-b349-a21440169694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303423676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2303423676
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3926836416
Short name T15
Test name
Test status
Simulation time 1318315076 ps
CPU time 1.66 seconds
Started Jul 15 06:20:56 PM PDT 24
Finished Jul 15 06:20:59 PM PDT 24
Peak memory 204880 kb
Host smart-a3e07cd8-bd77-4963-956f-dc4653ffce64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926836416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3926836416
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.771873954
Short name T167
Test name
Test status
Simulation time 37097532967 ps
CPU time 64.42 seconds
Started Jul 15 06:21:39 PM PDT 24
Finished Jul 15 06:22:44 PM PDT 24
Peak memory 213408 kb
Host smart-0cf0d4bf-5eee-4006-9657-b0c1cd036a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771873954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.771873954
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2242103090
Short name T42
Test name
Test status
Simulation time 581364800 ps
CPU time 1.91 seconds
Started Jul 15 06:21:09 PM PDT 24
Finished Jul 15 06:21:11 PM PDT 24
Peak memory 228252 kb
Host smart-79fec003-9f1e-4a66-a066-ddb3e9e9ddde
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242103090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2242103090
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3278946594
Short name T105
Test name
Test status
Simulation time 3500995101 ps
CPU time 73.04 seconds
Started Jul 15 06:14:55 PM PDT 24
Finished Jul 15 06:16:09 PM PDT 24
Peak memory 213168 kb
Host smart-3dec667e-94d6-411d-a6ae-430bdf7ca844
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278946594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3278946594
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.3997389833
Short name T84
Test name
Test status
Simulation time 3422153036 ps
CPU time 4.34 seconds
Started Jul 15 06:21:03 PM PDT 24
Finished Jul 15 06:21:08 PM PDT 24
Peak memory 204952 kb
Host smart-8843681e-100c-4df2-a411-d7f98a0d919d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997389833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3997389833
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3894638569
Short name T24
Test name
Test status
Simulation time 3587256278 ps
CPU time 11.47 seconds
Started Jul 15 06:21:12 PM PDT 24
Finished Jul 15 06:21:24 PM PDT 24
Peak memory 214924 kb
Host smart-4cb3d14c-28a1-4255-b65c-d2f7a880cb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894638569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3894638569
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.2292588054
Short name T19
Test name
Test status
Simulation time 8543662090 ps
CPU time 21.3 seconds
Started Jul 15 06:21:43 PM PDT 24
Finished Jul 15 06:22:04 PM PDT 24
Peak memory 213212 kb
Host smart-2d8a27b6-a042-4c7c-b51a-40a070353de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292588054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2292588054
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.944288138
Short name T8
Test name
Test status
Simulation time 5015898983 ps
CPU time 14.23 seconds
Started Jul 15 06:21:56 PM PDT 24
Finished Jul 15 06:22:11 PM PDT 24
Peak memory 221424 kb
Host smart-cd1cc587-4d08-4cdc-a2ee-e848f20468d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944288138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.944288138
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.2913616982
Short name T33
Test name
Test status
Simulation time 102689685 ps
CPU time 1.04 seconds
Started Jul 15 06:21:25 PM PDT 24
Finished Jul 15 06:21:27 PM PDT 24
Peak memory 204848 kb
Host smart-bdd45290-b02a-4d98-bd52-ed74fd73de4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913616982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2913616982
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1144681442
Short name T67
Test name
Test status
Simulation time 1014461118 ps
CPU time 4.33 seconds
Started Jul 15 06:15:20 PM PDT 24
Finished Jul 15 06:15:25 PM PDT 24
Peak memory 204908 kb
Host smart-add802cf-2cbf-4464-b5ad-7418ed1679c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144681442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1144681442
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.646000007
Short name T22
Test name
Test status
Simulation time 1067821182 ps
CPU time 3.81 seconds
Started Jul 15 06:21:12 PM PDT 24
Finished Jul 15 06:21:16 PM PDT 24
Peak memory 204772 kb
Host smart-754d45e6-a73e-406d-8c77-ee312e2277bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646000007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.646000007
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2078474634
Short name T159
Test name
Test status
Simulation time 29472340912 ps
CPU time 43.48 seconds
Started Jul 15 06:22:14 PM PDT 24
Finished Jul 15 06:22:58 PM PDT 24
Peak memory 213364 kb
Host smart-62a0883e-da36-45a3-9154-0aabb9d868a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078474634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2078474634
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.2064682393
Short name T46
Test name
Test status
Simulation time 112032580 ps
CPU time 0.94 seconds
Started Jul 15 06:21:09 PM PDT 24
Finished Jul 15 06:21:11 PM PDT 24
Peak memory 204800 kb
Host smart-3546cd13-0f4e-4399-b826-f2609a4236ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064682393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2064682393
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3146229326
Short name T32
Test name
Test status
Simulation time 67732699 ps
CPU time 0.95 seconds
Started Jul 15 06:21:24 PM PDT 24
Finished Jul 15 06:21:25 PM PDT 24
Peak memory 213008 kb
Host smart-c835ba43-09ad-439b-88cd-0a1c95928298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146229326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3146229326
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1582619048
Short name T10
Test name
Test status
Simulation time 6111757415 ps
CPU time 9.81 seconds
Started Jul 15 06:22:13 PM PDT 24
Finished Jul 15 06:22:23 PM PDT 24
Peak memory 215148 kb
Host smart-4cd36261-6c4c-4144-b5f5-e3942dfe94ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582619048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1582619048
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4274580942
Short name T176
Test name
Test status
Simulation time 1392213681 ps
CPU time 17.76 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:15:12 PM PDT 24
Peak memory 213068 kb
Host smart-eb66acb2-fb35-4ea9-9a4b-33174c6d6631
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274580942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.4274580942
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.2958364653
Short name T14
Test name
Test status
Simulation time 9418681511 ps
CPU time 4.28 seconds
Started Jul 15 06:21:58 PM PDT 24
Finished Jul 15 06:22:03 PM PDT 24
Peak memory 205004 kb
Host smart-e3b5bbea-1d51-44a9-9af9-3a905b5a7a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958364653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2958364653
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2582775547
Short name T13
Test name
Test status
Simulation time 5206845317 ps
CPU time 4.81 seconds
Started Jul 15 06:22:19 PM PDT 24
Finished Jul 15 06:22:24 PM PDT 24
Peak memory 205080 kb
Host smart-a79ad5b9-6561-4ec1-8684-3b3b22ac8254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582775547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2582775547
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2796219420
Short name T35
Test name
Test status
Simulation time 168799953 ps
CPU time 0.92 seconds
Started Jul 15 06:21:11 PM PDT 24
Finished Jul 15 06:21:13 PM PDT 24
Peak memory 204796 kb
Host smart-9b2d0fdd-54a3-4bae-a69d-f98c1ad58c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796219420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2796219420
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.171289208
Short name T158
Test name
Test status
Simulation time 2640518990 ps
CPU time 8.59 seconds
Started Jul 15 06:20:55 PM PDT 24
Finished Jul 15 06:21:04 PM PDT 24
Peak memory 221520 kb
Host smart-3082c711-4496-42a9-ba8c-0e97eb204bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171289208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.171289208
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2059235295
Short name T146
Test name
Test status
Simulation time 6452204068 ps
CPU time 6.42 seconds
Started Jul 15 06:20:57 PM PDT 24
Finished Jul 15 06:21:04 PM PDT 24
Peak memory 221476 kb
Host smart-5f445942-45fb-4243-b9e3-be3540544acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059235295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2059235295
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.3785522045
Short name T7
Test name
Test status
Simulation time 4682356396 ps
CPU time 4.21 seconds
Started Jul 15 06:22:25 PM PDT 24
Finished Jul 15 06:22:29 PM PDT 24
Peak memory 205100 kb
Host smart-f2136ac0-f92d-42ab-8a37-db1cd42cf83f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785522045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3785522045
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.807377397
Short name T59
Test name
Test status
Simulation time 113669143 ps
CPU time 1.07 seconds
Started Jul 15 06:21:21 PM PDT 24
Finished Jul 15 06:21:23 PM PDT 24
Peak memory 215492 kb
Host smart-4dab9626-c8ed-4a96-9f0b-d13e453ced85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807377397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.807377397
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1656606868
Short name T48
Test name
Test status
Simulation time 8580007962 ps
CPU time 12.11 seconds
Started Jul 15 06:21:32 PM PDT 24
Finished Jul 15 06:21:45 PM PDT 24
Peak memory 213380 kb
Host smart-8ceb88fe-b04c-489d-b506-a108552c208e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656606868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1656606868
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3006970608
Short name T156
Test name
Test status
Simulation time 5093949056 ps
CPU time 15.84 seconds
Started Jul 15 06:21:44 PM PDT 24
Finished Jul 15 06:22:01 PM PDT 24
Peak memory 213336 kb
Host smart-1f35eb70-5ec8-4d7b-b899-7a88531c0d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006970608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3006970608
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.568005504
Short name T87
Test name
Test status
Simulation time 1005008056 ps
CPU time 16.22 seconds
Started Jul 15 06:15:06 PM PDT 24
Finished Jul 15 06:15:23 PM PDT 24
Peak memory 213176 kb
Host smart-058c6266-5484-493b-9e31-cb2dcb4c8abf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568005504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.568005504
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2151208533
Short name T322
Test name
Test status
Simulation time 225574726 ps
CPU time 1.07 seconds
Started Jul 15 06:14:54 PM PDT 24
Finished Jul 15 06:14:57 PM PDT 24
Peak memory 204716 kb
Host smart-cc56ed45-107c-428a-9bb2-9cd7f0ce1258
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151208533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2151208533
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.742253859
Short name T103
Test name
Test status
Simulation time 8752808657 ps
CPU time 16.74 seconds
Started Jul 15 06:14:55 PM PDT 24
Finished Jul 15 06:15:13 PM PDT 24
Peak memory 205020 kb
Host smart-c178918c-dc90-46c7-a4c0-e18f8243db5b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742253859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.742253859
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2447943896
Short name T110
Test name
Test status
Simulation time 309514673 ps
CPU time 1.79 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:14:57 PM PDT 24
Peak memory 213168 kb
Host smart-50eb85b7-705b-4caa-acdf-cd335e54f8fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447943896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2447943896
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.891436138
Short name T65
Test name
Test status
Simulation time 153295169 ps
CPU time 2.56 seconds
Started Jul 15 06:15:13 PM PDT 24
Finished Jul 15 06:15:17 PM PDT 24
Peak memory 213084 kb
Host smart-a606afc0-0cf7-4246-a65d-9bfd7dd96385
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891436138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.891436138
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.1805360229
Short name T34
Test name
Test status
Simulation time 2208950079 ps
CPU time 3.7 seconds
Started Jul 15 06:21:31 PM PDT 24
Finished Jul 15 06:21:35 PM PDT 24
Peak memory 205008 kb
Host smart-0456a403-d50d-470e-a07c-8d810789ba7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805360229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1805360229
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.932557545
Short name T149
Test name
Test status
Simulation time 2454275750 ps
CPU time 7.22 seconds
Started Jul 15 06:22:05 PM PDT 24
Finished Jul 15 06:22:12 PM PDT 24
Peak memory 213316 kb
Host smart-0feac288-ee80-4f79-a541-cfc68577704b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932557545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.932557545
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.742704
Short name T174
Test name
Test status
Simulation time 8458953893 ps
CPU time 23.66 seconds
Started Jul 15 06:21:57 PM PDT 24
Finished Jul 15 06:22:21 PM PDT 24
Peak memory 213352 kb
Host smart-046c0fe3-6101-4b29-aef6-8b37618b79d1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=742704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_a
ccess.742704
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.4225275129
Short name T23
Test name
Test status
Simulation time 12326827214 ps
CPU time 5.65 seconds
Started Jul 15 06:21:29 PM PDT 24
Finished Jul 15 06:21:35 PM PDT 24
Peak memory 213212 kb
Host smart-eb3def86-99df-4a6e-878e-a3a1dcce4cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225275129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.4225275129
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3473649600
Short name T29
Test name
Test status
Simulation time 342944118 ps
CPU time 1.61 seconds
Started Jul 15 06:21:02 PM PDT 24
Finished Jul 15 06:21:04 PM PDT 24
Peak memory 204784 kb
Host smart-3beed764-c312-4ccf-a92d-2fa45b4fbf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473649600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3473649600
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.921277429
Short name T180
Test name
Test status
Simulation time 3217149012 ps
CPU time 23.09 seconds
Started Jul 15 06:15:20 PM PDT 24
Finished Jul 15 06:15:44 PM PDT 24
Peak memory 213156 kb
Host smart-23185550-d72b-4c11-a6c8-4ac63435b7df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921277429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.921277429
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2641917681
Short name T155
Test name
Test status
Simulation time 727524840 ps
CPU time 1.77 seconds
Started Jul 15 06:21:08 PM PDT 24
Finished Jul 15 06:21:10 PM PDT 24
Peak memory 204876 kb
Host smart-e8938dca-38e3-4161-b3d0-cb8aa4ad6f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641917681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2641917681
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1870411809
Short name T170
Test name
Test status
Simulation time 2887076550 ps
CPU time 4.43 seconds
Started Jul 15 06:20:56 PM PDT 24
Finished Jul 15 06:21:01 PM PDT 24
Peak memory 205116 kb
Host smart-cb578987-b82f-4fe9-beca-eafc79149db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870411809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1870411809
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2387477182
Short name T132
Test name
Test status
Simulation time 13476642044 ps
CPU time 17.83 seconds
Started Jul 15 06:21:11 PM PDT 24
Finished Jul 15 06:21:30 PM PDT 24
Peak memory 214424 kb
Host smart-d3b42c83-c98b-4190-920a-62d21cf38fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387477182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2387477182
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3610178822
Short name T165
Test name
Test status
Simulation time 4483121297 ps
CPU time 11.62 seconds
Started Jul 15 06:21:52 PM PDT 24
Finished Jul 15 06:22:05 PM PDT 24
Peak memory 213340 kb
Host smart-2b765969-5b28-4a96-b067-599fe324da30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610178822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3610178822
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3881134888
Short name T168
Test name
Test status
Simulation time 3564469094 ps
CPU time 3.94 seconds
Started Jul 15 06:21:49 PM PDT 24
Finished Jul 15 06:21:53 PM PDT 24
Peak memory 213352 kb
Host smart-8a1f858b-ee68-4a38-ac85-7e309712dae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881134888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3881134888
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.3954382177
Short name T52
Test name
Test status
Simulation time 3777366511 ps
CPU time 9.47 seconds
Started Jul 15 06:21:53 PM PDT 24
Finished Jul 15 06:22:03 PM PDT 24
Peak memory 213248 kb
Host smart-792136ca-a746-4ae8-9def-659dd2ac8a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954382177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3954382177
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2317690566
Short name T151
Test name
Test status
Simulation time 4162115059 ps
CPU time 3.32 seconds
Started Jul 15 06:22:01 PM PDT 24
Finished Jul 15 06:22:05 PM PDT 24
Peak memory 205104 kb
Host smart-4366a195-f4de-4711-8c87-deaba7535741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317690566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2317690566
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3354075187
Short name T55
Test name
Test status
Simulation time 2297994345 ps
CPU time 4.41 seconds
Started Jul 15 06:22:01 PM PDT 24
Finished Jul 15 06:22:06 PM PDT 24
Peak memory 205080 kb
Host smart-3c7a3bc1-db61-4e0f-a4c1-106f5892de9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354075187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3354075187
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3388717799
Short name T144
Test name
Test status
Simulation time 3541263915 ps
CPU time 5.57 seconds
Started Jul 15 06:22:00 PM PDT 24
Finished Jul 15 06:22:06 PM PDT 24
Peak memory 205016 kb
Host smart-7c8821a7-0101-4a26-9ae4-3621fc169fff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388717799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3388717799
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1646251421
Short name T161
Test name
Test status
Simulation time 7358153644 ps
CPU time 7.96 seconds
Started Jul 15 06:22:04 PM PDT 24
Finished Jul 15 06:22:13 PM PDT 24
Peak memory 216072 kb
Host smart-6d3938e3-05ee-4d44-aba8-9772eb0df1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646251421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1646251421
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1614638612
Short name T73
Test name
Test status
Simulation time 9351133797 ps
CPU time 8 seconds
Started Jul 15 06:22:04 PM PDT 24
Finished Jul 15 06:22:13 PM PDT 24
Peak memory 213364 kb
Host smart-fae7eea8-d1ac-49e2-8ac9-b9512233a2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614638612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1614638612
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.3921018523
Short name T172
Test name
Test status
Simulation time 2607578338 ps
CPU time 3.4 seconds
Started Jul 15 06:22:03 PM PDT 24
Finished Jul 15 06:22:07 PM PDT 24
Peak memory 213260 kb
Host smart-dee92e84-cda6-4696-9f6c-2916e311bd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921018523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3921018523
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.894212965
Short name T166
Test name
Test status
Simulation time 6733941661 ps
CPU time 11.16 seconds
Started Jul 15 06:22:04 PM PDT 24
Finished Jul 15 06:22:15 PM PDT 24
Peak memory 213328 kb
Host smart-d320af9d-c237-4b1b-ae68-8636161561a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894212965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.894212965
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2028131821
Short name T152
Test name
Test status
Simulation time 4925547785 ps
CPU time 8.4 seconds
Started Jul 15 06:22:06 PM PDT 24
Finished Jul 15 06:22:15 PM PDT 24
Peak memory 213416 kb
Host smart-60cd5d47-4165-4c00-8f80-043133034af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028131821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2028131821
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.111611388
Short name T171
Test name
Test status
Simulation time 7467950543 ps
CPU time 13.51 seconds
Started Jul 15 06:22:07 PM PDT 24
Finished Jul 15 06:22:21 PM PDT 24
Peak memory 213348 kb
Host smart-b32ade40-cd1d-425f-af56-6524ef9a523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111611388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.111611388
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.265188978
Short name T137
Test name
Test status
Simulation time 7071899547 ps
CPU time 10.73 seconds
Started Jul 15 06:22:15 PM PDT 24
Finished Jul 15 06:22:26 PM PDT 24
Peak memory 218480 kb
Host smart-31d77b20-2f1c-45ad-bf3d-ad97e037493d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265188978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.265188978
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.1834852612
Short name T141
Test name
Test status
Simulation time 11143760967 ps
CPU time 4.43 seconds
Started Jul 15 06:22:14 PM PDT 24
Finished Jul 15 06:22:19 PM PDT 24
Peak memory 213272 kb
Host smart-d0fab2c0-8d79-4e17-a8fa-ed17defa0a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834852612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1834852612
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.578851449
Short name T145
Test name
Test status
Simulation time 7585692707 ps
CPU time 7.32 seconds
Started Jul 15 06:22:22 PM PDT 24
Finished Jul 15 06:22:30 PM PDT 24
Peak memory 213236 kb
Host smart-af1b4952-f08a-453f-a976-71d5bf1f11cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578851449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.578851449
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.2658039767
Short name T142
Test name
Test status
Simulation time 6759715991 ps
CPU time 5.78 seconds
Started Jul 15 06:22:21 PM PDT 24
Finished Jul 15 06:22:28 PM PDT 24
Peak memory 205012 kb
Host smart-4536968e-023f-4dc6-b2c8-66df684192b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658039767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2658039767
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3437956805
Short name T173
Test name
Test status
Simulation time 1885695775 ps
CPU time 2.18 seconds
Started Jul 15 06:21:31 PM PDT 24
Finished Jul 15 06:21:34 PM PDT 24
Peak memory 205004 kb
Host smart-e544d1fc-4327-456f-ae35-2519cbd0c4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437956805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3437956805
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3528426816
Short name T129
Test name
Test status
Simulation time 2461298504 ps
CPU time 2.69 seconds
Started Jul 15 06:22:25 PM PDT 24
Finished Jul 15 06:22:28 PM PDT 24
Peak memory 213072 kb
Host smart-53cbbbff-2fda-4d48-b11f-47d847e357fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528426816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3528426816
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.2886506476
Short name T133
Test name
Test status
Simulation time 4837586430 ps
CPU time 6.04 seconds
Started Jul 15 06:22:23 PM PDT 24
Finished Jul 15 06:22:30 PM PDT 24
Peak memory 213280 kb
Host smart-9582b245-f9c8-461e-bd77-61b6b214e86e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886506476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2886506476
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.3370903359
Short name T139
Test name
Test status
Simulation time 10202514851 ps
CPU time 31.64 seconds
Started Jul 15 06:22:21 PM PDT 24
Finished Jul 15 06:22:54 PM PDT 24
Peak memory 213216 kb
Host smart-99051ce6-e7d8-48ad-ac8d-5dc4ee06847d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370903359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3370903359
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2412169788
Short name T150
Test name
Test status
Simulation time 3466891655 ps
CPU time 4.52 seconds
Started Jul 15 06:21:39 PM PDT 24
Finished Jul 15 06:21:44 PM PDT 24
Peak memory 213312 kb
Host smart-4039547e-62c3-4c5e-95fc-12da8f63f481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412169788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2412169788
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.4179402278
Short name T140
Test name
Test status
Simulation time 3355840330 ps
CPU time 5.13 seconds
Started Jul 15 06:21:45 PM PDT 24
Finished Jul 15 06:21:51 PM PDT 24
Peak memory 213208 kb
Host smart-3350b3a0-727e-4d3a-8a4e-7c83b71535b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179402278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.4179402278
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1999164360
Short name T147
Test name
Test status
Simulation time 5139351479 ps
CPU time 13.32 seconds
Started Jul 15 06:21:45 PM PDT 24
Finished Jul 15 06:21:59 PM PDT 24
Peak memory 221464 kb
Host smart-aa484767-67ec-4c0e-b275-edcafcb331d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999164360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1999164360
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1258665387
Short name T297
Test name
Test status
Simulation time 40571973901 ps
CPU time 25.08 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:15:19 PM PDT 24
Peak memory 205008 kb
Host smart-30c30079-43b6-4d3e-9e8d-a05610b3798b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258665387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1258665387
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1768266006
Short name T104
Test name
Test status
Simulation time 2324545802 ps
CPU time 67.64 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:16:02 PM PDT 24
Peak memory 213160 kb
Host smart-bdb22939-efe7-4395-83a9-c26c0f400b06
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768266006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1768266006
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3764306106
Short name T336
Test name
Test status
Simulation time 4516683882 ps
CPU time 28.19 seconds
Started Jul 15 06:14:49 PM PDT 24
Finished Jul 15 06:15:17 PM PDT 24
Peak memory 213192 kb
Host smart-6f63ac80-3947-4305-a81a-791c744ca027
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764306106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3764306106
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.500047314
Short name T89
Test name
Test status
Simulation time 205153711 ps
CPU time 1.98 seconds
Started Jul 15 06:14:58 PM PDT 24
Finished Jul 15 06:15:02 PM PDT 24
Peak memory 213156 kb
Host smart-3453cf46-7682-40b9-9eb4-a20d70fbc053
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500047314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.500047314
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3558121560
Short name T398
Test name
Test status
Simulation time 1138655126 ps
CPU time 3.87 seconds
Started Jul 15 06:14:49 PM PDT 24
Finished Jul 15 06:14:53 PM PDT 24
Peak memory 217464 kb
Host smart-2ad9b228-43e2-4103-84fa-c59196a0d664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558121560 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3558121560
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2379095208
Short name T411
Test name
Test status
Simulation time 157751512 ps
CPU time 2.27 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:14:57 PM PDT 24
Peak memory 213088 kb
Host smart-9ee4ffb6-a16f-495b-b2c9-f5698c0f3be0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379095208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2379095208
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3625842873
Short name T290
Test name
Test status
Simulation time 14034877055 ps
CPU time 9.42 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:15:04 PM PDT 24
Peak memory 204868 kb
Host smart-6a239895-4df4-4bed-8227-e776b49f2ed7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625842873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.3625842873
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1890821899
Short name T299
Test name
Test status
Simulation time 2070703662 ps
CPU time 3.71 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:14:58 PM PDT 24
Peak memory 204840 kb
Host smart-b94cb8bb-a101-4f32-ad0e-85b414b29784
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890821899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
890821899
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1330581956
Short name T353
Test name
Test status
Simulation time 692055310 ps
CPU time 1.34 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:14:55 PM PDT 24
Peak memory 204796 kb
Host smart-25088579-1c50-400d-8dc4-a811ee7a32cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330581956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.1330581956
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1084192164
Short name T354
Test name
Test status
Simulation time 18045470834 ps
CPU time 25.7 seconds
Started Jul 15 06:14:51 PM PDT 24
Finished Jul 15 06:15:17 PM PDT 24
Peak memory 204972 kb
Host smart-a5f9664b-d222-49a5-8d44-a993fd835aaa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084192164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1084192164
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2970952141
Short name T379
Test name
Test status
Simulation time 553142677 ps
CPU time 1.14 seconds
Started Jul 15 06:14:51 PM PDT 24
Finished Jul 15 06:14:53 PM PDT 24
Peak memory 204816 kb
Host smart-c241dfef-50f8-413e-865c-d1d586261381
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970952141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
970952141
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.687373565
Short name T437
Test name
Test status
Simulation time 93085455 ps
CPU time 0.78 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:14:54 PM PDT 24
Peak memory 204800 kb
Host smart-b8fd1d2f-e3a2-4b84-a205-c7ef1637b2e2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687373565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.687373565
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1511375161
Short name T438
Test name
Test status
Simulation time 147185823 ps
CPU time 0.79 seconds
Started Jul 15 06:14:55 PM PDT 24
Finished Jul 15 06:14:57 PM PDT 24
Peak memory 204824 kb
Host smart-8ff097b1-1ad7-475b-8769-c658ead329db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511375161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1511375161
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.284528747
Short name T106
Test name
Test status
Simulation time 224563213 ps
CPU time 6.83 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:15:00 PM PDT 24
Peak memory 204976 kb
Host smart-00b2308a-bea1-473f-943f-e03771689a90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284528747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.284528747
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3198971774
Short name T383
Test name
Test status
Simulation time 54955699485 ps
CPU time 47.33 seconds
Started Jul 15 06:14:51 PM PDT 24
Finished Jul 15 06:15:39 PM PDT 24
Peak memory 221424 kb
Host smart-f4afeed8-9b1a-4209-878f-bd65949b170a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198971774 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3198971774
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1886019731
Short name T344
Test name
Test status
Simulation time 221645944 ps
CPU time 3.63 seconds
Started Jul 15 06:14:50 PM PDT 24
Finished Jul 15 06:14:54 PM PDT 24
Peak memory 213216 kb
Host smart-beb41213-6c71-4663-87f0-aaddc662f527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886019731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1886019731
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.811154651
Short name T91
Test name
Test status
Simulation time 4653981658 ps
CPU time 33.47 seconds
Started Jul 15 06:14:51 PM PDT 24
Finished Jul 15 06:15:26 PM PDT 24
Peak memory 213172 kb
Host smart-1482a597-c637-44b4-bc19-7e0ef1071377
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811154651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.811154651
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2909409022
Short name T115
Test name
Test status
Simulation time 63481892561 ps
CPU time 39.24 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:15:34 PM PDT 24
Peak memory 205056 kb
Host smart-fe401495-e6e6-47e8-82d2-a0a5165c81f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909409022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2909409022
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1486647947
Short name T391
Test name
Test status
Simulation time 125979976 ps
CPU time 2.41 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:14:56 PM PDT 24
Peak memory 213184 kb
Host smart-3cd98a89-4260-45c3-9727-0feb0255a739
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486647947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1486647947
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3608857653
Short name T126
Test name
Test status
Simulation time 1152622023 ps
CPU time 3.8 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:14:56 PM PDT 24
Peak memory 218552 kb
Host smart-7188960c-7348-48f1-88e2-2dc8756f3a51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608857653 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3608857653
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3041924147
Short name T389
Test name
Test status
Simulation time 207187532 ps
CPU time 2.52 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:14:56 PM PDT 24
Peak memory 213060 kb
Host smart-3f2474b9-7581-49a9-8519-fd3bbc312fd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041924147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3041924147
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3846494987
Short name T349
Test name
Test status
Simulation time 99506400240 ps
CPU time 239.71 seconds
Started Jul 15 06:14:50 PM PDT 24
Finished Jul 15 06:18:51 PM PDT 24
Peak memory 205024 kb
Host smart-df3b2116-dbbd-41b9-bb51-052585c5faf8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846494987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3846494987
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3041292277
Short name T321
Test name
Test status
Simulation time 14631917910 ps
CPU time 22.74 seconds
Started Jul 15 06:14:54 PM PDT 24
Finished Jul 15 06:15:19 PM PDT 24
Peak memory 204884 kb
Host smart-1180a855-86b1-4695-9805-0dcbc21cc33e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041292277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3041292277
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.673370419
Short name T100
Test name
Test status
Simulation time 11875056574 ps
CPU time 32.47 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:15:27 PM PDT 24
Peak memory 204968 kb
Host smart-8058d979-5d76-49e1-b2a9-183aab913a4f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673370419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.673370419
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.283399899
Short name T405
Test name
Test status
Simulation time 1320866989 ps
CPU time 2.06 seconds
Started Jul 15 06:14:54 PM PDT 24
Finished Jul 15 06:14:58 PM PDT 24
Peak memory 204900 kb
Host smart-9c6b7d85-8762-4b14-91d0-2b15bf6335e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283399899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.283399899
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1057679879
Short name T392
Test name
Test status
Simulation time 749951997 ps
CPU time 1.14 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:14:55 PM PDT 24
Peak memory 204820 kb
Host smart-ed19b0ad-4f13-4b39-9c80-0096cd43290c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057679879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1057679879
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4123353538
Short name T80
Test name
Test status
Simulation time 43175825119 ps
CPU time 106.77 seconds
Started Jul 15 06:14:51 PM PDT 24
Finished Jul 15 06:16:38 PM PDT 24
Peak memory 204948 kb
Host smart-4f09e7d3-3b01-45d9-9cf5-44692b69a3c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123353538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.4123353538
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.499100022
Short name T362
Test name
Test status
Simulation time 243176842 ps
CPU time 1.27 seconds
Started Jul 15 06:14:59 PM PDT 24
Finished Jul 15 06:15:01 PM PDT 24
Peak memory 204680 kb
Host smart-dc3e649d-a4dd-4fbd-b87a-6a04a090a137
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499100022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.499100022
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.552519407
Short name T365
Test name
Test status
Simulation time 305203382 ps
CPU time 0.79 seconds
Started Jul 15 06:14:51 PM PDT 24
Finished Jul 15 06:14:52 PM PDT 24
Peak memory 204804 kb
Host smart-a3fda6c2-083b-4355-a4e6-b540693272e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552519407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.552519407
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4258196361
Short name T294
Test name
Test status
Simulation time 67463674 ps
CPU time 0.78 seconds
Started Jul 15 06:14:55 PM PDT 24
Finished Jul 15 06:14:57 PM PDT 24
Peak memory 204808 kb
Host smart-5e0cda77-c7e5-4e33-9679-612915494aa6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258196361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.4258196361
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3268909683
Short name T368
Test name
Test status
Simulation time 44573919 ps
CPU time 0.71 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:14:54 PM PDT 24
Peak memory 204816 kb
Host smart-263662ed-42ab-48a8-97d7-de35a434019e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268909683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3268909683
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2905331014
Short name T118
Test name
Test status
Simulation time 304527025 ps
CPU time 4.41 seconds
Started Jul 15 06:14:49 PM PDT 24
Finished Jul 15 06:14:54 PM PDT 24
Peak memory 204904 kb
Host smart-d9c676fe-65da-4162-a4da-766925af3a98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905331014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2905331014
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1277840899
Short name T333
Test name
Test status
Simulation time 32332578662 ps
CPU time 34.38 seconds
Started Jul 15 06:14:59 PM PDT 24
Finished Jul 15 06:15:34 PM PDT 24
Peak memory 220000 kb
Host smart-6a1ad848-9fcc-4cd8-81a1-f39405d1d8be
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277840899 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1277840899
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.539831400
Short name T393
Test name
Test status
Simulation time 67148458 ps
CPU time 3.66 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:14:59 PM PDT 24
Peak memory 213244 kb
Host smart-6f6e6fdb-564c-4adf-8cc1-e43395d1f48d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539831400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.539831400
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3839385309
Short name T98
Test name
Test status
Simulation time 1538561494 ps
CPU time 9.15 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:15:04 PM PDT 24
Peak memory 213144 kb
Host smart-88f78dab-de45-489b-bb23-64a5029c7f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839385309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3839385309
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2895532648
Short name T127
Test name
Test status
Simulation time 360347866 ps
CPU time 2.35 seconds
Started Jul 15 06:15:13 PM PDT 24
Finished Jul 15 06:15:16 PM PDT 24
Peak memory 216628 kb
Host smart-af078d44-a045-44fd-b10d-7d23b9783a4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895532648 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2895532648
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1481126828
Short name T112
Test name
Test status
Simulation time 184928072 ps
CPU time 2.34 seconds
Started Jul 15 06:15:14 PM PDT 24
Finished Jul 15 06:15:17 PM PDT 24
Peak memory 213124 kb
Host smart-19c5dd4b-df2d-4bd9-aa30-fb4756d4bb67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481126828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1481126828
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3460162351
Short name T319
Test name
Test status
Simulation time 9642731622 ps
CPU time 27.11 seconds
Started Jul 15 06:15:07 PM PDT 24
Finished Jul 15 06:15:36 PM PDT 24
Peak memory 204936 kb
Host smart-ca1d67e5-517e-4d41-861a-6083f017a7b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460162351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.3460162351
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.323410799
Short name T361
Test name
Test status
Simulation time 2510192020 ps
CPU time 3.69 seconds
Started Jul 15 06:15:07 PM PDT 24
Finished Jul 15 06:15:12 PM PDT 24
Peak memory 204996 kb
Host smart-61fd6824-9344-4a4c-b31d-e8f1142347ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323410799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.323410799
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2346591962
Short name T348
Test name
Test status
Simulation time 298607046 ps
CPU time 0.95 seconds
Started Jul 15 06:15:05 PM PDT 24
Finished Jul 15 06:15:06 PM PDT 24
Peak memory 204776 kb
Host smart-1eb83d03-1b24-454e-8157-37ae9799078c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346591962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2346591962
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3762386
Short name T122
Test name
Test status
Simulation time 233337970 ps
CPU time 3.96 seconds
Started Jul 15 06:15:12 PM PDT 24
Finished Jul 15 06:15:17 PM PDT 24
Peak memory 204948 kb
Host smart-12873b12-e948-4d39-b964-4c98fc3f30d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_cs
r_outstanding.3762386
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2227741878
Short name T85
Test name
Test status
Simulation time 507027114 ps
CPU time 3.45 seconds
Started Jul 15 06:15:15 PM PDT 24
Finished Jul 15 06:15:19 PM PDT 24
Peak memory 213220 kb
Host smart-5550f38d-474f-4278-b052-f625f6f6d671
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227741878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2227741878
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1689042060
Short name T415
Test name
Test status
Simulation time 2683432056 ps
CPU time 15.63 seconds
Started Jul 15 06:15:13 PM PDT 24
Finished Jul 15 06:15:29 PM PDT 24
Peak memory 213168 kb
Host smart-97780988-a472-4421-bae0-217591accd7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689042060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
689042060
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1669268264
Short name T63
Test name
Test status
Simulation time 206946544 ps
CPU time 4.11 seconds
Started Jul 15 06:15:13 PM PDT 24
Finished Jul 15 06:15:18 PM PDT 24
Peak memory 219508 kb
Host smart-8503046c-e517-4307-a339-60a01f0358de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669268264 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1669268264
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3989100633
Short name T356
Test name
Test status
Simulation time 87343467 ps
CPU time 1.7 seconds
Started Jul 15 06:15:14 PM PDT 24
Finished Jul 15 06:15:17 PM PDT 24
Peak memory 213144 kb
Host smart-4730fccb-afc3-4fc6-a32b-ce675224e843
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989100633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3989100633
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3659051708
Short name T291
Test name
Test status
Simulation time 41671561 ps
CPU time 0.7 seconds
Started Jul 15 06:15:12 PM PDT 24
Finished Jul 15 06:15:13 PM PDT 24
Peak memory 204800 kb
Host smart-ad8024b9-26a2-430b-96e1-a48220bd4f81
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659051708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3659051708
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1778458355
Short name T352
Test name
Test status
Simulation time 1067516110 ps
CPU time 3.82 seconds
Started Jul 15 06:15:13 PM PDT 24
Finished Jul 15 06:15:18 PM PDT 24
Peak memory 204900 kb
Host smart-626ef08b-7a3e-4a1a-97d1-5b18adcaa176
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778458355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1778458355
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2495446168
Short name T324
Test name
Test status
Simulation time 620126379 ps
CPU time 0.98 seconds
Started Jul 15 06:15:14 PM PDT 24
Finished Jul 15 06:15:15 PM PDT 24
Peak memory 204696 kb
Host smart-f4ab46f1-08c7-4ffe-802d-8906086740f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495446168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2495446168
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1297996271
Short name T346
Test name
Test status
Simulation time 360748553 ps
CPU time 7.06 seconds
Started Jul 15 06:15:11 PM PDT 24
Finished Jul 15 06:15:19 PM PDT 24
Peak memory 204904 kb
Host smart-1b687ae0-9e67-4d13-9d0e-e65d3e0d2d4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297996271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1297996271
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2488139394
Short name T177
Test name
Test status
Simulation time 5763434982 ps
CPU time 30.87 seconds
Started Jul 15 06:15:17 PM PDT 24
Finished Jul 15 06:15:49 PM PDT 24
Peak memory 213256 kb
Host smart-f1df4051-8a0a-4c6c-904c-e8c8f02c6312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488139394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
488139394
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.64781895
Short name T128
Test name
Test status
Simulation time 1855223360 ps
CPU time 6.36 seconds
Started Jul 15 06:15:12 PM PDT 24
Finished Jul 15 06:15:18 PM PDT 24
Peak memory 221188 kb
Host smart-1a5bad32-4fcd-4597-ae2d-60d6a07f3019
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64781895 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.64781895
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.332566974
Short name T369
Test name
Test status
Simulation time 103714167 ps
CPU time 2.22 seconds
Started Jul 15 06:15:13 PM PDT 24
Finished Jul 15 06:15:16 PM PDT 24
Peak memory 213156 kb
Host smart-2b0892fa-5cb6-4c1f-97b3-a5a69074e1a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332566974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.332566974
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3176087093
Short name T296
Test name
Test status
Simulation time 14410679514 ps
CPU time 7.32 seconds
Started Jul 15 06:15:15 PM PDT 24
Finished Jul 15 06:15:23 PM PDT 24
Peak memory 204992 kb
Host smart-4bf834e5-8e49-4db2-b08e-d3aa1f115776
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176087093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3176087093
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1794669577
Short name T419
Test name
Test status
Simulation time 2337572375 ps
CPU time 4.56 seconds
Started Jul 15 06:15:17 PM PDT 24
Finished Jul 15 06:15:22 PM PDT 24
Peak memory 204960 kb
Host smart-6ec3b3cf-53d5-4d27-9f7b-97f65eead245
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794669577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1794669577
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2307994655
Short name T423
Test name
Test status
Simulation time 567459165 ps
CPU time 2.12 seconds
Started Jul 15 06:15:12 PM PDT 24
Finished Jul 15 06:15:15 PM PDT 24
Peak memory 204796 kb
Host smart-6aa693d7-8bb8-412a-834d-8225822edeee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307994655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2307994655
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2982231037
Short name T121
Test name
Test status
Simulation time 603893133 ps
CPU time 6.4 seconds
Started Jul 15 06:15:16 PM PDT 24
Finished Jul 15 06:15:23 PM PDT 24
Peak memory 204672 kb
Host smart-c68a03ce-79e1-4d0f-b0cc-7388d21031c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982231037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2982231037
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3890882228
Short name T399
Test name
Test status
Simulation time 168903567 ps
CPU time 3.75 seconds
Started Jul 15 06:15:15 PM PDT 24
Finished Jul 15 06:15:19 PM PDT 24
Peak memory 213204 kb
Host smart-5a5ef331-6c33-418c-8d40-806a74743f06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890882228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3890882228
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3219292574
Short name T178
Test name
Test status
Simulation time 3007313917 ps
CPU time 10.77 seconds
Started Jul 15 06:15:15 PM PDT 24
Finished Jul 15 06:15:27 PM PDT 24
Peak memory 213224 kb
Host smart-b41f8fd5-f468-470a-bcc4-d5ac816d64a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219292574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
219292574
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.890283162
Short name T312
Test name
Test status
Simulation time 2367410098 ps
CPU time 4.12 seconds
Started Jul 15 06:15:19 PM PDT 24
Finished Jul 15 06:15:24 PM PDT 24
Peak memory 219528 kb
Host smart-5017e024-cbad-42a6-871d-169aa466481d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890283162 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.890283162
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1971782555
Short name T108
Test name
Test status
Simulation time 122883937 ps
CPU time 2.3 seconds
Started Jul 15 06:15:16 PM PDT 24
Finished Jul 15 06:15:19 PM PDT 24
Peak memory 213156 kb
Host smart-ade9e2d2-ef9f-4890-b26a-95a73a012fda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971782555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1971782555
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2244712556
Short name T400
Test name
Test status
Simulation time 64810577821 ps
CPU time 93.05 seconds
Started Jul 15 06:15:16 PM PDT 24
Finished Jul 15 06:16:50 PM PDT 24
Peak memory 204948 kb
Host smart-c25ae713-ae36-4b05-b557-28e6398410c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244712556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2244712556
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4120190573
Short name T358
Test name
Test status
Simulation time 5333479963 ps
CPU time 4.6 seconds
Started Jul 15 06:15:16 PM PDT 24
Finished Jul 15 06:15:22 PM PDT 24
Peak memory 204668 kb
Host smart-73771971-238b-446b-97f8-35d8ebc647a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120190573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
4120190573
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1823566411
Short name T318
Test name
Test status
Simulation time 266232324 ps
CPU time 0.81 seconds
Started Jul 15 06:15:19 PM PDT 24
Finished Jul 15 06:15:20 PM PDT 24
Peak memory 204800 kb
Host smart-8baf11fc-2aad-4bb6-a208-7fcac37d9b56
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823566411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1823566411
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.4054817905
Short name T119
Test name
Test status
Simulation time 254999748 ps
CPU time 6.73 seconds
Started Jul 15 06:15:15 PM PDT 24
Finished Jul 15 06:15:23 PM PDT 24
Peak memory 204956 kb
Host smart-df1e5444-7494-4520-8c1c-13ce851544ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054817905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.4054817905
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2836664215
Short name T374
Test name
Test status
Simulation time 311653878 ps
CPU time 4.2 seconds
Started Jul 15 06:15:15 PM PDT 24
Finished Jul 15 06:15:20 PM PDT 24
Peak memory 213220 kb
Host smart-24e1515c-494e-46cb-bc25-44d4b181e7f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836664215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2836664215
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3515586083
Short name T372
Test name
Test status
Simulation time 1027286566 ps
CPU time 10.35 seconds
Started Jul 15 06:15:14 PM PDT 24
Finished Jul 15 06:15:25 PM PDT 24
Peak memory 213160 kb
Host smart-0983e0e1-be01-4930-90ac-696cc6ab1220
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515586083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
515586083
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3265756499
Short name T304
Test name
Test status
Simulation time 274395577 ps
CPU time 3.6 seconds
Started Jul 15 06:15:12 PM PDT 24
Finished Jul 15 06:15:16 PM PDT 24
Peak memory 217660 kb
Host smart-5defba73-e547-499c-a2e6-0ea1dfbb2891
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265756499 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3265756499
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4113482833
Short name T114
Test name
Test status
Simulation time 213241808 ps
CPU time 2.34 seconds
Started Jul 15 06:15:14 PM PDT 24
Finished Jul 15 06:15:18 PM PDT 24
Peak memory 213128 kb
Host smart-57d0f340-9c2d-4116-b43c-2ddb9b101e17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113482833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4113482833
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3584834685
Short name T428
Test name
Test status
Simulation time 75774735 ps
CPU time 0.8 seconds
Started Jul 15 06:15:15 PM PDT 24
Finished Jul 15 06:15:17 PM PDT 24
Peak memory 204804 kb
Host smart-2c841e79-5541-4a92-963e-1ffe63106c7e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584834685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.3584834685
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1861586894
Short name T440
Test name
Test status
Simulation time 1156177272 ps
CPU time 3.65 seconds
Started Jul 15 06:15:15 PM PDT 24
Finished Jul 15 06:15:20 PM PDT 24
Peak memory 204876 kb
Host smart-373470d0-91fb-4a0f-876e-974a9f9c582f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861586894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1861586894
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1992405401
Short name T82
Test name
Test status
Simulation time 156489903 ps
CPU time 0.75 seconds
Started Jul 15 06:15:13 PM PDT 24
Finished Jul 15 06:15:14 PM PDT 24
Peak memory 204812 kb
Host smart-d1d0be3e-1e88-4a17-a001-976976997fc6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992405401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1992405401
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2068051086
Short name T120
Test name
Test status
Simulation time 158745412 ps
CPU time 6.29 seconds
Started Jul 15 06:15:17 PM PDT 24
Finished Jul 15 06:15:24 PM PDT 24
Peak memory 204880 kb
Host smart-f0e43fee-2441-47b7-a7bd-4b6078df4d08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068051086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2068051086
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.793276751
Short name T360
Test name
Test status
Simulation time 761271794 ps
CPU time 5.3 seconds
Started Jul 15 06:15:11 PM PDT 24
Finished Jul 15 06:15:17 PM PDT 24
Peak memory 213248 kb
Host smart-80b814d6-47f4-473f-9602-3f6d61d71189
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793276751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.793276751
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3735931083
Short name T375
Test name
Test status
Simulation time 4694278931 ps
CPU time 12.7 seconds
Started Jul 15 06:15:14 PM PDT 24
Finished Jul 15 06:15:27 PM PDT 24
Peak memory 213104 kb
Host smart-cf692c46-2d59-4282-b0a6-659aba4fdfc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735931083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
735931083
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2740081401
Short name T351
Test name
Test status
Simulation time 545832561 ps
CPU time 2.49 seconds
Started Jul 15 06:15:21 PM PDT 24
Finished Jul 15 06:15:25 PM PDT 24
Peak memory 215216 kb
Host smart-38e109eb-e9cc-44b4-9c0a-d2cdf4266427
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740081401 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2740081401
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3188016623
Short name T93
Test name
Test status
Simulation time 419412641 ps
CPU time 2.49 seconds
Started Jul 15 06:15:20 PM PDT 24
Finished Jul 15 06:15:23 PM PDT 24
Peak memory 213148 kb
Host smart-ff47ceec-5da9-400c-bace-52e54edd352e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188016623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3188016623
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.653042695
Short name T329
Test name
Test status
Simulation time 28767951184 ps
CPU time 78.75 seconds
Started Jul 15 06:15:12 PM PDT 24
Finished Jul 15 06:16:31 PM PDT 24
Peak memory 204952 kb
Host smart-6b6cb9b3-7c56-4632-bbfe-3f0f03899225
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653042695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rv_dm_jtag_dmi_csr_bit_bash.653042695
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1487663835
Short name T412
Test name
Test status
Simulation time 1621710386 ps
CPU time 3.35 seconds
Started Jul 15 06:15:17 PM PDT 24
Finished Jul 15 06:15:21 PM PDT 24
Peak memory 204920 kb
Host smart-210722eb-82c6-46bc-9412-8849c1bd761e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487663835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1487663835
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1656561725
Short name T413
Test name
Test status
Simulation time 185649178 ps
CPU time 0.85 seconds
Started Jul 15 06:15:16 PM PDT 24
Finished Jul 15 06:15:18 PM PDT 24
Peak memory 204800 kb
Host smart-77c1a4f4-d741-41ef-82a8-8a71a795a30a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656561725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1656561725
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.511448394
Short name T90
Test name
Test status
Simulation time 468155353 ps
CPU time 7.25 seconds
Started Jul 15 06:15:19 PM PDT 24
Finished Jul 15 06:15:26 PM PDT 24
Peak memory 204896 kb
Host smart-6214f915-a2e9-43c5-8e36-c3396bef96cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511448394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_
csr_outstanding.511448394
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3746825164
Short name T410
Test name
Test status
Simulation time 565432967 ps
CPU time 3.26 seconds
Started Jul 15 06:15:13 PM PDT 24
Finished Jul 15 06:15:17 PM PDT 24
Peak memory 213188 kb
Host smart-f0526d5f-16aa-4e61-967c-1c002943d5d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746825164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3746825164
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2471560744
Short name T376
Test name
Test status
Simulation time 855993106 ps
CPU time 3.33 seconds
Started Jul 15 06:15:25 PM PDT 24
Finished Jul 15 06:15:29 PM PDT 24
Peak memory 216828 kb
Host smart-cc38087a-2520-4917-9de4-0f8115172c2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471560744 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2471560744
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2992057377
Short name T92
Test name
Test status
Simulation time 117802445 ps
CPU time 1.74 seconds
Started Jul 15 06:15:19 PM PDT 24
Finished Jul 15 06:15:22 PM PDT 24
Peak memory 212984 kb
Host smart-ceb61d86-ad68-4787-9f6a-a6885f1e109a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992057377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2992057377
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1194035116
Short name T367
Test name
Test status
Simulation time 3453273558 ps
CPU time 10.78 seconds
Started Jul 15 06:15:21 PM PDT 24
Finished Jul 15 06:15:33 PM PDT 24
Peak memory 204932 kb
Host smart-f04de091-2254-4edf-a66d-89463fba7bb3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194035116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.1194035116
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2012588631
Short name T403
Test name
Test status
Simulation time 1410662910 ps
CPU time 1.81 seconds
Started Jul 15 06:15:25 PM PDT 24
Finished Jul 15 06:15:27 PM PDT 24
Peak memory 204900 kb
Host smart-938e4599-147b-45bb-8686-7fd41a2aa335
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012588631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2012588631
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1201430779
Short name T314
Test name
Test status
Simulation time 348339931 ps
CPU time 0.76 seconds
Started Jul 15 06:15:22 PM PDT 24
Finished Jul 15 06:15:24 PM PDT 24
Peak memory 204772 kb
Host smart-56c74bf3-9a75-4c11-a9c9-3882b4ec17b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201430779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1201430779
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3830604451
Short name T377
Test name
Test status
Simulation time 550073803 ps
CPU time 4.04 seconds
Started Jul 15 06:15:20 PM PDT 24
Finished Jul 15 06:15:24 PM PDT 24
Peak memory 204900 kb
Host smart-e84205b1-13fd-4c4f-b19c-12a0ad9518f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830604451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3830604451
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2828029273
Short name T313
Test name
Test status
Simulation time 284598701 ps
CPU time 5.42 seconds
Started Jul 15 06:15:20 PM PDT 24
Finished Jul 15 06:15:26 PM PDT 24
Peak memory 213116 kb
Host smart-ba9d8509-f98f-4968-88e8-06859277bf3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828029273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2828029273
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.935557251
Short name T97
Test name
Test status
Simulation time 2233292879 ps
CPU time 17.8 seconds
Started Jul 15 06:15:20 PM PDT 24
Finished Jul 15 06:15:39 PM PDT 24
Peak memory 213100 kb
Host smart-b5cb4993-554a-4299-8d10-572d8fb32290
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935557251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.935557251
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1612993985
Short name T420
Test name
Test status
Simulation time 175965549 ps
CPU time 2.26 seconds
Started Jul 15 06:15:24 PM PDT 24
Finished Jul 15 06:15:27 PM PDT 24
Peak memory 217972 kb
Host smart-3bbae9a0-7e1b-487b-a3ad-116185a63b2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612993985 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1612993985
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2104965921
Short name T378
Test name
Test status
Simulation time 126553250 ps
CPU time 2.15 seconds
Started Jul 15 06:15:20 PM PDT 24
Finished Jul 15 06:15:23 PM PDT 24
Peak memory 213168 kb
Host smart-e3a80691-4786-41bb-8009-5846da178162
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104965921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2104965921
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1579322398
Short name T301
Test name
Test status
Simulation time 7545009737 ps
CPU time 6.37 seconds
Started Jul 15 06:15:21 PM PDT 24
Finished Jul 15 06:15:28 PM PDT 24
Peak memory 204980 kb
Host smart-1302caec-3d9e-4fd2-ac22-775523966204
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579322398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.1579322398
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2957696552
Short name T287
Test name
Test status
Simulation time 6849153512 ps
CPU time 18.81 seconds
Started Jul 15 06:15:18 PM PDT 24
Finished Jul 15 06:15:37 PM PDT 24
Peak memory 204940 kb
Host smart-c4ad78ec-84a2-4b0d-9c2f-3b81b858a3af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957696552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2957696552
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3499791144
Short name T317
Test name
Test status
Simulation time 644869652 ps
CPU time 1.16 seconds
Started Jul 15 06:15:21 PM PDT 24
Finished Jul 15 06:15:24 PM PDT 24
Peak memory 204820 kb
Host smart-4cafb5b5-189d-4a26-983f-42b3130c3897
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499791144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3499791144
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3412575087
Short name T431
Test name
Test status
Simulation time 1139567654 ps
CPU time 7.97 seconds
Started Jul 15 06:15:21 PM PDT 24
Finished Jul 15 06:15:30 PM PDT 24
Peak memory 204964 kb
Host smart-5feb118e-3192-446d-ba13-6d5219f6e466
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412575087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3412575087
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1122403320
Short name T175
Test name
Test status
Simulation time 89467639 ps
CPU time 4.35 seconds
Started Jul 15 06:15:22 PM PDT 24
Finished Jul 15 06:15:27 PM PDT 24
Peak memory 213216 kb
Host smart-b23073c5-de11-4993-9cc5-e4df83f136c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122403320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1122403320
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1080362688
Short name T62
Test name
Test status
Simulation time 2439038432 ps
CPU time 16.24 seconds
Started Jul 15 06:15:21 PM PDT 24
Finished Jul 15 06:15:39 PM PDT 24
Peak memory 213148 kb
Host smart-f73adfdc-f741-4d42-9af6-ebc6ef8bb603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080362688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
080362688
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3709448853
Short name T298
Test name
Test status
Simulation time 1254362495 ps
CPU time 4.92 seconds
Started Jul 15 06:15:20 PM PDT 24
Finished Jul 15 06:15:26 PM PDT 24
Peak memory 219828 kb
Host smart-bb29d8ea-2046-4dbb-ab7f-2859f58b2e0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709448853 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3709448853
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2693754118
Short name T116
Test name
Test status
Simulation time 232912903 ps
CPU time 2.42 seconds
Started Jul 15 06:15:26 PM PDT 24
Finished Jul 15 06:15:29 PM PDT 24
Peak memory 213120 kb
Host smart-f533b647-333e-4db2-9b11-f1d0a92bf267
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693754118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2693754118
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1822359628
Short name T406
Test name
Test status
Simulation time 5927397696 ps
CPU time 10.49 seconds
Started Jul 15 06:15:20 PM PDT 24
Finished Jul 15 06:15:31 PM PDT 24
Peak memory 204956 kb
Host smart-4076faf8-df83-41b1-bfc1-dbe3c25a6032
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822359628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.1822359628
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2102946573
Short name T292
Test name
Test status
Simulation time 5680270550 ps
CPU time 16.29 seconds
Started Jul 15 06:15:24 PM PDT 24
Finished Jul 15 06:15:41 PM PDT 24
Peak memory 205040 kb
Host smart-fdb3f96c-5be2-4afc-b89d-cb7e2ebfc0ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102946573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2102946573
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2949527488
Short name T434
Test name
Test status
Simulation time 165309696 ps
CPU time 0.78 seconds
Started Jul 15 06:15:23 PM PDT 24
Finished Jul 15 06:15:25 PM PDT 24
Peak memory 204772 kb
Host smart-4dd7eec5-d52a-4d13-93d8-38a5c441f49c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949527488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2949527488
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3630581313
Short name T385
Test name
Test status
Simulation time 703157416 ps
CPU time 5.98 seconds
Started Jul 15 06:15:22 PM PDT 24
Finished Jul 15 06:15:29 PM PDT 24
Peak memory 213160 kb
Host smart-a51adc43-17a4-4bb4-8119-82377ede37f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630581313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3630581313
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2541640411
Short name T181
Test name
Test status
Simulation time 5821388555 ps
CPU time 16.03 seconds
Started Jul 15 06:15:22 PM PDT 24
Finished Jul 15 06:15:39 PM PDT 24
Peak memory 212948 kb
Host smart-99f9465e-1b98-4a7d-acb3-07725c40c2ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541640411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
541640411
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4259990351
Short name T99
Test name
Test status
Simulation time 845607321 ps
CPU time 2.67 seconds
Started Jul 15 06:15:24 PM PDT 24
Finished Jul 15 06:15:28 PM PDT 24
Peak memory 216936 kb
Host smart-d5b47bc5-54f4-4def-bd7b-e733ab5b9fd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259990351 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.4259990351
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1972209033
Short name T347
Test name
Test status
Simulation time 412980276 ps
CPU time 2.45 seconds
Started Jul 15 06:15:24 PM PDT 24
Finished Jul 15 06:15:27 PM PDT 24
Peak memory 213156 kb
Host smart-7623cd92-8033-4d68-9f2c-abce924e0d85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972209033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1972209033
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.161046034
Short name T330
Test name
Test status
Simulation time 5881085192 ps
CPU time 5.48 seconds
Started Jul 15 06:15:26 PM PDT 24
Finished Jul 15 06:15:32 PM PDT 24
Peak memory 204612 kb
Host smart-364660ce-1b55-478d-99ce-7db2859ad7d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161046034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.161046034
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.159944372
Short name T426
Test name
Test status
Simulation time 1132679766 ps
CPU time 1.36 seconds
Started Jul 15 06:15:20 PM PDT 24
Finished Jul 15 06:15:23 PM PDT 24
Peak memory 204884 kb
Host smart-2c94797f-585c-4de2-8411-62e25610b268
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159944372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.159944372
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1455706889
Short name T395
Test name
Test status
Simulation time 615756347 ps
CPU time 0.9 seconds
Started Jul 15 06:15:19 PM PDT 24
Finished Jul 15 06:15:20 PM PDT 24
Peak memory 204784 kb
Host smart-f0d40e0c-2db2-4d89-a956-a6f4e973e7fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455706889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1455706889
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2503123369
Short name T414
Test name
Test status
Simulation time 233586463 ps
CPU time 4.24 seconds
Started Jul 15 06:15:24 PM PDT 24
Finished Jul 15 06:15:30 PM PDT 24
Peak memory 204980 kb
Host smart-6f65ab45-c796-456c-89e5-f909757ad549
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503123369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2503123369
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.986963853
Short name T335
Test name
Test status
Simulation time 7085381132 ps
CPU time 19.05 seconds
Started Jul 15 06:15:24 PM PDT 24
Finished Jul 15 06:15:44 PM PDT 24
Peak memory 213168 kb
Host smart-cec186ae-2fdb-4578-8841-55771adee799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986963853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.986963853
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2938196068
Short name T439
Test name
Test status
Simulation time 1187848593 ps
CPU time 67.02 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:16:02 PM PDT 24
Peak memory 213048 kb
Host smart-d4c2ea30-88e0-4068-b4c6-59904c17f32c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938196068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2938196068
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1269154422
Short name T408
Test name
Test status
Simulation time 2954856788 ps
CPU time 52.99 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:15:45 PM PDT 24
Peak memory 204984 kb
Host smart-210749d0-0475-4b88-abef-a5f8661d3d69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269154422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1269154422
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2802943250
Short name T94
Test name
Test status
Simulation time 304663133 ps
CPU time 1.77 seconds
Started Jul 15 06:14:57 PM PDT 24
Finished Jul 15 06:14:59 PM PDT 24
Peak memory 213156 kb
Host smart-826b9d75-d39b-4628-8967-cc6fd5d035f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802943250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2802943250
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3626518925
Short name T327
Test name
Test status
Simulation time 395792246 ps
CPU time 2.47 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:14:55 PM PDT 24
Peak memory 215308 kb
Host smart-a45be221-adde-4fae-a7e6-a01d665c2273
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626518925 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3626518925
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1487347403
Short name T95
Test name
Test status
Simulation time 1181045569 ps
CPU time 2.66 seconds
Started Jul 15 06:14:54 PM PDT 24
Finished Jul 15 06:14:59 PM PDT 24
Peak memory 213096 kb
Host smart-58e8ced3-5a25-4f56-b964-2d41e8e18bfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487347403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1487347403
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4219686703
Short name T288
Test name
Test status
Simulation time 91976287520 ps
CPU time 80.48 seconds
Started Jul 15 06:14:50 PM PDT 24
Finished Jul 15 06:16:12 PM PDT 24
Peak memory 204968 kb
Host smart-50a2a858-5a3d-40f8-97c9-e7684e18a522
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219686703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.4219686703
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.86055560
Short name T384
Test name
Test status
Simulation time 18798964636 ps
CPU time 21.78 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:15:14 PM PDT 24
Peak memory 205020 kb
Host smart-16542ba8-9416-4a06-bb0e-5ea057460828
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86055560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv
_dm_jtag_dmi_csr_bit_bash.86055560
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2538931070
Short name T305
Test name
Test status
Simulation time 4508919948 ps
CPU time 14.79 seconds
Started Jul 15 06:14:54 PM PDT 24
Finished Jul 15 06:15:10 PM PDT 24
Peak memory 204900 kb
Host smart-406d71c3-c451-4da6-ac4c-5ce583b21d81
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538931070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2538931070
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1079664320
Short name T300
Test name
Test status
Simulation time 4615627576 ps
CPU time 5.19 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:15:00 PM PDT 24
Peak memory 205020 kb
Host smart-d58eac7a-5ec6-4e9d-964b-85bd2636658f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079664320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
079664320
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.429242335
Short name T325
Test name
Test status
Simulation time 1604402337 ps
CPU time 2.84 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:14:58 PM PDT 24
Peak memory 204756 kb
Host smart-f620d855-ea8d-493b-858f-b165f5a86037
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429242335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.429242335
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.209670887
Short name T339
Test name
Test status
Simulation time 2479771380 ps
CPU time 3.2 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:14:59 PM PDT 24
Peak memory 204984 kb
Host smart-c7bf080b-e346-42c2-adfd-f1f69e1a446f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209670887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.209670887
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4091154795
Short name T371
Test name
Test status
Simulation time 472225975 ps
CPU time 0.82 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:14:56 PM PDT 24
Peak memory 204796 kb
Host smart-74a2d6c7-b6ab-419c-b3ba-5ec3d697aa96
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091154795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.4091154795
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2091296186
Short name T308
Test name
Test status
Simulation time 443872853 ps
CPU time 0.98 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:14:56 PM PDT 24
Peak memory 204820 kb
Host smart-fbc73b59-f632-49de-8c1b-6bbc5a934366
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091296186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
091296186
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.689549388
Short name T350
Test name
Test status
Simulation time 37564670 ps
CPU time 0.76 seconds
Started Jul 15 06:14:55 PM PDT 24
Finished Jul 15 06:14:57 PM PDT 24
Peak memory 204804 kb
Host smart-b85adb6f-a460-4a34-846e-0388c0930d16
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689549388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.689549388
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2370050105
Short name T364
Test name
Test status
Simulation time 133612637 ps
CPU time 0.74 seconds
Started Jul 15 06:14:54 PM PDT 24
Finished Jul 15 06:14:57 PM PDT 24
Peak memory 204808 kb
Host smart-47f299d2-87d1-4d38-9584-306d61079c16
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370050105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2370050105
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.608983657
Short name T113
Test name
Test status
Simulation time 176841851 ps
CPU time 6.18 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:15:01 PM PDT 24
Peak memory 204876 kb
Host smart-3329084b-af5f-458f-9526-69bc96503bfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608983657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.608983657
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2987225966
Short name T320
Test name
Test status
Simulation time 51352658399 ps
CPU time 42.82 seconds
Started Jul 15 06:14:52 PM PDT 24
Finished Jul 15 06:15:36 PM PDT 24
Peak memory 229616 kb
Host smart-672da7a2-0c97-4081-b745-a3c9544663a4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987225966 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2987225966
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2035930681
Short name T309
Test name
Test status
Simulation time 193509618 ps
CPU time 2.44 seconds
Started Jul 15 06:14:51 PM PDT 24
Finished Jul 15 06:14:54 PM PDT 24
Peak memory 213160 kb
Host smart-c4527a54-585b-4e37-b4b6-d34e713ad16e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035930681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2035930681
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.994311374
Short name T326
Test name
Test status
Simulation time 9424941571 ps
CPU time 34.39 seconds
Started Jul 15 06:14:59 PM PDT 24
Finished Jul 15 06:15:34 PM PDT 24
Peak memory 204884 kb
Host smart-5d9ca7db-0425-4270-b3b4-8825430b34c4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994311374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.994311374
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1304073627
Short name T429
Test name
Test status
Simulation time 30415497900 ps
CPU time 78.95 seconds
Started Jul 15 06:14:59 PM PDT 24
Finished Jul 15 06:16:20 PM PDT 24
Peak memory 213220 kb
Host smart-70594662-e8ab-43cb-a9fc-4f34a4f97609
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304073627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1304073627
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1388983440
Short name T109
Test name
Test status
Simulation time 103715165 ps
CPU time 1.69 seconds
Started Jul 15 06:14:55 PM PDT 24
Finished Jul 15 06:14:58 PM PDT 24
Peak memory 213168 kb
Host smart-c169f2f5-21d5-4690-b0d7-aa4d8ee936c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388983440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1388983440
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3961730894
Short name T331
Test name
Test status
Simulation time 3423770942 ps
CPU time 8.37 seconds
Started Jul 15 06:14:59 PM PDT 24
Finished Jul 15 06:15:09 PM PDT 24
Peak memory 221076 kb
Host smart-3c49718d-47c9-4bfc-867a-caddf764c9da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961730894 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3961730894
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.526215714
Short name T337
Test name
Test status
Simulation time 275905997 ps
CPU time 1.69 seconds
Started Jul 15 06:15:00 PM PDT 24
Finished Jul 15 06:15:03 PM PDT 24
Peak memory 213160 kb
Host smart-7b8f3bac-9f6e-4910-b797-7f77ffc3c77c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526215714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.526215714
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1523224877
Short name T432
Test name
Test status
Simulation time 157537562400 ps
CPU time 223.37 seconds
Started Jul 15 06:14:56 PM PDT 24
Finished Jul 15 06:18:41 PM PDT 24
Peak memory 206332 kb
Host smart-91580adc-05e5-4fd5-bd5c-04e60f2d1422
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523224877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1523224877
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4222739770
Short name T373
Test name
Test status
Simulation time 5135763682 ps
CPU time 8.7 seconds
Started Jul 15 06:14:55 PM PDT 24
Finished Jul 15 06:15:06 PM PDT 24
Peak memory 204948 kb
Host smart-70b91b9e-ee23-4f4a-a90b-dc39c58b4257
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222739770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.4222739770
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2052965868
Short name T101
Test name
Test status
Simulation time 2683740590 ps
CPU time 3.67 seconds
Started Jul 15 06:14:56 PM PDT 24
Finished Jul 15 06:15:01 PM PDT 24
Peak memory 205012 kb
Host smart-b28bfa09-e537-495e-9630-61d85d9fa667
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052965868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2052965868
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.367120417
Short name T345
Test name
Test status
Simulation time 5893390078 ps
CPU time 15.69 seconds
Started Jul 15 06:14:59 PM PDT 24
Finished Jul 15 06:15:16 PM PDT 24
Peak memory 205016 kb
Host smart-72f933d9-fe2d-4b4c-bf1c-74ee62540787
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367120417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.367120417
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4066337615
Short name T342
Test name
Test status
Simulation time 1107923873 ps
CPU time 3.7 seconds
Started Jul 15 06:14:56 PM PDT 24
Finished Jul 15 06:15:01 PM PDT 24
Peak memory 204772 kb
Host smart-ddaee068-5f2d-4910-9ace-8e70472bcd56
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066337615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.4066337615
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3527405002
Short name T421
Test name
Test status
Simulation time 3196901770 ps
CPU time 2.08 seconds
Started Jul 15 06:14:57 PM PDT 24
Finished Jul 15 06:15:00 PM PDT 24
Peak memory 204976 kb
Host smart-104d6d26-0803-4bd5-99c7-4a3623c1c668
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527405002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3527405002
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1364535051
Short name T397
Test name
Test status
Simulation time 337150458 ps
CPU time 0.82 seconds
Started Jul 15 06:14:53 PM PDT 24
Finished Jul 15 06:14:56 PM PDT 24
Peak memory 204804 kb
Host smart-941a5ff0-9973-427e-a3de-6ac3fd921e86
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364535051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1364535051
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.790849325
Short name T328
Test name
Test status
Simulation time 176994377 ps
CPU time 1.05 seconds
Started Jul 15 06:14:58 PM PDT 24
Finished Jul 15 06:15:00 PM PDT 24
Peak memory 204808 kb
Host smart-1d4768d5-1949-44d4-bdb9-9dde9572321f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790849325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.790849325
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3721823080
Short name T289
Test name
Test status
Simulation time 106725875 ps
CPU time 0.7 seconds
Started Jul 15 06:14:58 PM PDT 24
Finished Jul 15 06:15:00 PM PDT 24
Peak memory 204744 kb
Host smart-06008ade-c4fe-4b72-8cfb-316e42362edc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721823080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3721823080
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.944636195
Short name T433
Test name
Test status
Simulation time 143440389 ps
CPU time 0.84 seconds
Started Jul 15 06:14:56 PM PDT 24
Finished Jul 15 06:14:58 PM PDT 24
Peak memory 204764 kb
Host smart-0df9600f-b9fb-4361-a536-ac37bfc4c0f4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944636195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.944636195
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2990505532
Short name T430
Test name
Test status
Simulation time 571800568 ps
CPU time 6.84 seconds
Started Jul 15 06:14:56 PM PDT 24
Finished Jul 15 06:15:04 PM PDT 24
Peak memory 204956 kb
Host smart-efde049d-ed53-4e4f-92d1-a4bdc8d7569f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990505532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2990505532
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3988383695
Short name T332
Test name
Test status
Simulation time 37209531626 ps
CPU time 30.63 seconds
Started Jul 15 06:15:00 PM PDT 24
Finished Jul 15 06:15:32 PM PDT 24
Peak memory 221252 kb
Host smart-e04956d9-e453-47b1-a7db-faea3813e2f8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988383695 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3988383695
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3050401734
Short name T363
Test name
Test status
Simulation time 216066318 ps
CPU time 4.26 seconds
Started Jul 15 06:14:57 PM PDT 24
Finished Jul 15 06:15:02 PM PDT 24
Peak memory 213216 kb
Host smart-a46cf596-f66a-4d94-8730-4283d91aa844
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050401734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3050401734
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2438970371
Short name T179
Test name
Test status
Simulation time 2603407535 ps
CPU time 19.92 seconds
Started Jul 15 06:14:57 PM PDT 24
Finished Jul 15 06:15:18 PM PDT 24
Peak memory 213172 kb
Host smart-8be67d1a-0641-4453-9152-cb896179140b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438970371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2438970371
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4220190855
Short name T380
Test name
Test status
Simulation time 10288570003 ps
CPU time 65.51 seconds
Started Jul 15 06:15:00 PM PDT 24
Finished Jul 15 06:16:06 PM PDT 24
Peak memory 213216 kb
Host smart-41e9c9ba-db10-4232-92b0-b7030335024a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220190855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.4220190855
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1716128956
Short name T343
Test name
Test status
Simulation time 2544908062 ps
CPU time 3.38 seconds
Started Jul 15 06:15:00 PM PDT 24
Finished Jul 15 06:15:05 PM PDT 24
Peak memory 215876 kb
Host smart-8d472719-84e3-4965-97ee-fa0d8d99efa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716128956 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1716128956
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1571625736
Short name T66
Test name
Test status
Simulation time 133971547 ps
CPU time 1.64 seconds
Started Jul 15 06:14:57 PM PDT 24
Finished Jul 15 06:15:00 PM PDT 24
Peak memory 213008 kb
Host smart-45710260-6d72-4704-91a1-1bcaa613d178
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571625736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1571625736
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3045239565
Short name T366
Test name
Test status
Simulation time 14851932503 ps
CPU time 8.91 seconds
Started Jul 15 06:14:58 PM PDT 24
Finished Jul 15 06:15:08 PM PDT 24
Peak memory 205000 kb
Host smart-163f215c-a180-41a2-a679-7a08cb186b4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045239565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.3045239565
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3956957042
Short name T316
Test name
Test status
Simulation time 4395319615 ps
CPU time 4.88 seconds
Started Jul 15 06:15:02 PM PDT 24
Finished Jul 15 06:15:07 PM PDT 24
Peak memory 205024 kb
Host smart-dfcf1447-afca-4591-a34f-83f0d0fac017
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956957042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.3956957042
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2712958995
Short name T102
Test name
Test status
Simulation time 3473896125 ps
CPU time 11.05 seconds
Started Jul 15 06:14:56 PM PDT 24
Finished Jul 15 06:15:09 PM PDT 24
Peak memory 205028 kb
Host smart-ab1b24ee-924d-4ef1-9a0e-52e9394b4758
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712958995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2712958995
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3028082810
Short name T370
Test name
Test status
Simulation time 5678376151 ps
CPU time 7.58 seconds
Started Jul 15 06:14:59 PM PDT 24
Finished Jul 15 06:15:07 PM PDT 24
Peak memory 204924 kb
Host smart-f061d330-07ae-4b8b-bb63-48607214d267
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028082810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
028082810
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.99469496
Short name T295
Test name
Test status
Simulation time 470017184 ps
CPU time 1.06 seconds
Started Jul 15 06:14:58 PM PDT 24
Finished Jul 15 06:15:00 PM PDT 24
Peak memory 204788 kb
Host smart-38a5df25-79ce-4105-a136-e2deb72b8079
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99469496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_
aliasing.99469496
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.574576272
Short name T424
Test name
Test status
Simulation time 12907742375 ps
CPU time 11.62 seconds
Started Jul 15 06:14:56 PM PDT 24
Finished Jul 15 06:15:09 PM PDT 24
Peak memory 204960 kb
Host smart-31e2c1c4-0fa3-4a23-856d-9b1f877fe44c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574576272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.574576272
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.61643876
Short name T81
Test name
Test status
Simulation time 267933439 ps
CPU time 1.4 seconds
Started Jul 15 06:14:56 PM PDT 24
Finished Jul 15 06:14:59 PM PDT 24
Peak memory 204824 kb
Host smart-b89ff65b-da16-49ca-9770-71b528fd379d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61643876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_
hw_reset.61643876
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1615954618
Short name T340
Test name
Test status
Simulation time 162271501 ps
CPU time 1.1 seconds
Started Jul 15 06:14:58 PM PDT 24
Finished Jul 15 06:15:00 PM PDT 24
Peak memory 204824 kb
Host smart-2fe6bb14-1de7-489c-acda-4c86874af5f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615954618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
615954618
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.683977661
Short name T386
Test name
Test status
Simulation time 92801197 ps
CPU time 0.75 seconds
Started Jul 15 06:14:58 PM PDT 24
Finished Jul 15 06:15:00 PM PDT 24
Peak memory 204768 kb
Host smart-4d224836-98b0-40a2-991c-22ede7db477b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683977661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.683977661
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.396923717
Short name T359
Test name
Test status
Simulation time 51642521 ps
CPU time 0.69 seconds
Started Jul 15 06:14:57 PM PDT 24
Finished Jul 15 06:14:59 PM PDT 24
Peak memory 204828 kb
Host smart-805a1067-4cf7-4656-a20a-d318f11cd654
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396923717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.396923717
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1385232627
Short name T407
Test name
Test status
Simulation time 166495149 ps
CPU time 3.96 seconds
Started Jul 15 06:14:58 PM PDT 24
Finished Jul 15 06:15:03 PM PDT 24
Peak memory 205000 kb
Host smart-581468bb-54b5-45bd-ae0e-28f0cab301a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385232627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1385232627
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2947997110
Short name T417
Test name
Test status
Simulation time 80230334 ps
CPU time 3.48 seconds
Started Jul 15 06:14:59 PM PDT 24
Finished Jul 15 06:15:04 PM PDT 24
Peak memory 213152 kb
Host smart-ad910df1-1878-4ec7-bddc-5de9d557f681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947997110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2947997110
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2274573272
Short name T435
Test name
Test status
Simulation time 832215390 ps
CPU time 10.29 seconds
Started Jul 15 06:15:00 PM PDT 24
Finished Jul 15 06:15:12 PM PDT 24
Peak memory 212968 kb
Host smart-91a5c530-b766-473c-a2c9-065fe0380634
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274573272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2274573272
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3946029862
Short name T338
Test name
Test status
Simulation time 4552075265 ps
CPU time 4.42 seconds
Started Jul 15 06:14:58 PM PDT 24
Finished Jul 15 06:15:04 PM PDT 24
Peak memory 218604 kb
Host smart-afc9d781-fc3f-43ff-8dbf-8e48db7c53f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946029862 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3946029862
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.93425505
Short name T96
Test name
Test status
Simulation time 157412129 ps
CPU time 2.46 seconds
Started Jul 15 06:14:58 PM PDT 24
Finished Jul 15 06:15:02 PM PDT 24
Peak memory 213156 kb
Host smart-81a73e40-0625-4b24-8135-1c02b04e1ea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93425505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.93425505
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3959754949
Short name T418
Test name
Test status
Simulation time 22824581913 ps
CPU time 16.69 seconds
Started Jul 15 06:14:58 PM PDT 24
Finished Jul 15 06:15:15 PM PDT 24
Peak memory 204940 kb
Host smart-0c8d5994-0722-4ba3-8df5-3b89f50c2417
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959754949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3959754949
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1827801916
Short name T286
Test name
Test status
Simulation time 5135160722 ps
CPU time 8.22 seconds
Started Jul 15 06:14:58 PM PDT 24
Finished Jul 15 06:15:07 PM PDT 24
Peak memory 204920 kb
Host smart-ce7d5223-0e0a-407a-a9b5-5c1dca30855f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827801916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
827801916
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3654827303
Short name T357
Test name
Test status
Simulation time 629468513 ps
CPU time 1.38 seconds
Started Jul 15 06:14:58 PM PDT 24
Finished Jul 15 06:15:00 PM PDT 24
Peak memory 204696 kb
Host smart-85162d9a-4371-46d5-a238-233f6560e820
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654827303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
654827303
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1322834149
Short name T111
Test name
Test status
Simulation time 879737889 ps
CPU time 7.69 seconds
Started Jul 15 06:14:57 PM PDT 24
Finished Jul 15 06:15:06 PM PDT 24
Peak memory 204904 kb
Host smart-ce90eab1-3a96-4d5f-a74f-370a88f0d94b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322834149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1322834149
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4014121633
Short name T402
Test name
Test status
Simulation time 1263542466 ps
CPU time 5.21 seconds
Started Jul 15 06:14:57 PM PDT 24
Finished Jul 15 06:15:04 PM PDT 24
Peak memory 213164 kb
Host smart-cfdd4439-c95b-4abd-b8b3-544873a782d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014121633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.4014121633
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2474433541
Short name T311
Test name
Test status
Simulation time 7743603397 ps
CPU time 14.47 seconds
Started Jul 15 06:14:59 PM PDT 24
Finished Jul 15 06:15:15 PM PDT 24
Peak memory 213164 kb
Host smart-629de909-0930-4361-89f3-12c835b7602d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474433541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2474433541
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2172768521
Short name T390
Test name
Test status
Simulation time 4216473183 ps
CPU time 6.54 seconds
Started Jul 15 06:15:08 PM PDT 24
Finished Jul 15 06:15:16 PM PDT 24
Peak memory 220984 kb
Host smart-fda8aae3-f414-4512-876f-c5d729ac65fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172768521 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2172768521
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2210429376
Short name T123
Test name
Test status
Simulation time 163959626 ps
CPU time 2.15 seconds
Started Jul 15 06:15:05 PM PDT 24
Finished Jul 15 06:15:08 PM PDT 24
Peak memory 213160 kb
Host smart-848a5c3a-dbea-41f8-a864-a896ac8a4dbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210429376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2210429376
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.740232231
Short name T315
Test name
Test status
Simulation time 5491118408 ps
CPU time 8.35 seconds
Started Jul 15 06:14:59 PM PDT 24
Finished Jul 15 06:15:09 PM PDT 24
Peak memory 205008 kb
Host smart-66476ea1-682e-4ce9-8616-c116260abdc0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740232231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
v_dm_jtag_dmi_csr_bit_bash.740232231
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3919882087
Short name T302
Test name
Test status
Simulation time 1202335376 ps
CPU time 1.13 seconds
Started Jul 15 06:14:59 PM PDT 24
Finished Jul 15 06:15:02 PM PDT 24
Peak memory 204920 kb
Host smart-7464e72a-e7e2-473b-8d35-470954f23204
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919882087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
919882087
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1292280643
Short name T427
Test name
Test status
Simulation time 251299914 ps
CPU time 0.73 seconds
Started Jul 15 06:15:00 PM PDT 24
Finished Jul 15 06:15:02 PM PDT 24
Peak memory 204776 kb
Host smart-3ccff68b-194f-4f88-965d-94896f812d29
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292280643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
292280643
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2513650635
Short name T387
Test name
Test status
Simulation time 1666500352 ps
CPU time 7.6 seconds
Started Jul 15 06:15:05 PM PDT 24
Finished Jul 15 06:15:13 PM PDT 24
Peak memory 204984 kb
Host smart-bfbb8144-4c1f-46ef-9511-7a2838b34afd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513650635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2513650635
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.247596051
Short name T404
Test name
Test status
Simulation time 29200576294 ps
CPU time 50.54 seconds
Started Jul 15 06:15:00 PM PDT 24
Finished Jul 15 06:15:52 PM PDT 24
Peak memory 221360 kb
Host smart-dcb487a1-1de2-46ea-8ac8-aef86adc77b1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247596051 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.247596051
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2089112361
Short name T436
Test name
Test status
Simulation time 187601887 ps
CPU time 4.76 seconds
Started Jul 15 06:14:59 PM PDT 24
Finished Jul 15 06:15:06 PM PDT 24
Peak memory 213184 kb
Host smart-d16b3afe-6fa7-455d-9dfa-6c48f5f8b3c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089112361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2089112361
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1508397552
Short name T388
Test name
Test status
Simulation time 3555507067 ps
CPU time 9.1 seconds
Started Jul 15 06:15:06 PM PDT 24
Finished Jul 15 06:15:17 PM PDT 24
Peak memory 213188 kb
Host smart-c1f04481-15c1-4fd1-b4db-5066b6b030cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508397552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1508397552
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2210104759
Short name T422
Test name
Test status
Simulation time 4232233010 ps
CPU time 5.61 seconds
Started Jul 15 06:15:04 PM PDT 24
Finished Jul 15 06:15:11 PM PDT 24
Peak memory 218244 kb
Host smart-6564b632-3156-4975-b011-290693130878
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210104759 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2210104759
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3502604033
Short name T117
Test name
Test status
Simulation time 187390748 ps
CPU time 2.54 seconds
Started Jul 15 06:15:07 PM PDT 24
Finished Jul 15 06:15:10 PM PDT 24
Peak memory 213092 kb
Host smart-769946ea-4f82-4565-bfe9-4c997c8fc27d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502604033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3502604033
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2469866522
Short name T381
Test name
Test status
Simulation time 3945339396 ps
CPU time 6.42 seconds
Started Jul 15 06:15:08 PM PDT 24
Finished Jul 15 06:15:15 PM PDT 24
Peak memory 205020 kb
Host smart-159387c1-ff9d-4083-a345-3736d1b01877
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469866522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2469866522
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2852390088
Short name T341
Test name
Test status
Simulation time 1134380920 ps
CPU time 3.78 seconds
Started Jul 15 06:15:06 PM PDT 24
Finished Jul 15 06:15:11 PM PDT 24
Peak memory 204828 kb
Host smart-cbfee020-b183-4933-9347-4a173333d494
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852390088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
852390088
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1268071220
Short name T310
Test name
Test status
Simulation time 186893742 ps
CPU time 1.09 seconds
Started Jul 15 06:15:08 PM PDT 24
Finished Jul 15 06:15:10 PM PDT 24
Peak memory 204800 kb
Host smart-cf631af2-480d-4e3f-b57b-869c26ae06ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268071220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
268071220
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.148483849
Short name T107
Test name
Test status
Simulation time 543426395 ps
CPU time 6.34 seconds
Started Jul 15 06:15:06 PM PDT 24
Finished Jul 15 06:15:14 PM PDT 24
Peak memory 204944 kb
Host smart-1b5df097-09dd-4068-ae22-aad6fd352cf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148483849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.148483849
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1533844528
Short name T78
Test name
Test status
Simulation time 33818414160 ps
CPU time 30.99 seconds
Started Jul 15 06:15:07 PM PDT 24
Finished Jul 15 06:15:39 PM PDT 24
Peak memory 221368 kb
Host smart-ee536703-b7b0-4a13-b8ad-5b0a920c3cc9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533844528 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1533844528
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2571067084
Short name T401
Test name
Test status
Simulation time 237111635 ps
CPU time 4.32 seconds
Started Jul 15 06:15:05 PM PDT 24
Finished Jul 15 06:15:10 PM PDT 24
Peak memory 213176 kb
Host smart-468dd020-f4a9-456a-bf15-dd342183c12d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571067084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2571067084
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1575365870
Short name T307
Test name
Test status
Simulation time 4580762093 ps
CPU time 10.66 seconds
Started Jul 15 06:15:05 PM PDT 24
Finished Jul 15 06:15:16 PM PDT 24
Peak memory 213192 kb
Host smart-6f1f4685-9ff4-47d2-b481-2a24e0f04f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575365870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1575365870
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3567212199
Short name T88
Test name
Test status
Simulation time 2254233781 ps
CPU time 5.95 seconds
Started Jul 15 06:15:06 PM PDT 24
Finished Jul 15 06:15:13 PM PDT 24
Peak memory 219580 kb
Host smart-4645849d-2dc1-4857-aaf0-bee17bbf367e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567212199 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3567212199
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1619579505
Short name T334
Test name
Test status
Simulation time 999358153 ps
CPU time 1.81 seconds
Started Jul 15 06:15:06 PM PDT 24
Finished Jul 15 06:15:09 PM PDT 24
Peak memory 213072 kb
Host smart-e73d3239-0dcd-47e5-9964-ce168f143106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619579505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1619579505
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4152000077
Short name T355
Test name
Test status
Simulation time 44999122666 ps
CPU time 38.83 seconds
Started Jul 15 06:15:07 PM PDT 24
Finished Jul 15 06:15:47 PM PDT 24
Peak memory 204940 kb
Host smart-6578eaf1-b82a-4a10-9117-38bd083ce2f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152000077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.4152000077
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1924422043
Short name T303
Test name
Test status
Simulation time 5244608297 ps
CPU time 3.97 seconds
Started Jul 15 06:15:07 PM PDT 24
Finished Jul 15 06:15:12 PM PDT 24
Peak memory 205016 kb
Host smart-21c88f7a-9774-4e6c-80c1-10a9b96d2f21
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924422043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
924422043
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3596166403
Short name T416
Test name
Test status
Simulation time 141804959 ps
CPU time 1.11 seconds
Started Jul 15 06:15:04 PM PDT 24
Finished Jul 15 06:15:05 PM PDT 24
Peak memory 204736 kb
Host smart-68989a29-8acc-4875-8dfe-c08205be9d93
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596166403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
596166403
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1187293894
Short name T382
Test name
Test status
Simulation time 1872638308 ps
CPU time 7.55 seconds
Started Jul 15 06:15:05 PM PDT 24
Finished Jul 15 06:15:13 PM PDT 24
Peak memory 204996 kb
Host smart-dcbe68e4-8bb1-4a2d-9a19-0a230e3e541d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187293894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1187293894
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3744846933
Short name T79
Test name
Test status
Simulation time 41257414806 ps
CPU time 35.76 seconds
Started Jul 15 06:15:07 PM PDT 24
Finished Jul 15 06:15:44 PM PDT 24
Peak memory 216920 kb
Host smart-11451f74-587b-4ef8-a9b7-5f87b842998e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744846933 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3744846933
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3665449336
Short name T64
Test name
Test status
Simulation time 131681569 ps
CPU time 2.3 seconds
Started Jul 15 06:15:06 PM PDT 24
Finished Jul 15 06:15:10 PM PDT 24
Peak memory 213164 kb
Host smart-b945c8fa-c3dd-42eb-8461-bc1d61770aa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665449336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3665449336
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4080182481
Short name T396
Test name
Test status
Simulation time 4117719546 ps
CPU time 6.67 seconds
Started Jul 15 06:15:07 PM PDT 24
Finished Jul 15 06:15:15 PM PDT 24
Peak memory 221496 kb
Host smart-c965a1f0-b421-48dd-bfbd-84a827611075
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080182481 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.4080182481
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1445259376
Short name T409
Test name
Test status
Simulation time 243872045 ps
CPU time 1.4 seconds
Started Jul 15 06:15:06 PM PDT 24
Finished Jul 15 06:15:08 PM PDT 24
Peak memory 213064 kb
Host smart-a9d2524a-1a5a-4194-8acd-dc043bbb697a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445259376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1445259376
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.495093447
Short name T394
Test name
Test status
Simulation time 38278052937 ps
CPU time 102.66 seconds
Started Jul 15 06:15:05 PM PDT 24
Finished Jul 15 06:16:48 PM PDT 24
Peak memory 204972 kb
Host smart-3a357583-f940-4ee1-b6c2-091ace861607
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495093447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r
v_dm_jtag_dmi_csr_bit_bash.495093447
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3206684597
Short name T293
Test name
Test status
Simulation time 2893390775 ps
CPU time 9.15 seconds
Started Jul 15 06:15:06 PM PDT 24
Finished Jul 15 06:15:16 PM PDT 24
Peak memory 204940 kb
Host smart-5944cf01-e70a-4406-ac1f-2703ef0d7ef4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206684597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
206684597
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1262253553
Short name T323
Test name
Test status
Simulation time 78010677 ps
CPU time 0.85 seconds
Started Jul 15 06:15:07 PM PDT 24
Finished Jul 15 06:15:09 PM PDT 24
Peak memory 204808 kb
Host smart-59b7728c-5c3a-4b52-8563-a61a268a0002
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262253553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
262253553
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.717492848
Short name T425
Test name
Test status
Simulation time 641687454 ps
CPU time 6.42 seconds
Started Jul 15 06:15:08 PM PDT 24
Finished Jul 15 06:15:15 PM PDT 24
Peak memory 204956 kb
Host smart-c554e74e-03fe-4e14-b8ab-17b2a4dcd498
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717492848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.717492848
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3984366179
Short name T239
Test name
Test status
Simulation time 755075446 ps
CPU time 6.24 seconds
Started Jul 15 06:15:08 PM PDT 24
Finished Jul 15 06:15:15 PM PDT 24
Peak memory 213212 kb
Host smart-64e31239-ff13-4192-a26e-57d9c7da4f9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984366179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3984366179
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3217017445
Short name T306
Test name
Test status
Simulation time 7021636404 ps
CPU time 18.56 seconds
Started Jul 15 06:15:03 PM PDT 24
Finished Jul 15 06:15:22 PM PDT 24
Peak memory 213204 kb
Host smart-0e58d56f-ea72-4f04-9aa3-9480cd0f89cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217017445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3217017445
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.1721512128
Short name T37
Test name
Test status
Simulation time 334350369 ps
CPU time 1.12 seconds
Started Jul 15 06:21:11 PM PDT 24
Finished Jul 15 06:21:13 PM PDT 24
Peak memory 204828 kb
Host smart-e725645b-93f3-4260-8739-38a9cd2c9f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721512128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.1721512128
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.67571346
Short name T254
Test name
Test status
Simulation time 35764100 ps
CPU time 0.76 seconds
Started Jul 15 06:21:10 PM PDT 24
Finished Jul 15 06:21:12 PM PDT 24
Peak memory 204788 kb
Host smart-13214c3a-f857-4c14-8425-7253c3310714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67571346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.67571346
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2366220030
Short name T283
Test name
Test status
Simulation time 225457025 ps
CPU time 1.03 seconds
Started Jul 15 06:20:56 PM PDT 24
Finished Jul 15 06:20:58 PM PDT 24
Peak memory 204856 kb
Host smart-4299617b-9fb3-4c25-b7dc-ca1ed005b57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366220030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2366220030
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2160920920
Short name T237
Test name
Test status
Simulation time 504633608 ps
CPU time 0.95 seconds
Started Jul 15 06:20:56 PM PDT 24
Finished Jul 15 06:20:58 PM PDT 24
Peak memory 204864 kb
Host smart-46d96e36-7480-46b1-aac0-437fe87b7ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160920920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2160920920
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.456363634
Short name T219
Test name
Test status
Simulation time 141678235 ps
CPU time 0.87 seconds
Started Jul 15 06:21:02 PM PDT 24
Finished Jul 15 06:21:04 PM PDT 24
Peak memory 204796 kb
Host smart-efee7f31-33bf-4a58-8714-0fd8bbcf55e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456363634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.456363634
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.3241148179
Short name T60
Test name
Test status
Simulation time 185938700 ps
CPU time 0.86 seconds
Started Jul 15 06:21:09 PM PDT 24
Finished Jul 15 06:21:11 PM PDT 24
Peak memory 215340 kb
Host smart-813b4d80-04c6-498d-afd5-941a83b26c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241148179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3241148179
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2464401697
Short name T162
Test name
Test status
Simulation time 5970173456 ps
CPU time 5.55 seconds
Started Jul 15 06:20:59 PM PDT 24
Finished Jul 15 06:21:05 PM PDT 24
Peak memory 213300 kb
Host smart-df36a6cc-70fb-47ce-b99a-b7fcc09d1cb8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464401697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2464401697
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2259464833
Short name T182
Test name
Test status
Simulation time 270287941 ps
CPU time 1.47 seconds
Started Jul 15 06:21:02 PM PDT 24
Finished Jul 15 06:21:04 PM PDT 24
Peak memory 204828 kb
Host smart-ab5ae833-360a-4739-90be-10d6be8bafc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259464833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2259464833
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1391388338
Short name T253
Test name
Test status
Simulation time 283841787 ps
CPU time 1.27 seconds
Started Jul 15 06:21:03 PM PDT 24
Finished Jul 15 06:21:05 PM PDT 24
Peak memory 204788 kb
Host smart-b96a21f5-91f8-40d1-b973-7b5ce095d3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391388338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1391388338
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2250971704
Short name T271
Test name
Test status
Simulation time 734356375 ps
CPU time 1.06 seconds
Started Jul 15 06:21:02 PM PDT 24
Finished Jul 15 06:21:04 PM PDT 24
Peak memory 204844 kb
Host smart-2f7bb017-f729-4b39-958d-61018026839e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250971704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2250971704
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.543860176
Short name T265
Test name
Test status
Simulation time 1867726227 ps
CPU time 5.14 seconds
Started Jul 15 06:21:02 PM PDT 24
Finished Jul 15 06:21:08 PM PDT 24
Peak memory 204816 kb
Host smart-897acbcc-0c0b-4e1e-921e-08dfa398d573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543860176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.543860176
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3607254649
Short name T285
Test name
Test status
Simulation time 688567862 ps
CPU time 1.21 seconds
Started Jul 15 06:21:02 PM PDT 24
Finished Jul 15 06:21:04 PM PDT 24
Peak memory 204852 kb
Host smart-4d34cbf2-7e74-4abf-bf75-bc6ceed52140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607254649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3607254649
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3338559208
Short name T185
Test name
Test status
Simulation time 212325710 ps
CPU time 1.29 seconds
Started Jul 15 06:20:56 PM PDT 24
Finished Jul 15 06:20:58 PM PDT 24
Peak memory 204812 kb
Host smart-9cb75440-374b-4593-adda-f4b8afcac320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338559208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3338559208
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1261536049
Short name T259
Test name
Test status
Simulation time 150045984 ps
CPU time 1.02 seconds
Started Jul 15 06:20:56 PM PDT 24
Finished Jul 15 06:20:58 PM PDT 24
Peak memory 204844 kb
Host smart-20038223-386b-4557-8a8f-6171a0941245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261536049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1261536049
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.4067392423
Short name T49
Test name
Test status
Simulation time 180239576 ps
CPU time 1.03 seconds
Started Jul 15 06:21:02 PM PDT 24
Finished Jul 15 06:21:04 PM PDT 24
Peak memory 213040 kb
Host smart-fe24b586-2d7d-46cb-83ab-54fa328771b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067392423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.4067392423
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3761484608
Short name T31
Test name
Test status
Simulation time 40181476 ps
CPU time 0.83 seconds
Started Jul 15 06:21:10 PM PDT 24
Finished Jul 15 06:21:11 PM PDT 24
Peak memory 213124 kb
Host smart-7c0aca5c-c35a-4de3-b16b-8bf0829ca05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761484608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3761484608
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3059444486
Short name T40
Test name
Test status
Simulation time 1901369355 ps
CPU time 3.06 seconds
Started Jul 15 06:20:51 PM PDT 24
Finished Jul 15 06:20:55 PM PDT 24
Peak memory 204868 kb
Host smart-82f77a1b-638c-4418-8837-0b923d1cd353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059444486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3059444486
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1657630337
Short name T220
Test name
Test status
Simulation time 103678381 ps
CPU time 0.74 seconds
Started Jul 15 06:21:29 PM PDT 24
Finished Jul 15 06:21:30 PM PDT 24
Peak memory 204852 kb
Host smart-60277058-288a-4268-95ad-52f2348abbb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657630337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1657630337
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2079177756
Short name T148
Test name
Test status
Simulation time 6762700910 ps
CPU time 3.34 seconds
Started Jul 15 06:21:09 PM PDT 24
Finished Jul 15 06:21:13 PM PDT 24
Peak memory 213316 kb
Host smart-2460e8f9-ce9f-4efa-8872-3d7ca20edc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079177756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2079177756
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.951633811
Short name T187
Test name
Test status
Simulation time 233985602 ps
CPU time 1.13 seconds
Started Jul 15 06:21:16 PM PDT 24
Finished Jul 15 06:21:18 PM PDT 24
Peak memory 204812 kb
Host smart-f2f78f53-a93d-47f3-8b9f-60ec7e0f77ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951633811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.951633811
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2486935818
Short name T16
Test name
Test status
Simulation time 1701645264 ps
CPU time 5.2 seconds
Started Jul 15 06:21:18 PM PDT 24
Finished Jul 15 06:21:23 PM PDT 24
Peak memory 204832 kb
Host smart-964b7a87-fc08-47f0-b55c-76ee22cadb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486935818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2486935818
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1770632845
Short name T28
Test name
Test status
Simulation time 279360391 ps
CPU time 1.38 seconds
Started Jul 15 06:21:18 PM PDT 24
Finished Jul 15 06:21:20 PM PDT 24
Peak memory 204792 kb
Host smart-56183473-ed00-4f82-8c24-03117f3399dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770632845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1770632845
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2845809321
Short name T234
Test name
Test status
Simulation time 717387097 ps
CPU time 2.22 seconds
Started Jul 15 06:21:22 PM PDT 24
Finished Jul 15 06:21:25 PM PDT 24
Peak memory 204792 kb
Host smart-9363e2ab-025a-4d38-b28b-aa80358b1ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845809321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2845809321
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.4183497653
Short name T188
Test name
Test status
Simulation time 108535724 ps
CPU time 0.74 seconds
Started Jul 15 06:21:17 PM PDT 24
Finished Jul 15 06:21:18 PM PDT 24
Peak memory 204816 kb
Host smart-f91513de-f177-45a0-88d4-6a157b3d084d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183497653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.4183497653
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3201041622
Short name T41
Test name
Test status
Simulation time 1536347769 ps
CPU time 3.18 seconds
Started Jul 15 06:21:10 PM PDT 24
Finished Jul 15 06:21:13 PM PDT 24
Peak memory 213276 kb
Host smart-810f0ed9-9fc5-4e0c-a91a-cde232d085e7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201041622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3201041622
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.30884908
Short name T45
Test name
Test status
Simulation time 628171365 ps
CPU time 0.77 seconds
Started Jul 15 06:21:22 PM PDT 24
Finished Jul 15 06:21:23 PM PDT 24
Peak memory 204828 kb
Host smart-a44bdfb5-763b-46cb-90ed-29fa8043c8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30884908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.30884908
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1350273751
Short name T184
Test name
Test status
Simulation time 824646608 ps
CPU time 2.98 seconds
Started Jul 15 06:21:16 PM PDT 24
Finished Jul 15 06:21:19 PM PDT 24
Peak memory 204872 kb
Host smart-33e78baf-f939-403f-824e-607546ab19a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350273751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1350273751
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1016725035
Short name T131
Test name
Test status
Simulation time 252432609 ps
CPU time 1 seconds
Started Jul 15 06:21:20 PM PDT 24
Finished Jul 15 06:21:22 PM PDT 24
Peak memory 204812 kb
Host smart-5fbd97e9-42fe-4bea-a138-b31aa2343a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016725035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1016725035
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.646864850
Short name T47
Test name
Test status
Simulation time 729109469 ps
CPU time 1.84 seconds
Started Jul 15 06:21:23 PM PDT 24
Finished Jul 15 06:21:25 PM PDT 24
Peak memory 204840 kb
Host smart-a1ddddf1-77f2-426e-b38e-852d56a78c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646864850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.646864850
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2282689965
Short name T266
Test name
Test status
Simulation time 1031810941 ps
CPU time 3.39 seconds
Started Jul 15 06:21:25 PM PDT 24
Finished Jul 15 06:21:28 PM PDT 24
Peak memory 204788 kb
Host smart-17065815-b019-4e92-8b55-7fb94bdc029c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282689965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2282689965
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2188739367
Short name T74
Test name
Test status
Simulation time 1344923561 ps
CPU time 2.03 seconds
Started Jul 15 06:21:26 PM PDT 24
Finished Jul 15 06:21:28 PM PDT 24
Peak memory 204672 kb
Host smart-5d95a0e6-0a59-44fd-9e0e-4ce15d9c2b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188739367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2188739367
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.125745222
Short name T246
Test name
Test status
Simulation time 108469846 ps
CPU time 0.88 seconds
Started Jul 15 06:21:24 PM PDT 24
Finished Jul 15 06:21:25 PM PDT 24
Peak memory 204788 kb
Host smart-4c335fb6-6207-4bdd-b269-07e9db85561d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125745222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.125745222
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.4127314918
Short name T183
Test name
Test status
Simulation time 402289586 ps
CPU time 1.66 seconds
Started Jul 15 06:21:15 PM PDT 24
Finished Jul 15 06:21:17 PM PDT 24
Peak memory 204856 kb
Host smart-0023a205-e200-45ec-aa05-edef30edd3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127314918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.4127314918
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3723631901
Short name T264
Test name
Test status
Simulation time 3661402639 ps
CPU time 5.53 seconds
Started Jul 15 06:21:18 PM PDT 24
Finished Jul 15 06:21:24 PM PDT 24
Peak memory 204892 kb
Host smart-0b5932f9-c15c-46d0-bb3f-ab8158e950e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723631901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3723631901
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.163466316
Short name T190
Test name
Test status
Simulation time 781312628 ps
CPU time 2.68 seconds
Started Jul 15 06:21:18 PM PDT 24
Finished Jul 15 06:21:21 PM PDT 24
Peak memory 212980 kb
Host smart-26c072e9-d145-48fe-80d3-e2759588d9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163466316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.163466316
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3858331912
Short name T4
Test name
Test status
Simulation time 1893690864 ps
CPU time 5.91 seconds
Started Jul 15 06:21:22 PM PDT 24
Finished Jul 15 06:21:29 PM PDT 24
Peak memory 204924 kb
Host smart-3ee1258a-f4a3-4b09-b85c-d67de9a40e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858331912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3858331912
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4074597111
Short name T36
Test name
Test status
Simulation time 280115060 ps
CPU time 1.13 seconds
Started Jul 15 06:21:26 PM PDT 24
Finished Jul 15 06:21:27 PM PDT 24
Peak memory 204452 kb
Host smart-b6accbaa-a63e-4a27-a035-9f49c6f0ffc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074597111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.4074597111
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3242178851
Short name T83
Test name
Test status
Simulation time 1522216396 ps
CPU time 1.79 seconds
Started Jul 15 06:21:16 PM PDT 24
Finished Jul 15 06:21:18 PM PDT 24
Peak memory 204860 kb
Host smart-0983d382-903f-458b-a466-ada895c8d333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242178851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3242178851
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3983522419
Short name T261
Test name
Test status
Simulation time 6919840933 ps
CPU time 5.19 seconds
Started Jul 15 06:21:10 PM PDT 24
Finished Jul 15 06:21:16 PM PDT 24
Peak memory 213296 kb
Host smart-cb61fa96-6719-46b1-b2a3-c1bcf888deae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983522419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3983522419
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2610932846
Short name T43
Test name
Test status
Simulation time 257764133 ps
CPU time 1.33 seconds
Started Jul 15 06:21:31 PM PDT 24
Finished Jul 15 06:21:32 PM PDT 24
Peak memory 229212 kb
Host smart-bcd6feae-b58e-46ca-863e-95a22abcc568
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610932846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2610932846
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1426608452
Short name T281
Test name
Test status
Simulation time 540076489 ps
CPU time 1.45 seconds
Started Jul 15 06:21:11 PM PDT 24
Finished Jul 15 06:21:13 PM PDT 24
Peak memory 204884 kb
Host smart-89a65849-e531-4701-82db-5a8abee81123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426608452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1426608452
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.303843133
Short name T222
Test name
Test status
Simulation time 59579176 ps
CPU time 0.8 seconds
Started Jul 15 06:21:51 PM PDT 24
Finished Jul 15 06:21:53 PM PDT 24
Peak memory 204860 kb
Host smart-f5cfa6f1-c9ca-459f-9659-da234182d379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303843133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.303843133
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3851309138
Short name T235
Test name
Test status
Simulation time 2587282687 ps
CPU time 2.38 seconds
Started Jul 15 06:21:53 PM PDT 24
Finished Jul 15 06:21:56 PM PDT 24
Peak memory 205100 kb
Host smart-e00144e6-cc2e-4c6a-8284-f6fe2ce8c845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851309138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3851309138
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.121848246
Short name T58
Test name
Test status
Simulation time 2397082026 ps
CPU time 2.64 seconds
Started Jul 15 06:21:51 PM PDT 24
Finished Jul 15 06:21:54 PM PDT 24
Peak memory 213236 kb
Host smart-bdf558f2-89f4-40fe-a664-9ad2e9e8f3f8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=121848246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t
l_access.121848246
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.2909858737
Short name T186
Test name
Test status
Simulation time 4729863658 ps
CPU time 2.88 seconds
Started Jul 15 06:21:52 PM PDT 24
Finished Jul 15 06:21:56 PM PDT 24
Peak memory 213276 kb
Host smart-25d58309-cb42-42c2-a039-dc1f0aed02bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909858737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2909858737
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2516963476
Short name T38
Test name
Test status
Simulation time 131105097 ps
CPU time 0.74 seconds
Started Jul 15 06:21:51 PM PDT 24
Finished Jul 15 06:21:52 PM PDT 24
Peak memory 204772 kb
Host smart-d035a241-f221-4065-b632-55406e2c8d12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516963476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2516963476
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.4214910005
Short name T195
Test name
Test status
Simulation time 2147396128 ps
CPU time 2.37 seconds
Started Jul 15 06:21:52 PM PDT 24
Finished Jul 15 06:21:55 PM PDT 24
Peak memory 213208 kb
Host smart-fffffca5-8619-403b-a5ec-92b0be47404a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214910005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.4214910005
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1015758435
Short name T260
Test name
Test status
Simulation time 6753093348 ps
CPU time 10.09 seconds
Started Jul 15 06:21:51 PM PDT 24
Finished Jul 15 06:22:01 PM PDT 24
Peak memory 205088 kb
Host smart-a58a4dab-a653-468c-9113-299b71b7cb6f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1015758435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1015758435
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2066187543
Short name T70
Test name
Test status
Simulation time 2463623716 ps
CPU time 6.89 seconds
Started Jul 15 06:21:53 PM PDT 24
Finished Jul 15 06:22:01 PM PDT 24
Peak memory 213368 kb
Host smart-396063a2-de27-474d-afc0-04d0b47e2193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066187543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2066187543
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2352939509
Short name T125
Test name
Test status
Simulation time 48305610 ps
CPU time 0.79 seconds
Started Jul 15 06:21:59 PM PDT 24
Finished Jul 15 06:22:00 PM PDT 24
Peak memory 204776 kb
Host smart-550e0aba-a0a0-43db-83eb-d7bb54fc5a3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352939509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2352939509
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.506665065
Short name T157
Test name
Test status
Simulation time 20837710924 ps
CPU time 15.71 seconds
Started Jul 15 06:21:58 PM PDT 24
Finished Jul 15 06:22:15 PM PDT 24
Peak memory 213332 kb
Host smart-240c248e-bf82-4134-8aa7-b7915df67043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506665065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.506665065
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2598063153
Short name T240
Test name
Test status
Simulation time 1960086508 ps
CPU time 2.02 seconds
Started Jul 15 06:22:03 PM PDT 24
Finished Jul 15 06:22:06 PM PDT 24
Peak memory 205048 kb
Host smart-7374550b-b04a-45dd-9c29-8f64e69b1830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598063153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2598063153
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2204646689
Short name T217
Test name
Test status
Simulation time 7965010053 ps
CPU time 23.14 seconds
Started Jul 15 06:22:01 PM PDT 24
Finished Jul 15 06:22:25 PM PDT 24
Peak memory 213332 kb
Host smart-f0341448-9961-492c-99c7-06198d868609
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204646689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2204646689
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.715014610
Short name T263
Test name
Test status
Simulation time 770453779 ps
CPU time 1.26 seconds
Started Jul 15 06:21:53 PM PDT 24
Finished Jul 15 06:21:55 PM PDT 24
Peak memory 205040 kb
Host smart-9f7fdc94-4dec-4981-a79b-95cdb9137ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715014610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.715014610
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1345833678
Short name T2
Test name
Test status
Simulation time 146413828 ps
CPU time 0.88 seconds
Started Jul 15 06:22:01 PM PDT 24
Finished Jul 15 06:22:02 PM PDT 24
Peak memory 204844 kb
Host smart-6ede217e-d2ea-4a3e-9276-9ef9d77d59c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345833678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1345833678
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1659398543
Short name T216
Test name
Test status
Simulation time 6232340257 ps
CPU time 4.75 seconds
Started Jul 15 06:21:58 PM PDT 24
Finished Jul 15 06:22:03 PM PDT 24
Peak memory 215664 kb
Host smart-2b8d512c-65e8-4e97-9658-b345fd5f7e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659398543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1659398543
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3339755733
Short name T233
Test name
Test status
Simulation time 5799400163 ps
CPU time 5.16 seconds
Started Jul 15 06:21:59 PM PDT 24
Finished Jul 15 06:22:05 PM PDT 24
Peak memory 205392 kb
Host smart-357f3551-2d03-4ff5-a0cf-de3fd8a7ecf4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3339755733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3339755733
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.984143594
Short name T205
Test name
Test status
Simulation time 72945145 ps
CPU time 0.79 seconds
Started Jul 15 06:21:58 PM PDT 24
Finished Jul 15 06:22:00 PM PDT 24
Peak memory 204836 kb
Host smart-fbd41c07-4c53-4e32-a0ec-1a6372a525ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984143594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.984143594
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3266384870
Short name T193
Test name
Test status
Simulation time 40163560413 ps
CPU time 57.5 seconds
Started Jul 15 06:21:58 PM PDT 24
Finished Jul 15 06:22:56 PM PDT 24
Peak memory 213304 kb
Host smart-261a5ff8-e520-4ab7-bb18-22847d6e4a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266384870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3266384870
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3448757225
Short name T211
Test name
Test status
Simulation time 1176487521 ps
CPU time 3.95 seconds
Started Jul 15 06:21:58 PM PDT 24
Finished Jul 15 06:22:02 PM PDT 24
Peak memory 213292 kb
Host smart-fcfacaed-498b-44ae-8369-9ddbd88156fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448757225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3448757225
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.916279258
Short name T269
Test name
Test status
Simulation time 2843539032 ps
CPU time 8.1 seconds
Started Jul 15 06:22:03 PM PDT 24
Finished Jul 15 06:22:12 PM PDT 24
Peak memory 213380 kb
Host smart-114d8b23-e488-4fd5-80e7-33f187b96480
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=916279258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.916279258
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2129982578
Short name T258
Test name
Test status
Simulation time 1278751398 ps
CPU time 4.31 seconds
Started Jul 15 06:22:03 PM PDT 24
Finished Jul 15 06:22:08 PM PDT 24
Peak memory 213296 kb
Host smart-3c8bb11b-5f46-4b3b-8512-6907931775a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129982578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2129982578
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2309081674
Short name T284
Test name
Test status
Simulation time 124883764 ps
CPU time 1.01 seconds
Started Jul 15 06:22:07 PM PDT 24
Finished Jul 15 06:22:08 PM PDT 24
Peak memory 204924 kb
Host smart-d497f3f6-5ced-4cd7-a512-17f808009290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309081674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2309081674
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2992422041
Short name T250
Test name
Test status
Simulation time 3158554040 ps
CPU time 5.66 seconds
Started Jul 15 06:21:58 PM PDT 24
Finished Jul 15 06:22:04 PM PDT 24
Peak memory 213256 kb
Host smart-b891b088-301f-4a3f-ad74-454533c45447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992422041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2992422041
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.8640346
Short name T236
Test name
Test status
Simulation time 85542574 ps
CPU time 0.77 seconds
Started Jul 15 06:22:04 PM PDT 24
Finished Jul 15 06:22:06 PM PDT 24
Peak memory 204828 kb
Host smart-c3479037-5aa5-487a-8cbc-41aa577d4c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8640346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.8640346
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2131408072
Short name T231
Test name
Test status
Simulation time 8507652636 ps
CPU time 4.41 seconds
Started Jul 15 06:22:03 PM PDT 24
Finished Jul 15 06:22:07 PM PDT 24
Peak memory 213352 kb
Host smart-00992b95-c8e3-4325-a3d7-2972ae177a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131408072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2131408072
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1363314583
Short name T160
Test name
Test status
Simulation time 2952671172 ps
CPU time 6.14 seconds
Started Jul 15 06:22:06 PM PDT 24
Finished Jul 15 06:22:13 PM PDT 24
Peak memory 213432 kb
Host smart-1d01e141-d58a-4233-b1a1-a71e4f8f5a1a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1363314583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1363314583
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.242885476
Short name T200
Test name
Test status
Simulation time 40632764 ps
CPU time 0.73 seconds
Started Jul 15 06:22:04 PM PDT 24
Finished Jul 15 06:22:05 PM PDT 24
Peak memory 204856 kb
Host smart-42b4b796-0134-432b-ba1b-be0507845eeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242885476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.242885476
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.637945635
Short name T11
Test name
Test status
Simulation time 4185471048 ps
CPU time 6.88 seconds
Started Jul 15 06:22:03 PM PDT 24
Finished Jul 15 06:22:10 PM PDT 24
Peak memory 213356 kb
Host smart-e61e3661-0e3a-42bd-933a-ac1fb80e6649
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=637945635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.637945635
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.2345976485
Short name T54
Test name
Test status
Simulation time 2060449891 ps
CPU time 3.49 seconds
Started Jul 15 06:22:04 PM PDT 24
Finished Jul 15 06:22:08 PM PDT 24
Peak memory 205056 kb
Host smart-f02ee4dc-c178-4275-99a7-df7b80c68678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345976485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2345976485
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.3937946267
Short name T134
Test name
Test status
Simulation time 3365393774 ps
CPU time 9 seconds
Started Jul 15 06:22:04 PM PDT 24
Finished Jul 15 06:22:14 PM PDT 24
Peak memory 213200 kb
Host smart-1493d7c8-f126-41ad-8600-20d65c4b2fec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937946267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3937946267
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3564402384
Short name T208
Test name
Test status
Simulation time 120592738 ps
CPU time 0.78 seconds
Started Jul 15 06:22:12 PM PDT 24
Finished Jul 15 06:22:13 PM PDT 24
Peak memory 204776 kb
Host smart-2061a0bd-5deb-439c-8234-b97c85ac2da6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564402384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3564402384
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.4109024775
Short name T252
Test name
Test status
Simulation time 2158020857 ps
CPU time 6.63 seconds
Started Jul 15 06:22:04 PM PDT 24
Finished Jul 15 06:22:12 PM PDT 24
Peak memory 205104 kb
Host smart-6f8bda5e-0170-4838-b1d1-2394347af088
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4109024775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.4109024775
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.3495315621
Short name T50
Test name
Test status
Simulation time 4734427216 ps
CPU time 4.87 seconds
Started Jul 15 06:22:13 PM PDT 24
Finished Jul 15 06:22:18 PM PDT 24
Peak memory 213164 kb
Host smart-ce7b468e-60c6-4647-bf49-6fdccdaebb4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495315621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.3495315621
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3014819662
Short name T207
Test name
Test status
Simulation time 89240576 ps
CPU time 0.93 seconds
Started Jul 15 06:22:12 PM PDT 24
Finished Jul 15 06:22:14 PM PDT 24
Peak memory 204856 kb
Host smart-7335daa1-8104-4f24-ad39-cf52fbe17b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014819662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3014819662
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1667309128
Short name T230
Test name
Test status
Simulation time 4238799616 ps
CPU time 4.48 seconds
Started Jul 15 06:22:15 PM PDT 24
Finished Jul 15 06:22:20 PM PDT 24
Peak memory 213312 kb
Host smart-9757df01-ffa8-4f68-bc58-40171ca96cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667309128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1667309128
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1075455048
Short name T238
Test name
Test status
Simulation time 3091584860 ps
CPU time 3.29 seconds
Started Jul 15 06:22:13 PM PDT 24
Finished Jul 15 06:22:17 PM PDT 24
Peak memory 205152 kb
Host smart-d1a8ef7f-8169-4302-badd-24fa373ca69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075455048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1075455048
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2608213005
Short name T241
Test name
Test status
Simulation time 8592097362 ps
CPU time 6.76 seconds
Started Jul 15 06:22:11 PM PDT 24
Finished Jul 15 06:22:18 PM PDT 24
Peak memory 221528 kb
Host smart-e270bb42-1cd8-4c60-993e-390720117d44
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608213005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.2608213005
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.572730847
Short name T280
Test name
Test status
Simulation time 4064306458 ps
CPU time 12.17 seconds
Started Jul 15 06:22:12 PM PDT 24
Finished Jul 15 06:22:25 PM PDT 24
Peak memory 213312 kb
Host smart-93f6d39b-8c5d-4e9d-837a-4ee3a94b4667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572730847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.572730847
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.1566459832
Short name T17
Test name
Test status
Simulation time 2669177652 ps
CPU time 3.64 seconds
Started Jul 15 06:22:12 PM PDT 24
Finished Jul 15 06:22:16 PM PDT 24
Peak memory 213212 kb
Host smart-0a811a7b-c60b-4db2-b2c5-6b6559df2378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566459832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1566459832
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3345631257
Short name T196
Test name
Test status
Simulation time 74612445 ps
CPU time 0.72 seconds
Started Jul 15 06:21:30 PM PDT 24
Finished Jul 15 06:21:31 PM PDT 24
Peak memory 204776 kb
Host smart-927f3e94-43e7-4efe-a710-bb00295947dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345631257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3345631257
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.2615013369
Short name T26
Test name
Test status
Simulation time 32339157719 ps
CPU time 16.58 seconds
Started Jul 15 06:21:31 PM PDT 24
Finished Jul 15 06:21:48 PM PDT 24
Peak memory 213560 kb
Host smart-d182096f-378f-4a3e-900d-66bbd236495f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615013369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2615013369
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1591214356
Short name T248
Test name
Test status
Simulation time 9370157366 ps
CPU time 6.7 seconds
Started Jul 15 06:21:30 PM PDT 24
Finished Jul 15 06:21:37 PM PDT 24
Peak memory 213316 kb
Host smart-c55c9c36-2b6e-4d3b-98ab-eeb15102e94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591214356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1591214356
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2773516426
Short name T199
Test name
Test status
Simulation time 13905000742 ps
CPU time 38.5 seconds
Started Jul 15 06:21:31 PM PDT 24
Finished Jul 15 06:22:10 PM PDT 24
Peak memory 213340 kb
Host smart-30250ead-8ef3-4c50-a585-61b54ef6cdda
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2773516426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2773516426
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.15761980
Short name T245
Test name
Test status
Simulation time 755050694 ps
CPU time 2.81 seconds
Started Jul 15 06:21:32 PM PDT 24
Finished Jul 15 06:21:35 PM PDT 24
Peak memory 204896 kb
Host smart-730af00e-e3cc-4a2d-ac6e-1c3339f2965f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15761980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.15761980
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.239397886
Short name T270
Test name
Test status
Simulation time 15361724358 ps
CPU time 12 seconds
Started Jul 15 06:21:30 PM PDT 24
Finished Jul 15 06:21:43 PM PDT 24
Peak memory 213296 kb
Host smart-09cbc993-a008-4519-9c0f-caa7f1152bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239397886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.239397886
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1773484494
Short name T71
Test name
Test status
Simulation time 593883566 ps
CPU time 2.62 seconds
Started Jul 15 06:21:29 PM PDT 24
Finished Jul 15 06:21:32 PM PDT 24
Peak memory 228856 kb
Host smart-4c3ec5e7-b87a-46b8-9ac7-b3772e3e2db2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773484494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1773484494
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.551568442
Short name T275
Test name
Test status
Simulation time 114736275 ps
CPU time 0.83 seconds
Started Jul 15 06:22:12 PM PDT 24
Finished Jul 15 06:22:14 PM PDT 24
Peak memory 204828 kb
Host smart-0f31754c-927e-42dc-b7f9-c7d881b95b00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551568442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.551568442
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3488646751
Short name T232
Test name
Test status
Simulation time 52724927 ps
CPU time 0.73 seconds
Started Jul 15 06:22:13 PM PDT 24
Finished Jul 15 06:22:14 PM PDT 24
Peak memory 204824 kb
Host smart-80a55a7e-5e75-4d8f-a274-ba0252c947ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488646751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3488646751
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2296028499
Short name T202
Test name
Test status
Simulation time 173993324 ps
CPU time 0.8 seconds
Started Jul 15 06:22:11 PM PDT 24
Finished Jul 15 06:22:12 PM PDT 24
Peak memory 204828 kb
Host smart-19836e95-17d0-4ab9-bc19-f61202018255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296028499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2296028499
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2372544752
Short name T215
Test name
Test status
Simulation time 61348235 ps
CPU time 0.71 seconds
Started Jul 15 06:22:13 PM PDT 24
Finished Jul 15 06:22:14 PM PDT 24
Peak memory 204840 kb
Host smart-5c7e4d84-f70c-4211-bc42-e75ab021ad2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372544752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2372544752
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.2173415349
Short name T1
Test name
Test status
Simulation time 3723536281 ps
CPU time 3.38 seconds
Started Jul 15 06:22:14 PM PDT 24
Finished Jul 15 06:22:18 PM PDT 24
Peak memory 205008 kb
Host smart-3a11554b-3fbf-4ba4-9d9d-e4857be3d5a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173415349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2173415349
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1504144838
Short name T282
Test name
Test status
Simulation time 176476880 ps
CPU time 0.92 seconds
Started Jul 15 06:22:19 PM PDT 24
Finished Jul 15 06:22:21 PM PDT 24
Peak memory 204856 kb
Host smart-c2afd4c6-0a1e-4fcf-b87f-8aa57735b81b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504144838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1504144838
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.186064195
Short name T276
Test name
Test status
Simulation time 34335292 ps
CPU time 0.78 seconds
Started Jul 15 06:22:20 PM PDT 24
Finished Jul 15 06:22:21 PM PDT 24
Peak memory 204820 kb
Host smart-26023299-db93-42cf-ad33-b9126fc40117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186064195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.186064195
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.275555167
Short name T21
Test name
Test status
Simulation time 1916242285 ps
CPU time 3.87 seconds
Started Jul 15 06:22:20 PM PDT 24
Finished Jul 15 06:22:25 PM PDT 24
Peak memory 204904 kb
Host smart-7de430c9-354a-4693-8f51-4e3ea28b83b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275555167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.275555167
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1126088865
Short name T228
Test name
Test status
Simulation time 53722191 ps
CPU time 0.73 seconds
Started Jul 15 06:22:26 PM PDT 24
Finished Jul 15 06:22:27 PM PDT 24
Peak memory 204816 kb
Host smart-6ca7303e-cb51-4661-9410-631ba04524b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126088865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1126088865
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1982121923
Short name T229
Test name
Test status
Simulation time 81011809 ps
CPU time 0.71 seconds
Started Jul 15 06:22:20 PM PDT 24
Finished Jul 15 06:22:22 PM PDT 24
Peak memory 204816 kb
Host smart-a9d49048-36fc-4680-b7ab-d5797b5daa97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982121923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1982121923
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3411479951
Short name T124
Test name
Test status
Simulation time 139884590 ps
CPU time 0.77 seconds
Started Jul 15 06:22:21 PM PDT 24
Finished Jul 15 06:22:23 PM PDT 24
Peak memory 204804 kb
Host smart-fe8b6c1b-f67e-4d49-915f-c3a467dd0511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411479951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3411479951
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.3255944509
Short name T135
Test name
Test status
Simulation time 6542342639 ps
CPU time 18.28 seconds
Started Jul 15 06:22:21 PM PDT 24
Finished Jul 15 06:22:40 PM PDT 24
Peak memory 213296 kb
Host smart-77d149a9-7c35-46f6-98d8-d96a5871831c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255944509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3255944509
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3032815594
Short name T198
Test name
Test status
Simulation time 127014116 ps
CPU time 0.79 seconds
Started Jul 15 06:22:20 PM PDT 24
Finished Jul 15 06:22:22 PM PDT 24
Peak memory 204856 kb
Host smart-c1a7d964-dd04-44e6-ad34-65a4df4318a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032815594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3032815594
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.4062894311
Short name T223
Test name
Test status
Simulation time 81244360 ps
CPU time 0.75 seconds
Started Jul 15 06:21:37 PM PDT 24
Finished Jul 15 06:21:38 PM PDT 24
Peak memory 204844 kb
Host smart-69cb6281-1b35-4990-a012-048996920b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062894311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.4062894311
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2849851523
Short name T279
Test name
Test status
Simulation time 18157309272 ps
CPU time 7.45 seconds
Started Jul 15 06:21:32 PM PDT 24
Finished Jul 15 06:21:40 PM PDT 24
Peak memory 217892 kb
Host smart-ffd1770c-560d-4ea2-8556-739bd7297609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849851523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2849851523
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1649625115
Short name T75
Test name
Test status
Simulation time 9122389313 ps
CPU time 8.12 seconds
Started Jul 15 06:21:30 PM PDT 24
Finished Jul 15 06:21:39 PM PDT 24
Peak memory 213276 kb
Host smart-b6432096-4696-4959-a643-e0bf8a2e9181
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649625115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1649625115
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.704560863
Short name T257
Test name
Test status
Simulation time 164272423 ps
CPU time 0.89 seconds
Started Jul 15 06:21:38 PM PDT 24
Finished Jul 15 06:21:39 PM PDT 24
Peak memory 204820 kb
Host smart-bc0d6a2b-03ca-44f7-8bea-8e79ca305d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704560863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.704560863
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2549502760
Short name T44
Test name
Test status
Simulation time 339279470 ps
CPU time 1.16 seconds
Started Jul 15 06:21:38 PM PDT 24
Finished Jul 15 06:21:40 PM PDT 24
Peak memory 229300 kb
Host smart-b690c4df-4f91-4a44-a27e-8d6f4d1b88fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549502760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2549502760
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.2429924194
Short name T51
Test name
Test status
Simulation time 3216407710 ps
CPU time 5.11 seconds
Started Jul 15 06:21:38 PM PDT 24
Finished Jul 15 06:21:44 PM PDT 24
Peak memory 213240 kb
Host smart-65f20c57-1902-46d5-8fe7-218692d94e34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429924194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2429924194
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.672402483
Short name T243
Test name
Test status
Simulation time 68675967 ps
CPU time 0.7 seconds
Started Jul 15 06:22:26 PM PDT 24
Finished Jul 15 06:22:27 PM PDT 24
Peak memory 204816 kb
Host smart-226fe160-da19-44f8-919a-be5db1e42e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672402483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.672402483
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3990347662
Short name T274
Test name
Test status
Simulation time 46624207 ps
CPU time 0.82 seconds
Started Jul 15 06:22:21 PM PDT 24
Finished Jul 15 06:22:23 PM PDT 24
Peak memory 204816 kb
Host smart-8850c1e0-a62b-40c2-991e-e197a640893c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990347662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3990347662
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.325137088
Short name T68
Test name
Test status
Simulation time 162705767 ps
CPU time 0.83 seconds
Started Jul 15 06:22:25 PM PDT 24
Finished Jul 15 06:22:27 PM PDT 24
Peak memory 204780 kb
Host smart-a7fef66d-4bd6-4fa2-8050-57d094835ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325137088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.325137088
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1197265856
Short name T214
Test name
Test status
Simulation time 64131263 ps
CPU time 0.81 seconds
Started Jul 15 06:22:20 PM PDT 24
Finished Jul 15 06:22:21 PM PDT 24
Peak memory 204844 kb
Host smart-0b9cd510-0214-48cd-a400-79be00fea82b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197265856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1197265856
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.10978060
Short name T189
Test name
Test status
Simulation time 3108204588 ps
CPU time 9.37 seconds
Started Jul 15 06:22:25 PM PDT 24
Finished Jul 15 06:22:35 PM PDT 24
Peak memory 204968 kb
Host smart-7e5ab431-a617-44ca-a1d3-7eb3865e88cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10978060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.10978060
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2998408249
Short name T206
Test name
Test status
Simulation time 69532475 ps
CPU time 0.78 seconds
Started Jul 15 06:22:20 PM PDT 24
Finished Jul 15 06:22:21 PM PDT 24
Peak memory 204836 kb
Host smart-01d728d6-97ed-4df5-949d-8b37ebb8f58c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998408249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2998408249
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.801137827
Short name T268
Test name
Test status
Simulation time 265436009 ps
CPU time 0.73 seconds
Started Jul 15 06:22:23 PM PDT 24
Finished Jul 15 06:22:24 PM PDT 24
Peak memory 204844 kb
Host smart-74a0bdaa-59cc-47e6-9471-034a81c012ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801137827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.801137827
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.3765278957
Short name T30
Test name
Test status
Simulation time 16333074658 ps
CPU time 26.56 seconds
Started Jul 15 06:22:20 PM PDT 24
Finished Jul 15 06:22:47 PM PDT 24
Peak memory 214808 kb
Host smart-6a5161b3-2f09-40a3-9259-778ff0ea9962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765278957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3765278957
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.4219643441
Short name T213
Test name
Test status
Simulation time 61506349 ps
CPU time 0.84 seconds
Started Jul 15 06:22:23 PM PDT 24
Finished Jul 15 06:22:25 PM PDT 24
Peak memory 204844 kb
Host smart-51496540-d91b-46cf-b07f-9831c48fd3f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219643441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.4219643441
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2998741755
Short name T57
Test name
Test status
Simulation time 122768107 ps
CPU time 0.91 seconds
Started Jul 15 06:22:20 PM PDT 24
Finished Jul 15 06:22:22 PM PDT 24
Peak memory 204820 kb
Host smart-e62be5cc-4f98-444c-b6c0-d43c00b7c680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998741755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2998741755
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1235913154
Short name T218
Test name
Test status
Simulation time 140131154 ps
CPU time 0.84 seconds
Started Jul 15 06:22:26 PM PDT 24
Finished Jul 15 06:22:28 PM PDT 24
Peak memory 204824 kb
Host smart-527efef5-617d-4866-b0ee-d237af73fef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235913154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1235913154
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3847895470
Short name T227
Test name
Test status
Simulation time 11138610501 ps
CPU time 16.07 seconds
Started Jul 15 06:22:19 PM PDT 24
Finished Jul 15 06:22:35 PM PDT 24
Peak memory 218024 kb
Host smart-2db76067-709d-499a-b82b-262c587f2905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847895470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3847895470
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2885441821
Short name T69
Test name
Test status
Simulation time 42840120 ps
CPU time 0.71 seconds
Started Jul 15 06:21:40 PM PDT 24
Finished Jul 15 06:21:42 PM PDT 24
Peak memory 204856 kb
Host smart-1134459c-01da-4078-a0e5-0ce5c22dfa5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885441821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2885441821
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3123936318
Short name T12
Test name
Test status
Simulation time 755759864 ps
CPU time 1.42 seconds
Started Jul 15 06:21:39 PM PDT 24
Finished Jul 15 06:21:41 PM PDT 24
Peak memory 205016 kb
Host smart-58f3ae98-9935-4fcd-aa08-1be0d17fae3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123936318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3123936318
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2637059526
Short name T247
Test name
Test status
Simulation time 1757125647 ps
CPU time 5.89 seconds
Started Jul 15 06:21:40 PM PDT 24
Finished Jul 15 06:21:47 PM PDT 24
Peak memory 213272 kb
Host smart-749dca6f-fdbf-42c4-9f0e-cf52d3fadc21
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637059526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2637059526
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2955590052
Short name T209
Test name
Test status
Simulation time 474882541 ps
CPU time 1.8 seconds
Started Jul 15 06:21:41 PM PDT 24
Finished Jul 15 06:21:43 PM PDT 24
Peak memory 204844 kb
Host smart-b6077f49-356e-44a2-9454-64cf551c4568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955590052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2955590052
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.453848513
Short name T242
Test name
Test status
Simulation time 1455642604 ps
CPU time 4.78 seconds
Started Jul 15 06:21:36 PM PDT 24
Finished Jul 15 06:21:41 PM PDT 24
Peak memory 213200 kb
Host smart-15d90a27-ea06-4775-ade6-3662759a7778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453848513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.453848513
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.4056462992
Short name T72
Test name
Test status
Simulation time 461574132 ps
CPU time 1.95 seconds
Started Jul 15 06:21:37 PM PDT 24
Finished Jul 15 06:21:39 PM PDT 24
Peak memory 237368 kb
Host smart-0945cbfa-0a18-4b10-b4b6-f1758bb88bed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056462992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.4056462992
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.505751914
Short name T197
Test name
Test status
Simulation time 101512263 ps
CPU time 0.77 seconds
Started Jul 15 06:22:28 PM PDT 24
Finished Jul 15 06:22:30 PM PDT 24
Peak memory 204836 kb
Host smart-01aa75ad-e3ed-42cb-8a24-e8505b8527f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505751914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.505751914
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3954109646
Short name T191
Test name
Test status
Simulation time 42887416 ps
CPU time 0.75 seconds
Started Jul 15 06:22:26 PM PDT 24
Finished Jul 15 06:22:28 PM PDT 24
Peak memory 204748 kb
Host smart-a823e601-28b2-4fca-962b-07e555296080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954109646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3954109646
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.1430237004
Short name T6
Test name
Test status
Simulation time 2162750125 ps
CPU time 6.68 seconds
Started Jul 15 06:22:27 PM PDT 24
Finished Jul 15 06:22:35 PM PDT 24
Peak memory 205052 kb
Host smart-1afb560d-ef87-44a9-b40b-37680387cf0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430237004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1430237004
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.2887625904
Short name T210
Test name
Test status
Simulation time 57906406 ps
CPU time 0.77 seconds
Started Jul 15 06:22:27 PM PDT 24
Finished Jul 15 06:22:28 PM PDT 24
Peak memory 204832 kb
Host smart-63567e2f-9806-4fa8-83ae-c53d82542d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887625904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2887625904
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.2254136616
Short name T136
Test name
Test status
Simulation time 4208691140 ps
CPU time 6.19 seconds
Started Jul 15 06:22:28 PM PDT 24
Finished Jul 15 06:22:35 PM PDT 24
Peak memory 205028 kb
Host smart-16108377-b1b7-4d10-a915-5304c1bd7f80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254136616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2254136616
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3015102076
Short name T39
Test name
Test status
Simulation time 159084148 ps
CPU time 0.72 seconds
Started Jul 15 06:22:28 PM PDT 24
Finished Jul 15 06:22:30 PM PDT 24
Peak memory 204856 kb
Host smart-9f8bc75c-0cd8-489b-80f3-1a1f243d5bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015102076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3015102076
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.3722183950
Short name T226
Test name
Test status
Simulation time 12421689788 ps
CPU time 34.72 seconds
Started Jul 15 06:22:27 PM PDT 24
Finished Jul 15 06:23:03 PM PDT 24
Peak memory 213324 kb
Host smart-4ba36c0d-8048-4271-83d6-f79e93520551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722183950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3722183950
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2037536274
Short name T204
Test name
Test status
Simulation time 332981250 ps
CPU time 0.75 seconds
Started Jul 15 06:22:28 PM PDT 24
Finished Jul 15 06:22:30 PM PDT 24
Peak memory 204796 kb
Host smart-f2219290-a0f4-42aa-b4b2-8bc33a578532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037536274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2037536274
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.4207875568
Short name T9
Test name
Test status
Simulation time 8219512781 ps
CPU time 7.45 seconds
Started Jul 15 06:22:29 PM PDT 24
Finished Jul 15 06:22:37 PM PDT 24
Peak memory 213420 kb
Host smart-f088e52b-bf71-46a7-a759-aa35f6f2dd36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207875568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.4207875568
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1454148369
Short name T224
Test name
Test status
Simulation time 58200552 ps
CPU time 0.81 seconds
Started Jul 15 06:22:27 PM PDT 24
Finished Jul 15 06:22:28 PM PDT 24
Peak memory 204816 kb
Host smart-80f317e9-6659-40cc-98bf-b5e6b48587fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454148369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1454148369
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.2221859254
Short name T130
Test name
Test status
Simulation time 5554846328 ps
CPU time 6.6 seconds
Started Jul 15 06:22:28 PM PDT 24
Finished Jul 15 06:22:36 PM PDT 24
Peak memory 213296 kb
Host smart-5e659b6c-dcda-408e-ae8c-cb7bf7188d6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221859254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.2221859254
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1502511679
Short name T201
Test name
Test status
Simulation time 53918861 ps
CPU time 0.76 seconds
Started Jul 15 06:22:29 PM PDT 24
Finished Jul 15 06:22:31 PM PDT 24
Peak memory 204828 kb
Host smart-e9eaf3c4-ac23-458c-a636-26a56230b645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502511679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1502511679
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.3045659478
Short name T3
Test name
Test status
Simulation time 7314540810 ps
CPU time 14.27 seconds
Started Jul 15 06:22:27 PM PDT 24
Finished Jul 15 06:22:42 PM PDT 24
Peak memory 213260 kb
Host smart-c6699716-2401-4c68-83c5-bddfb0795436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045659478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3045659478
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3245171608
Short name T221
Test name
Test status
Simulation time 62316682 ps
CPU time 0.83 seconds
Started Jul 15 06:22:28 PM PDT 24
Finished Jul 15 06:22:30 PM PDT 24
Peak memory 204852 kb
Host smart-58ab366b-79cd-49bc-9c49-d0b2c75a217f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245171608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3245171608
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2442607977
Short name T249
Test name
Test status
Simulation time 83006081 ps
CPU time 0.76 seconds
Started Jul 15 06:22:28 PM PDT 24
Finished Jul 15 06:22:30 PM PDT 24
Peak memory 204808 kb
Host smart-208d0af0-fc48-44ee-b22d-e053df1caadc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442607977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2442607977
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.790223647
Short name T18
Test name
Test status
Simulation time 4310206716 ps
CPU time 12.57 seconds
Started Jul 15 06:22:28 PM PDT 24
Finished Jul 15 06:22:42 PM PDT 24
Peak memory 205084 kb
Host smart-449c07d7-113f-41b6-b159-f4d2de109978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790223647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.790223647
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3016181329
Short name T244
Test name
Test status
Simulation time 116277402 ps
CPU time 0.84 seconds
Started Jul 15 06:22:27 PM PDT 24
Finished Jul 15 06:22:29 PM PDT 24
Peak memory 204812 kb
Host smart-736a0df1-7b5d-4dd1-96f2-d6c32bfab93d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016181329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3016181329
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1057603544
Short name T203
Test name
Test status
Simulation time 49050836 ps
CPU time 0.78 seconds
Started Jul 15 06:21:44 PM PDT 24
Finished Jul 15 06:21:45 PM PDT 24
Peak memory 204796 kb
Host smart-60f43c79-faf1-4a38-9fb8-c6cb70daf552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057603544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1057603544
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3489798777
Short name T251
Test name
Test status
Simulation time 2031895176 ps
CPU time 4.1 seconds
Started Jul 15 06:21:39 PM PDT 24
Finished Jul 15 06:21:44 PM PDT 24
Peak memory 213232 kb
Host smart-02759891-388b-4de1-a247-3385de6dd878
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3489798777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3489798777
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.140765891
Short name T143
Test name
Test status
Simulation time 1560693623 ps
CPU time 5.07 seconds
Started Jul 15 06:21:38 PM PDT 24
Finished Jul 15 06:21:44 PM PDT 24
Peak memory 205048 kb
Host smart-318fc33e-4b15-4bde-b18f-28c4bf40e5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140765891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.140765891
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.607125510
Short name T262
Test name
Test status
Simulation time 32489870 ps
CPU time 0.71 seconds
Started Jul 15 06:21:44 PM PDT 24
Finished Jul 15 06:21:46 PM PDT 24
Peak memory 204852 kb
Host smart-a36db226-bdf1-46f5-ac41-9049007255c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607125510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.607125510
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3707380630
Short name T255
Test name
Test status
Simulation time 4911896649 ps
CPU time 3.89 seconds
Started Jul 15 06:21:45 PM PDT 24
Finished Jul 15 06:21:49 PM PDT 24
Peak memory 215292 kb
Host smart-f09a73db-a08b-4937-8303-77107a257c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707380630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3707380630
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2083797123
Short name T256
Test name
Test status
Simulation time 1910972761 ps
CPU time 3.73 seconds
Started Jul 15 06:21:46 PM PDT 24
Finished Jul 15 06:21:50 PM PDT 24
Peak memory 213180 kb
Host smart-cdda880b-0e7c-428c-83b1-0aaab7c6b017
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2083797123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2083797123
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3354621121
Short name T267
Test name
Test status
Simulation time 2436506373 ps
CPU time 4.47 seconds
Started Jul 15 06:21:44 PM PDT 24
Finished Jul 15 06:21:49 PM PDT 24
Peak memory 213300 kb
Host smart-583b887e-4d34-42af-a9c1-bc5e0c672da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354621121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3354621121
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.282360176
Short name T20
Test name
Test status
Simulation time 14657386911 ps
CPU time 7.55 seconds
Started Jul 15 06:21:45 PM PDT 24
Finished Jul 15 06:21:53 PM PDT 24
Peak memory 213964 kb
Host smart-c99cf0da-00ae-458e-9021-8fe2fc331139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282360176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.282360176
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2621344719
Short name T225
Test name
Test status
Simulation time 52125458 ps
CPU time 0.83 seconds
Started Jul 15 06:21:47 PM PDT 24
Finished Jul 15 06:21:48 PM PDT 24
Peak memory 204824 kb
Host smart-4798663f-e147-4082-9031-a343759f04a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621344719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2621344719
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.12067131
Short name T272
Test name
Test status
Simulation time 12713407020 ps
CPU time 20.79 seconds
Started Jul 15 06:21:46 PM PDT 24
Finished Jul 15 06:22:07 PM PDT 24
Peak memory 213376 kb
Host smart-0b6918b7-df13-4e5c-b08e-23b263236baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12067131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.12067131
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2026507934
Short name T154
Test name
Test status
Simulation time 4312885502 ps
CPU time 6.77 seconds
Started Jul 15 06:21:45 PM PDT 24
Finished Jul 15 06:21:52 PM PDT 24
Peak memory 205156 kb
Host smart-5a828dbf-97f0-4139-941a-7fef6815fc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026507934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2026507934
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1276292573
Short name T277
Test name
Test status
Simulation time 4375649499 ps
CPU time 8.01 seconds
Started Jul 15 06:21:45 PM PDT 24
Finished Jul 15 06:21:53 PM PDT 24
Peak memory 213304 kb
Host smart-6055db82-6056-4a28-bbf3-7c40f0dfb614
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1276292573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1276292573
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2526564235
Short name T278
Test name
Test status
Simulation time 2715248371 ps
CPU time 8.23 seconds
Started Jul 15 06:21:49 PM PDT 24
Finished Jul 15 06:21:58 PM PDT 24
Peak memory 213304 kb
Host smart-9b63ef6b-32c6-450a-bdd7-60b6d14f1716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526564235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2526564235
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1222776477
Short name T76
Test name
Test status
Simulation time 135309727 ps
CPU time 0.83 seconds
Started Jul 15 06:21:50 PM PDT 24
Finished Jul 15 06:21:52 PM PDT 24
Peak memory 204828 kb
Host smart-2ec13b52-c910-49be-beef-19763508c651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222776477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1222776477
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3955200363
Short name T164
Test name
Test status
Simulation time 2973286292 ps
CPU time 5.26 seconds
Started Jul 15 06:21:53 PM PDT 24
Finished Jul 15 06:21:59 PM PDT 24
Peak memory 205088 kb
Host smart-bee4ad5b-5bea-41e5-9535-8fcd6a31afd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955200363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3955200363
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2039590405
Short name T194
Test name
Test status
Simulation time 9681956031 ps
CPU time 15.01 seconds
Started Jul 15 06:21:45 PM PDT 24
Finished Jul 15 06:22:01 PM PDT 24
Peak memory 213304 kb
Host smart-426db7f0-603c-4937-8285-ceec7116e587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039590405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2039590405
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2394492005
Short name T192
Test name
Test status
Simulation time 1806490072 ps
CPU time 2.7 seconds
Started Jul 15 06:21:44 PM PDT 24
Finished Jul 15 06:21:47 PM PDT 24
Peak memory 204988 kb
Host smart-9b354685-0ad3-46b0-8253-a6bfd953e197
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2394492005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2394492005
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3188952407
Short name T169
Test name
Test status
Simulation time 6295995837 ps
CPU time 15.45 seconds
Started Jul 15 06:21:46 PM PDT 24
Finished Jul 15 06:22:02 PM PDT 24
Peak memory 205084 kb
Host smart-c5f503f2-99f9-44eb-997a-21770219e3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188952407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3188952407
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.954342345
Short name T53
Test name
Test status
Simulation time 76321542 ps
CPU time 0.87 seconds
Started Jul 15 06:21:51 PM PDT 24
Finished Jul 15 06:21:52 PM PDT 24
Peak memory 204820 kb
Host smart-1b647c15-df98-4e6b-a5fb-bdd3af91a226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954342345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.954342345
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.2981481938
Short name T212
Test name
Test status
Simulation time 3689421713 ps
CPU time 11.06 seconds
Started Jul 15 06:21:53 PM PDT 24
Finished Jul 15 06:22:05 PM PDT 24
Peak memory 205168 kb
Host smart-385939db-fe42-4dfa-8352-cb40b5b32e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981481938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2981481938
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1021685648
Short name T153
Test name
Test status
Simulation time 2658320677 ps
CPU time 4.83 seconds
Started Jul 15 06:21:52 PM PDT 24
Finished Jul 15 06:21:58 PM PDT 24
Peak memory 213296 kb
Host smart-8c798437-64e8-483c-b090-1d553af1fd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021685648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1021685648
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.475005311
Short name T163
Test name
Test status
Simulation time 11080745427 ps
CPU time 17.13 seconds
Started Jul 15 06:21:52 PM PDT 24
Finished Jul 15 06:22:09 PM PDT 24
Peak memory 213344 kb
Host smart-e8355b9f-88f7-453b-a97b-744628333e38
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=475005311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.475005311
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.38223239
Short name T273
Test name
Test status
Simulation time 4102690841 ps
CPU time 10.76 seconds
Started Jul 15 06:21:53 PM PDT 24
Finished Jul 15 06:22:05 PM PDT 24
Peak memory 205160 kb
Host smart-ec79819f-8f97-472e-b593-95fde2f79bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38223239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.38223239
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.4058200351
Short name T138
Test name
Test status
Simulation time 9676237306 ps
CPU time 9.44 seconds
Started Jul 15 06:21:52 PM PDT 24
Finished Jul 15 06:22:03 PM PDT 24
Peak memory 213232 kb
Host smart-fb72a6ed-4c24-42d3-8be4-f4988df31c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058200351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.4058200351
Directory /workspace/9.rv_dm_stress_all/latest
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