ASSERT | PROPERTIES | SEQUENCES | |
Total | 923 | 0 | 28 |
Category 0 | 923 | 0 | 28 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 923 | 0 | 28 |
Severity 0 | 923 | 0 | 28 |
NUMBER | PERCENT | |
Total Number | 923 | 100.00 |
Uncovered | 7 | 0.76 |
Success | 916 | 99.24 |
Failure | 0 | 0.00 |
Incomplete | 4 | 0.43 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 28 | 100.00 |
Uncovered | 12 | 42.86 |
All Matches | 16 | 57.14 |
First Matches | 16 | 57.14 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.FpvSecCmRomTlLcGateFsm_A | 0 | 0 | 39241069 | 0 | 0 | 0 | |
tb.dut.FpvSecCmSbaTlLcGateFsm_A | 0 | 0 | 39241069 | 0 | 0 | 0 | |
tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.SyncReqAckHoldReq | 0 | 0 | 6480721 | 0 | 0 | 0 | |
tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.SyncReqAckHoldReq | 0 | 0 | 105881328 | 0 | 0 | 0 | |
tb.dut.enable_checker.MemTLResponseWithoutDebugIsError_A | 0 | 0 | 39241069 | 0 | 0 | 0 | |
tb.dut.u_tlul_lc_gate_rom.OutStandingOvfl_A | 0 | 0 | 39241069 | 0 | 0 | 0 | |
tb.dut.u_tlul_lc_gate_sba.OutStandingOvfl_A | 0 | 0 | 39241069 | 0 | 0 | 0 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_pm_en_sync.gen_flops.OutputDelay_A | 0 | 0 | 39241069 | 39201466 | 0 | 666 | |
tb.dut.u_prim_lc_sync_lc_dft_en.gen_flops.OutputDelay_A | 0 | 0 | 39241069 | 39201466 | 0 | 666 | |
tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_flops.OutputDelay_A | 0 | 0 | 39241069 | 39201466 | 0 | 666 | |
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.gen_no_stable_chks.OutputDelay_A | 0 | 0 | 39241069 | 39201466 | 0 | 666 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |