Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201157	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	546025	1		T7	2		T4	12		T5	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	475355	1		T39	80		T44	8		T32	6
values[0x0]	133290	1		T7	3		T4	17		T5	5
values[0x1]	138537	1		T7	3		T4	29		T8	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151806	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	595376	1		T7	2		T4	16		T5	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2920	1		T67	35		T68	18		T69	10
valid_sources[0x01]	3165	1		T40	2		T67	64		T68	20
valid_sources[0x02]	2892	1		T67	34		T68	19		T69	5
valid_sources[0x03]	3199	1		T39	1		T98	1		T158	1
valid_sources[0x04]	2847	1		T67	35		T68	24		T69	3
valid_sources[0x05]	2842	1		T4	2		T39	4		T67	33
valid_sources[0x06]	2891	1		T39	2		T182	30		T67	45
valid_sources[0x07]	2992	1		T156	5		T40	1		T9	1
valid_sources[0x08]	2582	1		T4	1		T41	2		T67	44
valid_sources[0x09]	3092	1		T4	1		T67	18		T68	18
valid_sources[0x0a]	2486	1		T22	1		T183	1		T64	2
valid_sources[0x0b]	2757	1		T4	1		T39	2		T67	30
valid_sources[0x0c]	2798	1		T4	1		T183	1		T11	2
valid_sources[0x0d]	2960	1		T4	2		T98	1		T184	1
valid_sources[0x0e]	2919	1		T158	1		T67	76		T68	14
valid_sources[0x0f]	2839	1		T32	7		T67	37		T68	20
valid_sources[0x10]	2703	1		T67	56		T68	23		T69	7
valid_sources[0x11]	2912	1		T40	1		T67	53		T68	24
valid_sources[0x12]	2770	1		T4	1		T43	5		T63	1
valid_sources[0x13]	2570	1		T39	1		T40	1		T67	46
valid_sources[0x14]	3160	1		T39	1		T12	6		T34	2
valid_sources[0x15]	3288	1		T67	78		T68	24		T69	6
valid_sources[0x16]	2706	1		T39	2		T40	1		T11	1
valid_sources[0x17]	2967	1		T9	1		T67	65		T68	22
valid_sources[0x18]	3265	1		T39	1		T34	2		T158	1
valid_sources[0x19]	2823	1		T12	1		T67	46		T68	25
valid_sources[0x1a]	2702	1		T39	1		T20	4		T67	37
valid_sources[0x1b]	3604	1		T39	1		T185	2		T67	68
valid_sources[0x1c]	2923	1		T7	1		T39	1		T15	1
valid_sources[0x1d]	2674	1		T158	1		T20	1		T67	42
valid_sources[0x1e]	2588	1		T183	2		T67	49		T68	13
valid_sources[0x1f]	2665	1		T183	1		T67	47		T68	7
valid_sources[0x20]	3097	1		T32	5		T67	34		T68	28
valid_sources[0x21]	2755	1		T67	44		T68	12		T69	5
valid_sources[0x22]	3245	1		T8	1		T40	2		T11	1
valid_sources[0x23]	3016	1		T4	1		T183	1		T40	2
valid_sources[0x24]	3424	1		T67	31		T68	24		T69	9
valid_sources[0x25]	2851	1		T19	1		T40	1		T67	39
valid_sources[0x26]	2732	1		T20	1		T67	43		T68	9
valid_sources[0x27]	2732	1		T67	35		T68	19		T69	4
valid_sources[0x28]	3114	1		T26	1		T11	1		T67	28
valid_sources[0x29]	2951	1		T40	2		T9	1		T11	1
valid_sources[0x2a]	3147	1		T39	1		T21	1		T67	27
valid_sources[0x2b]	2729	1		T40	2		T67	33		T68	26
valid_sources[0x2c]	2808	1		T67	54		T68	18		T100	200
valid_sources[0x2d]	2639	1		T39	1		T98	1		T67	66
valid_sources[0x2e]	2637	1		T44	9		T158	1		T9	1
valid_sources[0x2f]	3165	1		T15	1		T67	41		T68	16
valid_sources[0x30]	3526	1		T34	2		T67	34		T68	18
valid_sources[0x31]	3687	1		T21	1		T67	32		T68	29
valid_sources[0x32]	2725	1		T32	5		T19	1		T34	1
valid_sources[0x33]	3293	1		T11	1		T67	46		T68	18
valid_sources[0x34]	2602	1		T39	1		T67	29		T68	19
valid_sources[0x35]	2800	1		T19	1		T40	3		T67	50
valid_sources[0x36]	3049	1		T183	1		T40	1		T9	1
valid_sources[0x37]	2855	1		T39	1		T40	1		T9	1
valid_sources[0x38]	3215	1		T40	1		T67	24		T68	35
valid_sources[0x39]	2845	1		T34	2		T35	1		T67	40
valid_sources[0x3a]	2693	1		T158	1		T9	3		T67	45
valid_sources[0x3b]	3013	1		T64	1		T20	1		T67	55
valid_sources[0x3c]	3084	1		T43	3		T34	2		T183	1
valid_sources[0x3d]	3182	1		T67	21		T68	28		T69	7
valid_sources[0x3e]	2816	1		T9	1		T67	65		T68	22
valid_sources[0x3f]	2840	1		T39	1		T67	32		T68	22
valid_sources[0x40]	2885	1		T67	34		T68	19		T69	6
valid_sources[0x41]	2546	1		T39	1		T40	1		T67	65
valid_sources[0x42]	2809	1		T4	1		T39	1		T158	1
valid_sources[0x43]	3154	1		T9	1		T67	39		T68	22
valid_sources[0x44]	2954	1		T67	63		T68	23		T69	3
valid_sources[0x45]	2886	1		T67	47		T68	18		T69	5
valid_sources[0x46]	2937	1		T32	2		T34	2		T9	2
valid_sources[0x47]	2632	1		T40	1		T67	53		T68	22
valid_sources[0x48]	2533	1		T39	1		T67	27		T68	21
valid_sources[0x49]	3439	1		T32	4		T67	23		T68	17
valid_sources[0x4a]	2692	1		T39	4		T26	1		T67	43
valid_sources[0x4b]	2888	1		T40	1		T67	36		T68	18
valid_sources[0x4c]	2531	1		T39	1		T32	18		T67	39
valid_sources[0x4d]	2749	1		T67	33		T68	15		T69	5
valid_sources[0x4e]	2987	1		T67	40		T68	24		T69	2
valid_sources[0x4f]	3127	1		T40	1		T67	51		T68	17
valid_sources[0x50]	3572	1		T24	34		T67	43		T68	15
valid_sources[0x51]	2894	1		T26	2		T156	1		T67	37
valid_sources[0x52]	2809	1		T99	3		T9	1		T67	68
valid_sources[0x53]	3525	1		T186	16		T184	1		T67	26
valid_sources[0x54]	2988	1		T4	4		T67	41		T68	21
valid_sources[0x55]	3508	1		T41	4		T66	3		T64	4
valid_sources[0x56]	2570	1		T39	1		T40	1		T23	17
valid_sources[0x57]	2696	1		T48	1		T36	4		T146	12
valid_sources[0x58]	2724	1		T39	1		T46	3		T9	1
valid_sources[0x59]	3431	1		T67	44		T68	24		T69	2
valid_sources[0x5a]	2956	1		T39	2		T67	24		T68	21
valid_sources[0x5b]	2987	1		T184	1		T158	1		T40	2
valid_sources[0x5c]	2686	1		T184	1		T67	56		T68	17
valid_sources[0x5d]	2814	1		T41	6		T98	1		T17	1
valid_sources[0x5e]	3106	1		T9	1		T67	37		T68	24
valid_sources[0x5f]	2990	1		T98	1		T40	2		T67	46
valid_sources[0x60]	2638	1		T183	1		T67	52		T68	28
valid_sources[0x61]	3128	1		T99	1		T67	36		T68	23
valid_sources[0x62]	2654	1		T4	6		T36	1		T67	35
valid_sources[0x63]	2683	1		T67	43		T68	16		T69	7
valid_sources[0x64]	2905	1		T39	2		T67	37		T68	16
valid_sources[0x65]	2511	1		T146	1		T64	1		T67	45
valid_sources[0x66]	2921	1		T39	2		T99	2		T9	1
valid_sources[0x67]	2915	1		T67	35		T68	14		T69	7
valid_sources[0x68]	3057	1		T39	1		T17	1		T9	1
valid_sources[0x69]	3149	1		T40	1		T67	37		T68	21
valid_sources[0x6a]	2804	1		T147	2		T187	1		T21	1
valid_sources[0x6b]	2955	1		T99	1		T183	1		T67	34
valid_sources[0x6c]	2874	1		T66	1		T183	1		T67	42
valid_sources[0x6d]	2538	1		T98	2		T36	3		T156	10
valid_sources[0x6e]	2913	1		T41	10		T40	1		T67	29
valid_sources[0x6f]	2691	1		T67	34		T68	17		T69	7
valid_sources[0x70]	3126	1		T158	1		T67	31		T68	21
valid_sources[0x71]	2887	1		T40	1		T67	44		T68	13
valid_sources[0x72]	2932	1		T32	1		T36	1		T67	49
valid_sources[0x73]	2786	1		T184	1		T67	42		T68	32
valid_sources[0x74]	2832	1		T34	3		T11	1		T67	36
valid_sources[0x75]	2444	1		T67	29		T68	20		T69	9
valid_sources[0x76]	3032	1		T99	1		T67	54		T68	34
valid_sources[0x77]	2619	1		T7	5		T4	2		T9	1
valid_sources[0x78]	2771	1		T39	1		T40	1		T67	52
valid_sources[0x79]	2907	1		T12	1		T67	27		T68	19
valid_sources[0x7a]	2736	1		T99	1		T184	2		T147	2
valid_sources[0x7b]	2557	1		T4	1		T67	45		T68	19
valid_sources[0x7c]	3203	1		T183	1		T11	1		T67	46
valid_sources[0x7d]	2791	1		T158	1		T67	64		T68	21
valid_sources[0x7e]	2750	1		T67	45		T68	27		T69	4
valid_sources[0x7f]	3376	1		T67	48		T68	21		T69	6
valid_sources[0x80]	3026	1		T39	2		T188	1		T183	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

284070

1

T39

80

T44

1

T32

5

values[0x0]

all_enables

biggest_size

131426

1

T4

6

T5

1

T6

1

values[0x1]

all_enables

biggest_size

130529

1

T7

2

T4

6

T26

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4893	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	21525	1		T1	1		T2	1		T7	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9874	1		T67	65		T68	31		T69	158
values[0x0]	7979	1		T2	5		T3	4		T7	1
values[0x1]	8565	1		T1	1		T2	3		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3688	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	22730	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	71	1		T8	2		T36	2		T92	1
valid_sources[0x01]	111	1		T152	1		T189	1		T100	25
valid_sources[0x02]	71	1		T83	1		T93	1		T96	1
valid_sources[0x03]	65	1		T51	1		T15	1		T190	1
valid_sources[0x04]	53	1		T89	1		T83	1		T93	2
valid_sources[0x05]	116	1		T191	1		T192	1		T83	25
valid_sources[0x06]	49	1		T193	3		T89	3		T91	3
valid_sources[0x07]	84	1		T67	1		T83	11		T93	2
valid_sources[0x08]	204	1		T24	1		T67	1		T69	18
valid_sources[0x09]	95	1		T194	1		T68	7		T93	2
valid_sources[0x0a]	66	1		T34	1		T88	1		T93	2
valid_sources[0x0b]	106	1		T13	1		T22	1		T10	1
valid_sources[0x0c]	174	1		T72	1		T195	1		T16	1
valid_sources[0x0d]	64	1		T69	3		T92	2		T93	2
valid_sources[0x0e]	104	1		T196	1		T197	1		T91	11
valid_sources[0x0f]	74	1		T165	1		T198	2		T69	1
valid_sources[0x10]	71	1		T91	7		T83	13		T93	4
valid_sources[0x11]	60	1		T199	1		T200	1		T83	1
valid_sources[0x12]	154	1		T201	1		T15	2		T89	1
valid_sources[0x13]	145	1		T148	1		T67	1		T83	17
valid_sources[0x14]	47	1		T41	1		T22	1		T83	1
valid_sources[0x15]	60	1		T140	2		T192	1		T21	1
valid_sources[0x16]	167	1		T69	3		T92	1		T93	1
valid_sources[0x17]	111	1		T110	1		T115	1		T69	5
valid_sources[0x18]	75	1		T112	1		T190	1		T10	1
valid_sources[0x19]	120	1		T6	1		T16	1		T69	1
valid_sources[0x1a]	62	1		T26	1		T67	1		T88	1
valid_sources[0x1b]	88	1		T201	2		T16	1		T202	1
valid_sources[0x1c]	211	1		T164	1		T10	1		T100	145
valid_sources[0x1d]	64	1		T203	1		T199	1		T93	3
valid_sources[0x1e]	113	1		T26	1		T83	56		T103	1
valid_sources[0x1f]	123	1		T204	1		T67	1		T91	11
valid_sources[0x20]	101	1		T201	1		T199	1		T18	1
valid_sources[0x21]	67	1		T61	1		T196	2		T147	3
valid_sources[0x22]	114	1		T36	3		T205	1		T67	2
valid_sources[0x23]	60	1		T151	8		T45	1		T92	5
valid_sources[0x24]	88	1		T30	1		T199	1		T88	5
valid_sources[0x25]	96	1		T50	1		T141	2		T183	1
valid_sources[0x26]	160	1		T1	1		T206	1		T69	8
valid_sources[0x27]	75	1		T192	5		T12	1		T207	1
valid_sources[0x28]	81	1		T80	1		T157	10		T9	1
valid_sources[0x29]	122	1		T208	1		T89	2		T83	57
valid_sources[0x2a]	76	1		T16	1		T67	4		T93	2
valid_sources[0x2b]	127	1		T2	1		T209	1		T69	1
valid_sources[0x2c]	72	1		T147	1		T18	1		T69	4
valid_sources[0x2d]	98	1		T210	3		T69	1		T89	5
valid_sources[0x2e]	82	1		T156	1		T67	1		T69	5
valid_sources[0x2f]	188	1		T140	1		T66	7		T16	1
valid_sources[0x30]	147	1		T25	1		T196	1		T69	3
valid_sources[0x31]	37	1		T167	1		T196	1		T211	1
valid_sources[0x32]	55	1		T201	1		T83	12		T93	2
valid_sources[0x33]	77	1		T41	2		T67	1		T88	3
valid_sources[0x34]	97	1		T140	2		T67	1		T83	29
valid_sources[0x35]	86	1		T212	2		T67	1		T90	3
valid_sources[0x36]	94	1		T49	1		T213	2		T196	1
valid_sources[0x37]	85	1		T67	1		T69	3		T83	1
valid_sources[0x38]	85	1		T70	1		T42	1		T193	1
valid_sources[0x39]	91	1		T67	2		T69	8		T88	5
valid_sources[0x3a]	67	1		T15	3		T182	7		T102	2
valid_sources[0x3b]	91	1		T154	1		T206	1		T83	9
valid_sources[0x3c]	97	1		T39	1		T199	1		T83	7
valid_sources[0x3d]	107	1		T41	1		T214	1		T215	1
valid_sources[0x3e]	91	1		T69	6		T83	21		T93	4
valid_sources[0x3f]	85	1		T77	1		T88	2		T113	1
valid_sources[0x40]	75	1		T32	7		T216	1		T217	1
valid_sources[0x41]	84	1		T163	5		T189	1		T69	2
valid_sources[0x42]	69	1		T110	3		T209	1		T218	1
valid_sources[0x43]	148	1		T209	1		T90	3		T83	2
valid_sources[0x44]	103	1		T219	8		T9	1		T88	3
valid_sources[0x45]	95	1		T50	2		T196	1		T147	1
valid_sources[0x46]	68	1		T22	1		T89	1		T83	10
valid_sources[0x47]	53	1		T83	1		T93	3		T96	1
valid_sources[0x48]	78	1		T69	6		T91	3		T93	1
valid_sources[0x49]	145	1		T58	1		T220	6		T190	1
valid_sources[0x4a]	158	1		T69	2		T83	7		T92	2
valid_sources[0x4b]	64	1		T220	3		T221	1		T69	2
valid_sources[0x4c]	87	1		T168	1		T222	1		T69	2
valid_sources[0x4d]	61	1		T88	1		T83	10		T93	2
valid_sources[0x4e]	75	1		T34	1		T223	1		T67	1
valid_sources[0x4f]	89	1		T25	2		T26	1		T224	5
valid_sources[0x50]	72	1		T8	1		T225	1		T226	14
valid_sources[0x51]	85	1		T69	21		T88	2		T91	7
valid_sources[0x52]	98	1		T62	2		T147	1		T67	2
valid_sources[0x53]	105	1		T75	1		T67	1		T88	1
valid_sources[0x54]	48	1		T24	1		T93	3		T96	1
valid_sources[0x55]	97	1		T82	4		T69	4		T89	1
valid_sources[0x56]	74	1		T69	1		T93	3		T96	1
valid_sources[0x57]	83	1		T67	2		T69	1		T83	4
valid_sources[0x58]	70	1		T199	1		T67	1		T69	2
valid_sources[0x59]	171	1		T67	2		T69	6		T92	2
valid_sources[0x5a]	131	1		T196	1		T69	2		T83	46
valid_sources[0x5b]	72	1		T7	1		T227	1		T67	1
valid_sources[0x5c]	79	1		T59	1		T228	2		T88	4
valid_sources[0x5d]	93	1		T192	1		T83	1		T93	2
valid_sources[0x5e]	185	1		T192	1		T69	2		T89	1
valid_sources[0x5f]	163	1		T229	6		T230	1		T69	3
valid_sources[0x60]	71	1		T231	7		T69	3		T90	3
valid_sources[0x61]	106	1		T12	1		T212	2		T211	1
valid_sources[0x62]	57	1		T232	1		T22	1		T219	3
valid_sources[0x63]	73	1		T233	1		T183	1		T67	1
valid_sources[0x64]	224	1		T211	1		T69	18		T89	1
valid_sources[0x65]	67	1		T2	1		T141	1		T232	1
valid_sources[0x66]	76	1		T189	1		T199	1		T67	2
valid_sources[0x67]	60	1		T83	17		T113	5		T97	1
valid_sources[0x68]	120	1		T2	1		T83	42		T93	2
valid_sources[0x69]	67	1		T98	1		T189	2		T93	4
valid_sources[0x6a]	72	1		T88	1		T83	1		T93	5
valid_sources[0x6b]	227	1		T234	2		T67	2		T68	7
valid_sources[0x6c]	178	1		T196	1		T89	2		T83	77
valid_sources[0x6d]	94	1		T2	1		T93	3		T96	2
valid_sources[0x6e]	73	1		T222	1		T97	2		T143	3
valid_sources[0x6f]	418	1		T4	6		T62	2		T141	1
valid_sources[0x70]	65	1		T111	1		T69	1		T83	10
valid_sources[0x71]	181	1		T69	9		T94	1		T175	31
valid_sources[0x72]	70	1		T26	1		T211	1		T67	1
valid_sources[0x73]	68	1		T193	1		T10	1		T69	1
valid_sources[0x74]	109	1		T189	1		T235	1		T69	9
valid_sources[0x75]	196	1		T140	1		T184	1		T9	1
valid_sources[0x76]	165	1		T236	1		T16	2		T228	1
valid_sources[0x77]	82	1		T2	1		T141	1		T190	1
valid_sources[0x78]	57	1		T150	1		T34	1		T211	1
valid_sources[0x79]	83	1		T34	1		T88	1		T90	3
valid_sources[0x7a]	153	1		T77	5		T212	1		T210	6
valid_sources[0x7b]	280	1		T24	3		T67	1		T83	14
valid_sources[0x7c]	163	1		T34	1		T15	1		T68	7
valid_sources[0x7d]	596	1		T237	1		T88	1		T93	5
valid_sources[0x7e]	69	1		T110	1		T154	1		T199	1
valid_sources[0x7f]	89	1		T22	1		T89	3		T83	3
valid_sources[0x80]	116	1		T154	1		T189	1		T67	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6980

1

T67

24

T68

9

T69

149

values[0x0]

all_enables

biggest_size

7240

1

T2

1

T7

1

T4

4

values[0x1]

all_enables

biggest_size

7305

1

T1

1

T4

2

T8

1