SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 775076 | 1 | T7 | 6 | T4 | 46 | T8 | 2 | |||
auto[1] | 23975 | 1 | T39 | 80 | T40 | 80 | T67 | 14 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 798820 | 1 | T7 | 6 | T4 | 46 | T8 | 2 | |||
values[1] | 20 | 1 | T67 | 3 | T89 | 2 | T91 | 1 | |||
values[2] | 6 | 1 | T172 | 1 | T173 | 1 | T174 | 1 | |||
values[3] | 125 | 1 | T67 | 7 | T68 | 3 | T89 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 798834 | 1 | T7 | 6 | T4 | 46 | T8 | 2 | |||
values[1] | 22 | 1 | T67 | 2 | T89 | 2 | T91 | 1 | |||
values[2] | 8 | 1 | T113 | 1 | T175 | 1 | T176 | 2 | |||
values[3] | 111 | 1 | T67 | 9 | T68 | 2 | T89 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 798711 | 1 | T7 | 6 | T4 | 46 | T8 | 2 | |||
auto[TlIntgErrCmd] | 123 | 1 | T67 | 6 | T68 | 4 | T89 | 6 | |||
auto[TlIntgErrData] | 109 | 1 | T67 | 6 | T68 | 3 | T89 | 7 | |||
auto[TlIntgErrBoth] | 108 | 1 | T67 | 8 | T68 | 3 | T89 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 47019 | 0 | T1 | 1 | T2 | 8 | T3 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 46791 | 1 | T1 | 1 | T2 | 8 | T3 | 7 | |||
values[1] | 21 | 1 | T67 | 1 | T68 | 2 | T90 | 1 | |||
values[2] | 5 | 1 | T113 | 1 | T175 | 1 | T176 | 2 | |||
values[3] | 116 | 1 | T67 | 9 | T68 | 2 | T89 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 46789 | 1 | T1 | 1 | T2 | 8 | T3 | 7 | |||
values[1] | 22 | 1 | T67 | 1 | T89 | 3 | T113 | 2 | |||
values[2] | 10 | 1 | T67 | 1 | T89 | 1 | T175 | 1 | |||
values[3] | 109 | 1 | T67 | 4 | T68 | 5 | T89 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 46679 | 1 | T1 | 1 | T2 | 8 | T3 | 7 | |||
auto[TlIntgErrCmd] | 110 | 1 | T67 | 8 | T68 | 3 | T89 | 4 | |||
auto[TlIntgErrData] | 112 | 1 | T67 | 4 | T68 | 1 | T89 | 7 | |||
auto[TlIntgErrBoth] | 118 | 1 | T67 | 8 | T68 | 6 | T89 | 9 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |