Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	250939	1		T7	4		T4	34		T8	2
full_word	548112	1		T7	2		T4	12		T5	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	798711	1		T7	6		T4	46		T8	2
auto[TlIntgErrCmd]	123	1		T67	6		T68	4		T89	6
auto[TlIntgErrData]	109	1		T67	6		T68	3		T89	7
auto[TlIntgErrBoth]	108	1		T67	8		T68	3		T89	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	477861	1		T39	80		T44	8		T32	6
auto[1]	321190	1		T7	6		T4	46		T8	2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	193400	1		T44	7		T32	1		T41	11
auto[TlIntgErrNone]	partial	auto[1]	57222	1		T7	4		T4	34		T8	2
auto[TlIntgErrNone]	full_word	auto[0]	284298	1		T39	80		T44	1		T32	5
auto[TlIntgErrNone]	full_word	auto[1]	263791	1		T7	2		T4	12		T5	1
auto[TlIntgErrCmd]	partial	auto[0]	61	1		T67	2		T68	2		T89	3
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T67	4		T68	1		T89	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T177	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T68	1		T89	1		T90	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T67	3		T68	1		T90	1
auto[TlIntgErrData]	partial	auto[1]	53	1		T67	3		T68	2		T89	6
auto[TlIntgErrData]	full_word	auto[0]	6	1		T143	1		T176	3		T178	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T89	1		T178	1		T179	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T67	2		T89	2		T90	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T67	5		T68	3		T89	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T175	1		T172	1		T173	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T67	1		T89	2		T175	1