Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 122256473 15948 0 0
late_debug_enable_rd_A 122256473 3857 0 0
late_debug_enable_regwen_rd_A 122256473 3652 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122256473 15948 0 0
T67 327769 6 0 0
T68 121771 2 0 0
T69 343627 269 0 0
T83 611358 1806 0 0
T88 10094 176 0 0
T89 184629 5 0 0
T90 290966 2 0 0
T91 285750 5 0 0
T92 9435 18 0 0
T93 7747 582 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122256473 3857 0 0
T83 611358 932 0 0
T91 285750 57 0 0
T96 7625 34 0 0
T103 12728 8 0 0
T105 11730 10 0 0
T106 52607 65 0 0
T109 401552 548 0 0
T121 339780 1065 0 0
T143 112069 20 0 0
T144 20381 30 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 122256473 3652 0 0
T83 611358 729 0 0
T91 285750 32 0 0
T96 7625 45 0 0
T101 7375 5 0 0
T103 12728 12 0 0
T105 11730 2 0 0
T106 52607 18 0 0
T109 401552 599 0 0
T143 112069 52 0 0
T144 20381 41 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%