SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 212 | 212 | 0 | 0 |
OutputsKnown_A | 44141060 | 44108037 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 44141060 | 44106543 | 0 | 636 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212 | 212 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44108037 | 0 | 0 |
T1 | 158621 | 158541 | 0 | 0 |
T2 | 1303 | 1249 | 0 | 0 |
T3 | 1654 | 1574 | 0 | 0 |
T4 | 112268 | 111903 | 0 | 0 |
T5 | 87356 | 87297 | 0 | 0 |
T7 | 71641 | 71590 | 0 | 0 |
T8 | 130039 | 129908 | 0 | 0 |
T13 | 287430 | 287346 | 0 | 0 |
T47 | 66102 | 66034 | 0 | 0 |
T48 | 1792 | 1703 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44106543 | 0 | 636 |
T1 | 158621 | 158538 | 0 | 3 |
T2 | 1303 | 1246 | 0 | 3 |
T3 | 1654 | 1571 | 0 | 3 |
T4 | 112268 | 111888 | 0 | 3 |
T5 | 87356 | 87294 | 0 | 3 |
T7 | 71641 | 71587 | 0 | 3 |
T8 | 130039 | 129902 | 0 | 3 |
T13 | 287430 | 287343 | 0 | 3 |
T47 | 66102 | 66031 | 0 | 3 |
T48 | 1792 | 1700 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |