Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
44141060 |
3607358 |
0 |
0 |
T4 |
112268 |
31314 |
0 |
0 |
T5 |
87356 |
83341 |
0 |
0 |
T6 |
0 |
75733 |
0 |
0 |
T7 |
71641 |
22507 |
0 |
0 |
T8 |
130039 |
35733 |
0 |
0 |
T13 |
287430 |
0 |
0 |
0 |
T14 |
14822 |
0 |
0 |
0 |
T25 |
144213 |
0 |
0 |
0 |
T26 |
0 |
15238 |
0 |
0 |
T28 |
292601 |
35023 |
0 |
0 |
T32 |
0 |
281855 |
0 |
0 |
T44 |
0 |
30122 |
0 |
0 |
T47 |
66102 |
0 |
0 |
0 |
T48 |
1792 |
0 |
0 |
0 |
T145 |
0 |
672 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
44141060 |
2 |
0 |
0 |
T6 |
108067 |
0 |
0 |
0 |
T14 |
14822 |
0 |
0 |
0 |
T25 |
144213 |
0 |
0 |
0 |
T28 |
292601 |
0 |
0 |
0 |
T29 |
107754 |
0 |
0 |
0 |
T39 |
1738 |
0 |
0 |
0 |
T48 |
1792 |
1 |
0 |
0 |
T51 |
14070 |
0 |
0 |
0 |
T62 |
4884 |
0 |
0 |
0 |
T63 |
0 |
1 |
0 |
0 |
T110 |
3856 |
0 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
44141060 |
13 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T18 |
0 |
2 |
0 |
0 |
T24 |
612514 |
1 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T36 |
0 |
1 |
0 |
0 |
T37 |
62554 |
0 |
0 |
0 |
T64 |
0 |
2 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T66 |
360439 |
0 |
0 |
0 |
T146 |
0 |
1 |
0 |
0 |
T147 |
0 |
1 |
0 |
0 |
T148 |
123293 |
0 |
0 |
0 |
T149 |
1206 |
0 |
0 |
0 |
T150 |
919475 |
0 |
0 |
0 |
T151 |
2391 |
0 |
0 |
0 |
T152 |
21883 |
0 |
0 |
0 |
T153 |
177507 |
0 |
0 |
0 |
T154 |
6058 |
0 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
44141060 |
13171 |
0 |
0 |
T1 |
158621 |
40 |
0 |
0 |
T2 |
1303 |
0 |
0 |
0 |
T3 |
1654 |
0 |
0 |
0 |
T4 |
112268 |
0 |
0 |
0 |
T5 |
87356 |
0 |
0 |
0 |
T7 |
71641 |
0 |
0 |
0 |
T8 |
130039 |
0 |
0 |
0 |
T13 |
287430 |
9 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T25 |
0 |
7 |
0 |
0 |
T29 |
0 |
357 |
0 |
0 |
T47 |
66102 |
0 |
0 |
0 |
T48 |
1792 |
0 |
0 |
0 |
T49 |
0 |
108 |
0 |
0 |
T50 |
0 |
47 |
0 |
0 |
T70 |
0 |
10 |
0 |
0 |
T72 |
0 |
10 |
0 |
0 |
T115 |
0 |
40 |
0 |
0 |