Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9585682 |
9584400 |
0 |
0 |
selKnown1 |
50984719 |
50983437 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9585682 |
9584400 |
0 |
0 |
T1 |
13780 |
13778 |
0 |
0 |
T2 |
1073 |
1071 |
0 |
0 |
T3 |
747 |
745 |
0 |
0 |
T4 |
52644 |
52640 |
0 |
0 |
T5 |
13392 |
13388 |
0 |
0 |
T7 |
4637 |
4635 |
0 |
0 |
T8 |
20707 |
20703 |
0 |
0 |
T13 |
10675 |
10671 |
0 |
0 |
T14 |
6 |
4 |
0 |
0 |
T25 |
6 |
4 |
0 |
0 |
T26 |
0 |
23 |
0 |
0 |
T28 |
17 |
15 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T47 |
2661 |
2657 |
0 |
0 |
T48 |
730 |
726 |
0 |
0 |
T50 |
0 |
10 |
0 |
0 |
T51 |
2 |
0 |
0 |
0 |
T52 |
0 |
20 |
0 |
0 |
T55 |
0 |
8 |
0 |
0 |
T59 |
0 |
9 |
0 |
0 |
T60 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50984719 |
50983437 |
0 |
0 |
T1 |
165511 |
165509 |
0 |
0 |
T2 |
1839 |
1837 |
0 |
0 |
T3 |
2027 |
2025 |
0 |
0 |
T4 |
138594 |
138590 |
0 |
0 |
T5 |
94053 |
94049 |
0 |
0 |
T7 |
73959 |
73957 |
0 |
0 |
T8 |
140393 |
140389 |
0 |
0 |
T13 |
292768 |
292764 |
0 |
0 |
T14 |
6 |
4 |
0 |
0 |
T25 |
6 |
4 |
0 |
0 |
T26 |
0 |
10 |
0 |
0 |
T28 |
6 |
4 |
0 |
0 |
T32 |
0 |
8 |
0 |
0 |
T47 |
67433 |
67429 |
0 |
0 |
T48 |
2158 |
2154 |
0 |
0 |
T50 |
0 |
10 |
0 |
0 |
T51 |
2 |
0 |
0 |
0 |
T52 |
0 |
40 |
0 |
0 |
T60 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2741618 |
2741406 |
0 |
0 |
selKnown1 |
44141060 |
44140848 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2741618 |
2741406 |
0 |
0 |
T1 |
6890 |
6889 |
0 |
0 |
T2 |
536 |
535 |
0 |
0 |
T3 |
373 |
372 |
0 |
0 |
T4 |
26316 |
26315 |
0 |
0 |
T5 |
6695 |
6694 |
0 |
0 |
T7 |
2318 |
2317 |
0 |
0 |
T8 |
10350 |
10349 |
0 |
0 |
T13 |
5336 |
5335 |
0 |
0 |
T47 |
1329 |
1328 |
0 |
0 |
T48 |
364 |
363 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
44141060 |
44140848 |
0 |
0 |
T1 |
158621 |
158620 |
0 |
0 |
T2 |
1303 |
1302 |
0 |
0 |
T3 |
1654 |
1653 |
0 |
0 |
T4 |
112268 |
112267 |
0 |
0 |
T5 |
87356 |
87355 |
0 |
0 |
T7 |
71641 |
71640 |
0 |
0 |
T8 |
130039 |
130038 |
0 |
0 |
T13 |
287430 |
287429 |
0 |
0 |
T47 |
66102 |
66101 |
0 |
0 |
T48 |
1792 |
1791 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
516 |
304 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T8 |
3 |
2 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
3 |
2 |
0 |
0 |
T25 |
3 |
2 |
0 |
0 |
T26 |
0 |
6 |
0 |
0 |
T28 |
5 |
4 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T50 |
0 |
5 |
0 |
0 |
T51 |
1 |
0 |
0 |
0 |
T52 |
0 |
20 |
0 |
0 |
T60 |
0 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
498 |
286 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T8 |
2 |
1 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
3 |
2 |
0 |
0 |
T25 |
3 |
2 |
0 |
0 |
T26 |
0 |
5 |
0 |
0 |
T28 |
3 |
2 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T50 |
0 |
5 |
0 |
0 |
T51 |
1 |
0 |
0 |
0 |
T52 |
0 |
20 |
0 |
0 |
T60 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6841698 |
6841269 |
0 |
0 |
selKnown1 |
6841497 |
6841068 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6841698 |
6841269 |
0 |
0 |
T1 |
6890 |
6889 |
0 |
0 |
T2 |
537 |
536 |
0 |
0 |
T3 |
374 |
373 |
0 |
0 |
T4 |
26316 |
26315 |
0 |
0 |
T5 |
6695 |
6694 |
0 |
0 |
T7 |
2319 |
2318 |
0 |
0 |
T8 |
10351 |
10350 |
0 |
0 |
T13 |
5337 |
5336 |
0 |
0 |
T47 |
1330 |
1329 |
0 |
0 |
T48 |
364 |
363 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6841497 |
6841068 |
0 |
0 |
T1 |
6890 |
6889 |
0 |
0 |
T2 |
536 |
535 |
0 |
0 |
T3 |
373 |
372 |
0 |
0 |
T4 |
26316 |
26315 |
0 |
0 |
T5 |
6695 |
6694 |
0 |
0 |
T7 |
2318 |
2317 |
0 |
0 |
T8 |
10350 |
10349 |
0 |
0 |
T13 |
5336 |
5335 |
0 |
0 |
T47 |
1329 |
1328 |
0 |
0 |
T48 |
364 |
363 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1850 |
1421 |
0 |
0 |
selKnown1 |
1664 |
1235 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1850 |
1421 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T8 |
3 |
2 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
3 |
2 |
0 |
0 |
T25 |
3 |
2 |
0 |
0 |
T26 |
0 |
17 |
0 |
0 |
T28 |
12 |
11 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T50 |
0 |
5 |
0 |
0 |
T51 |
1 |
0 |
0 |
0 |
T55 |
0 |
8 |
0 |
0 |
T59 |
0 |
9 |
0 |
0 |
T60 |
0 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1664 |
1235 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T8 |
2 |
1 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
3 |
2 |
0 |
0 |
T25 |
3 |
2 |
0 |
0 |
T26 |
0 |
5 |
0 |
0 |
T28 |
3 |
2 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T50 |
0 |
5 |
0 |
0 |
T51 |
1 |
0 |
0 |
0 |
T52 |
0 |
20 |
0 |
0 |
T60 |
0 |
2 |
0 |
0 |