SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
79.81 | 98.04 | 77.78 | 85.71 | 87.50 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1272 | 1272 | 0 | 0 |
OutputsKnown_A | 264846360 | 264648222 | 0 | 0 |
gen_flops.OutputDelay_A | 132423180 | 132319629 | 0 | 1908 |
gen_no_flops.OutputDelay_A | 132423180 | 132324111 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1272 | 1272 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T13 | 6 | 6 | 0 | 0 |
T47 | 6 | 6 | 0 | 0 |
T48 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 264846360 | 264648222 | 0 | 0 |
T1 | 951726 | 951246 | 0 | 0 |
T2 | 7818 | 7494 | 0 | 0 |
T3 | 9924 | 9444 | 0 | 0 |
T4 | 673608 | 671418 | 0 | 0 |
T5 | 524136 | 523782 | 0 | 0 |
T7 | 429846 | 429540 | 0 | 0 |
T8 | 780234 | 779448 | 0 | 0 |
T13 | 1724580 | 1724076 | 0 | 0 |
T47 | 396612 | 396204 | 0 | 0 |
T48 | 10752 | 10218 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 132423180 | 132319629 | 0 | 1908 |
T1 | 475863 | 475614 | 0 | 9 |
T2 | 3909 | 3738 | 0 | 9 |
T3 | 4962 | 4713 | 0 | 9 |
T4 | 336804 | 335664 | 0 | 9 |
T5 | 262068 | 261882 | 0 | 9 |
T7 | 214923 | 214761 | 0 | 9 |
T8 | 390117 | 389706 | 0 | 9 |
T13 | 862290 | 862029 | 0 | 9 |
T47 | 198306 | 198093 | 0 | 9 |
T48 | 5376 | 5100 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 132423180 | 132324111 | 0 | 0 |
T1 | 475863 | 475623 | 0 | 0 |
T2 | 3909 | 3747 | 0 | 0 |
T3 | 4962 | 4722 | 0 | 0 |
T4 | 336804 | 335709 | 0 | 0 |
T5 | 262068 | 261891 | 0 | 0 |
T7 | 214923 | 214770 | 0 | 0 |
T8 | 390117 | 389724 | 0 | 0 |
T13 | 862290 | 862038 | 0 | 0 |
T47 | 198306 | 198102 | 0 | 0 |
T48 | 5376 | 5109 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 212 | 212 | 0 | 0 |
OutputsKnown_A | 44141060 | 44108037 | 0 | 0 |
gen_flops.OutputDelay_A | 44141060 | 44106543 | 0 | 636 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212 | 212 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44108037 | 0 | 0 |
T1 | 158621 | 158541 | 0 | 0 |
T2 | 1303 | 1249 | 0 | 0 |
T3 | 1654 | 1574 | 0 | 0 |
T4 | 112268 | 111903 | 0 | 0 |
T5 | 87356 | 87297 | 0 | 0 |
T7 | 71641 | 71590 | 0 | 0 |
T8 | 130039 | 129908 | 0 | 0 |
T13 | 287430 | 287346 | 0 | 0 |
T47 | 66102 | 66034 | 0 | 0 |
T48 | 1792 | 1703 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44106543 | 0 | 636 |
T1 | 158621 | 158538 | 0 | 3 |
T2 | 1303 | 1246 | 0 | 3 |
T3 | 1654 | 1571 | 0 | 3 |
T4 | 112268 | 111888 | 0 | 3 |
T5 | 87356 | 87294 | 0 | 3 |
T7 | 71641 | 71587 | 0 | 3 |
T8 | 130039 | 129902 | 0 | 3 |
T13 | 287430 | 287343 | 0 | 3 |
T47 | 66102 | 66031 | 0 | 3 |
T48 | 1792 | 1700 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 212 | 212 | 0 | 0 |
OutputsKnown_A | 44141060 | 44108037 | 0 | 0 |
gen_flops.OutputDelay_A | 44141060 | 44106543 | 0 | 636 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212 | 212 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44108037 | 0 | 0 |
T1 | 158621 | 158541 | 0 | 0 |
T2 | 1303 | 1249 | 0 | 0 |
T3 | 1654 | 1574 | 0 | 0 |
T4 | 112268 | 111903 | 0 | 0 |
T5 | 87356 | 87297 | 0 | 0 |
T7 | 71641 | 71590 | 0 | 0 |
T8 | 130039 | 129908 | 0 | 0 |
T13 | 287430 | 287346 | 0 | 0 |
T47 | 66102 | 66034 | 0 | 0 |
T48 | 1792 | 1703 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44106543 | 0 | 636 |
T1 | 158621 | 158538 | 0 | 3 |
T2 | 1303 | 1246 | 0 | 3 |
T3 | 1654 | 1571 | 0 | 3 |
T4 | 112268 | 111888 | 0 | 3 |
T5 | 87356 | 87294 | 0 | 3 |
T7 | 71641 | 71587 | 0 | 3 |
T8 | 130039 | 129902 | 0 | 3 |
T13 | 287430 | 287343 | 0 | 3 |
T47 | 66102 | 66031 | 0 | 3 |
T48 | 1792 | 1700 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 212 | 212 | 0 | 0 |
OutputsKnown_A | 44141060 | 44108037 | 0 | 0 |
gen_no_flops.OutputDelay_A | 44141060 | 44108037 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212 | 212 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44108037 | 0 | 0 |
T1 | 158621 | 158541 | 0 | 0 |
T2 | 1303 | 1249 | 0 | 0 |
T3 | 1654 | 1574 | 0 | 0 |
T4 | 112268 | 111903 | 0 | 0 |
T5 | 87356 | 87297 | 0 | 0 |
T7 | 71641 | 71590 | 0 | 0 |
T8 | 130039 | 129908 | 0 | 0 |
T13 | 287430 | 287346 | 0 | 0 |
T47 | 66102 | 66034 | 0 | 0 |
T48 | 1792 | 1703 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44108037 | 0 | 0 |
T1 | 158621 | 158541 | 0 | 0 |
T2 | 1303 | 1249 | 0 | 0 |
T3 | 1654 | 1574 | 0 | 0 |
T4 | 112268 | 111903 | 0 | 0 |
T5 | 87356 | 87297 | 0 | 0 |
T7 | 71641 | 71590 | 0 | 0 |
T8 | 130039 | 129908 | 0 | 0 |
T13 | 287430 | 287346 | 0 | 0 |
T47 | 66102 | 66034 | 0 | 0 |
T48 | 1792 | 1703 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 212 | 212 | 0 | 0 |
OutputsKnown_A | 44141060 | 44108037 | 0 | 0 |
gen_flops.OutputDelay_A | 44141060 | 44106543 | 0 | 636 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212 | 212 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44108037 | 0 | 0 |
T1 | 158621 | 158541 | 0 | 0 |
T2 | 1303 | 1249 | 0 | 0 |
T3 | 1654 | 1574 | 0 | 0 |
T4 | 112268 | 111903 | 0 | 0 |
T5 | 87356 | 87297 | 0 | 0 |
T7 | 71641 | 71590 | 0 | 0 |
T8 | 130039 | 129908 | 0 | 0 |
T13 | 287430 | 287346 | 0 | 0 |
T47 | 66102 | 66034 | 0 | 0 |
T48 | 1792 | 1703 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44106543 | 0 | 636 |
T1 | 158621 | 158538 | 0 | 3 |
T2 | 1303 | 1246 | 0 | 3 |
T3 | 1654 | 1571 | 0 | 3 |
T4 | 112268 | 111888 | 0 | 3 |
T5 | 87356 | 87294 | 0 | 3 |
T7 | 71641 | 71587 | 0 | 3 |
T8 | 130039 | 129902 | 0 | 3 |
T13 | 287430 | 287343 | 0 | 3 |
T47 | 66102 | 66031 | 0 | 3 |
T48 | 1792 | 1700 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 212 | 212 | 0 | 0 |
OutputsKnown_A | 44141060 | 44108037 | 0 | 0 |
gen_no_flops.OutputDelay_A | 44141060 | 44108037 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212 | 212 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44108037 | 0 | 0 |
T1 | 158621 | 158541 | 0 | 0 |
T2 | 1303 | 1249 | 0 | 0 |
T3 | 1654 | 1574 | 0 | 0 |
T4 | 112268 | 111903 | 0 | 0 |
T5 | 87356 | 87297 | 0 | 0 |
T7 | 71641 | 71590 | 0 | 0 |
T8 | 130039 | 129908 | 0 | 0 |
T13 | 287430 | 287346 | 0 | 0 |
T47 | 66102 | 66034 | 0 | 0 |
T48 | 1792 | 1703 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44108037 | 0 | 0 |
T1 | 158621 | 158541 | 0 | 0 |
T2 | 1303 | 1249 | 0 | 0 |
T3 | 1654 | 1574 | 0 | 0 |
T4 | 112268 | 111903 | 0 | 0 |
T5 | 87356 | 87297 | 0 | 0 |
T7 | 71641 | 71590 | 0 | 0 |
T8 | 130039 | 129908 | 0 | 0 |
T13 | 287430 | 287346 | 0 | 0 |
T47 | 66102 | 66034 | 0 | 0 |
T48 | 1792 | 1703 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 212 | 212 | 0 | 0 |
OutputsKnown_A | 44141060 | 44108037 | 0 | 0 |
gen_no_flops.OutputDelay_A | 44141060 | 44108037 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 212 | 212 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44108037 | 0 | 0 |
T1 | 158621 | 158541 | 0 | 0 |
T2 | 1303 | 1249 | 0 | 0 |
T3 | 1654 | 1574 | 0 | 0 |
T4 | 112268 | 111903 | 0 | 0 |
T5 | 87356 | 87297 | 0 | 0 |
T7 | 71641 | 71590 | 0 | 0 |
T8 | 130039 | 129908 | 0 | 0 |
T13 | 287430 | 287346 | 0 | 0 |
T47 | 66102 | 66034 | 0 | 0 |
T48 | 1792 | 1703 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44141060 | 44108037 | 0 | 0 |
T1 | 158621 | 158541 | 0 | 0 |
T2 | 1303 | 1249 | 0 | 0 |
T3 | 1654 | 1574 | 0 | 0 |
T4 | 112268 | 111903 | 0 | 0 |
T5 | 87356 | 87297 | 0 | 0 |
T7 | 71641 | 71590 | 0 | 0 |
T8 | 130039 | 129908 | 0 | 0 |
T13 | 287430 | 287346 | 0 | 0 |
T47 | 66102 | 66034 | 0 | 0 |
T48 | 1792 | 1703 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |