Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	181220	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	519116	1		T7	4		T4	1		T6	10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	418607	1		T7	6		T6	1		T44	8
values[0x0]	132455	1		T7	5		T8	1		T4	2
values[0x1]	149274	1		T7	3		T4	3		T6	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	132402	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	567934	1		T7	5		T4	2		T6	14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2503	1		T12	1		T28	1		T155	1
valid_sources[0x01]	2755	1		T4	1		T71	127		T68	1
valid_sources[0x02]	2724	1		T42	1		T71	155		T68	1
valid_sources[0x03]	2612	1		T28	1		T13	1		T181	2
valid_sources[0x04]	2444	1		T71	116		T68	5		T65	18
valid_sources[0x05]	2554	1		T28	1		T182	1		T42	1
valid_sources[0x06]	3139	1		T28	1		T42	1		T181	1
valid_sources[0x07]	2575	1		T183	1		T71	124		T65	18
valid_sources[0x08]	2711	1		T77	1		T71	154		T68	2
valid_sources[0x09]	2548	1		T71	133		T68	1		T65	30
valid_sources[0x0a]	2931	1		T71	140		T65	29		T66	21
valid_sources[0x0b]	2551	1		T165	1		T163	7		T71	130
valid_sources[0x0c]	2321	1		T42	2		T71	133		T68	1
valid_sources[0x0d]	2668	1		T12	1		T184	14		T42	6
valid_sources[0x0e]	2503	1		T41	1		T71	116		T68	1
valid_sources[0x0f]	2469	1		T20	5		T42	1		T71	135
valid_sources[0x10]	2493	1		T41	1		T163	4		T71	156
valid_sources[0x11]	2707	1		T185	1		T165	1		T71	137
valid_sources[0x12]	2482	1		T13	1		T42	1		T71	152
valid_sources[0x13]	3209	1		T29	6		T41	2		T71	147
valid_sources[0x14]	2525	1		T17	1		T186	4		T71	109
valid_sources[0x15]	2507	1		T165	2		T71	138		T68	2
valid_sources[0x16]	2973	1		T162	2		T71	149		T65	20
valid_sources[0x17]	2620	1		T28	1		T162	1		T181	1
valid_sources[0x18]	3302	1		T28	1		T185	1		T71	110
valid_sources[0x19]	2408	1		T41	1		T165	1		T26	1
valid_sources[0x1a]	3876	1		T28	1		T71	134		T65	23
valid_sources[0x1b]	2651	1		T71	114		T68	1		T65	28
valid_sources[0x1c]	2840	1		T41	3		T42	1		T71	147
valid_sources[0x1d]	2898	1		T43	11		T14	1		T42	1
valid_sources[0x1e]	2666	1		T42	2		T183	1		T71	156
valid_sources[0x1f]	3562	1		T185	1		T71	119		T68	4
valid_sources[0x20]	2679	1		T77	2		T42	1		T71	151
valid_sources[0x21]	2502	1		T6	3		T157	1		T165	2
valid_sources[0x22]	3100	1		T187	2		T71	123		T68	3
valid_sources[0x23]	3216	1		T41	1		T42	1		T188	2
valid_sources[0x24]	3749	1		T71	121		T65	23		T69	5
valid_sources[0x25]	2738	1		T28	1		T162	1		T71	141
valid_sources[0x26]	2760	1		T28	1		T165	1		T17	1
valid_sources[0x27]	2735	1		T71	113		T68	1		T65	16
valid_sources[0x28]	2548	1		T185	2		T71	121		T68	2
valid_sources[0x29]	3022	1		T71	140		T68	1		T65	22
valid_sources[0x2a]	2744	1		T41	3		T71	135		T68	3
valid_sources[0x2b]	2652	1		T185	1		T163	1		T17	1
valid_sources[0x2c]	2602	1		T181	2		T71	129		T65	17
valid_sources[0x2d]	2772	1		T42	1		T17	1		T71	141
valid_sources[0x2e]	2657	1		T12	1		T28	1		T185	1
valid_sources[0x2f]	2671	1		T42	2		T181	1		T71	139
valid_sources[0x30]	2562	1		T41	2		T71	134		T65	14
valid_sources[0x31]	2380	1		T28	2		T14	1		T71	123
valid_sources[0x32]	2756	1		T8	1		T93	5		T185	1
valid_sources[0x33]	2958	1		T181	1		T71	135		T68	1
valid_sources[0x34]	2494	1		T183	2		T71	149		T65	28
valid_sources[0x35]	2401	1		T5	1		T6	2		T71	135
valid_sources[0x36]	2606	1		T71	131		T65	30		T69	1
valid_sources[0x37]	2969	1		T42	1		T163	1		T23	7
valid_sources[0x38]	2794	1		T162	2		T42	1		T18	29
valid_sources[0x39]	2795	1		T71	123		T68	3		T65	19
valid_sources[0x3a]	2512	1		T28	1		T162	1		T21	2
valid_sources[0x3b]	2799	1		T28	1		T25	2		T150	1
valid_sources[0x3c]	2487	1		T181	1		T71	138		T68	2
valid_sources[0x3d]	2438	1		T14	1		T21	1		T41	1
valid_sources[0x3e]	2788	1		T157	2		T165	1		T42	1
valid_sources[0x3f]	2531	1		T28	1		T14	1		T21	1
valid_sources[0x40]	2661	1		T185	1		T157	1		T42	1
valid_sources[0x41]	2519	1		T42	1		T71	141		T68	5
valid_sources[0x42]	2547	1		T41	1		T165	1		T167	1
valid_sources[0x43]	2525	1		T71	132		T68	5		T65	14
valid_sources[0x44]	2349	1		T28	1		T21	1		T71	149
valid_sources[0x45]	3471	1		T28	1		T185	1		T71	130
valid_sources[0x46]	2541	1		T71	124		T68	1		T65	23
valid_sources[0x47]	2715	1		T162	1		T150	2		T71	143
valid_sources[0x48]	2703	1		T77	2		T165	1		T42	1
valid_sources[0x49]	2681	1		T185	1		T42	3		T17	1
valid_sources[0x4a]	2450	1		T12	1		T71	130		T68	1
valid_sources[0x4b]	2466	1		T6	1		T71	130		T68	2
valid_sources[0x4c]	2823	1		T44	2		T12	2		T71	143
valid_sources[0x4d]	2608	1		T185	1		T21	1		T71	149
valid_sources[0x4e]	2699	1		T6	1		T28	2		T165	1
valid_sources[0x4f]	2614	1		T165	1		T42	2		T71	128
valid_sources[0x50]	2543	1		T71	139		T68	2		T65	19
valid_sources[0x51]	2994	1		T6	2		T12	7		T93	7
valid_sources[0x52]	2630	1		T13	1		T71	129		T68	4
valid_sources[0x53]	2598	1		T93	1		T42	1		T163	10
valid_sources[0x54]	2546	1		T13	1		T71	133		T68	2
valid_sources[0x55]	2631	1		T12	1		T41	5		T17	1
valid_sources[0x56]	2495	1		T77	1		T28	1		T21	1
valid_sources[0x57]	2475	1		T42	1		T71	134		T65	23
valid_sources[0x58]	2837	1		T41	3		T165	1		T42	1
valid_sources[0x59]	2709	1		T167	1		T71	121		T68	1
valid_sources[0x5a]	2627	1		T44	2		T41	1		T26	1
valid_sources[0x5b]	2700	1		T41	1		T145	2		T71	142
valid_sources[0x5c]	2645	1		T162	1		T17	3		T181	1
valid_sources[0x5d]	2965	1		T21	1		T181	1		T71	124
valid_sources[0x5e]	2949	1		T4	1		T71	134		T65	26
valid_sources[0x5f]	2878	1		T71	150		T65	18		T69	2
valid_sources[0x60]	2591	1		T28	1		T165	1		T42	1
valid_sources[0x61]	2654	1		T185	1		T41	3		T71	160
valid_sources[0x62]	2812	1		T12	1		T71	138		T68	1
valid_sources[0x63]	2495	1		T13	1		T42	1		T150	1
valid_sources[0x64]	2638	1		T181	1		T71	124		T65	16
valid_sources[0x65]	2731	1		T162	1		T41	1		T42	1
valid_sources[0x66]	2889	1		T41	1		T42	1		T71	134
valid_sources[0x67]	2967	1		T182	1		T71	139		T65	28
valid_sources[0x68]	2358	1		T162	2		T71	134		T68	1
valid_sources[0x69]	2839	1		T41	1		T165	1		T71	135
valid_sources[0x6a]	2910	1		T14	2		T150	2		T71	140
valid_sources[0x6b]	2945	1		T185	1		T157	1		T41	1
valid_sources[0x6c]	2671	1		T185	1		T42	2		T181	1
valid_sources[0x6d]	2616	1		T7	1		T41	1		T71	116
valid_sources[0x6e]	2996	1		T189	13		T71	124		T68	2
valid_sources[0x6f]	2680	1		T185	1		T165	1		T181	1
valid_sources[0x70]	2750	1		T28	1		T14	2		T41	1
valid_sources[0x71]	2375	1		T71	122		T68	1		T65	19
valid_sources[0x72]	2969	1		T71	140		T68	4		T65	22
valid_sources[0x73]	2598	1		T6	1		T12	1		T181	1
valid_sources[0x74]	2899	1		T42	1		T71	107		T68	1
valid_sources[0x75]	2712	1		T28	1		T42	1		T155	1
valid_sources[0x76]	2728	1		T157	2		T71	128		T68	3
valid_sources[0x77]	2573	1		T62	3		T71	127		T68	1
valid_sources[0x78]	2640	1		T157	1		T190	17		T71	138
valid_sources[0x79]	2460	1		T7	1		T71	123		T65	25
valid_sources[0x7a]	2859	1		T19	6		T42	1		T71	143
valid_sources[0x7b]	2877	1		T162	1		T41	3		T165	1
valid_sources[0x7c]	2604	1		T165	1		T42	1		T26	1
valid_sources[0x7d]	3112	1		T185	1		T71	149		T65	23
valid_sources[0x7e]	2777	1		T189	22		T71	146		T68	1
valid_sources[0x7f]	2834	1		T71	142		T65	31		T69	3
valid_sources[0x80]	2911	1		T155	1		T71	123		T68	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

260295

1

T7

3

T6

1

T44

5

values[0x0]

all_enables

biggest_size

129467

1

T7

1

T4

1

T6

4

values[0x1]

all_enables

biggest_size

129354

1

T6

5

T34

1

T77

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5588	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	43281	1		T1	4		T2	3		T10	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15794	1		T71	192		T68	45		T65	36
values[0x0]	16382	1		T1	3		T2	5		T10	1
values[0x1]	16693	1		T1	1		T2	6		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4046	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	44823	1		T1	4		T2	5		T10	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	299	1		T4	4		T28	1		T191	1
valid_sources[0x01]	201	1		T23	2		T68	1		T65	2
valid_sources[0x02]	232	1		T147	1		T192	1		T193	1
valid_sources[0x03]	251	1		T134	1		T138	3		T68	1
valid_sources[0x04]	205	1		T68	1		T69	3		T86	1
valid_sources[0x05]	142	1		T148	1		T71	2		T86	1
valid_sources[0x06]	255	1		T69	7		T67	1		T95	4
valid_sources[0x07]	176	1		T75	1		T194	1		T181	1
valid_sources[0x08]	186	1		T146	1		T71	1		T68	1
valid_sources[0x09]	162	1		T195	1		T23	1		T68	1
valid_sources[0x0a]	189	1		T162	1		T196	1		T197	1
valid_sources[0x0b]	178	1		T135	1		T198	1		T153	1
valid_sources[0x0c]	192	1		T199	1		T200	1		T86	1
valid_sources[0x0d]	220	1		T168	1		T152	1		T18	1
valid_sources[0x0e]	145	1		T65	2		T86	1		T95	1
valid_sources[0x0f]	169	1		T201	2		T202	1		T71	2
valid_sources[0x10]	247	1		T57	1		T161	4		T203	1
valid_sources[0x11]	159	1		T93	6		T204	1		T68	1
valid_sources[0x12]	186	1		T68	1		T95	4		T96	2
valid_sources[0x13]	217	1		T195	1		T205	1		T206	4
valid_sources[0x14]	167	1		T18	1		T68	2		T95	1
valid_sources[0x15]	179	1		T60	11		T37	2		T32	1
valid_sources[0x16]	171	1		T160	1		T68	1		T86	2
valid_sources[0x17]	188	1		T19	1		T207	1		T86	1
valid_sources[0x18]	200	1		T204	1		T208	7		T65	1
valid_sources[0x19]	169	1		T133	1		T86	2		T67	1
valid_sources[0x1a]	341	1		T209	1		T17	1		T210	1
valid_sources[0x1b]	238	1		T35	1		T131	13		T211	13
valid_sources[0x1c]	163	1		T148	1		T135	1		T95	3
valid_sources[0x1d]	220	1		T36	3		T210	1		T193	1
valid_sources[0x1e]	161	1		T71	3		T68	2		T65	3
valid_sources[0x1f]	198	1		T201	3		T205	1		T68	1
valid_sources[0x20]	185	1		T69	3		T86	2		T95	3
valid_sources[0x21]	565	1		T212	1		T44	1		T62	1
valid_sources[0x22]	149	1		T88	1		T19	1		T204	1
valid_sources[0x23]	194	1		T87	1		T132	1		T213	1
valid_sources[0x24]	170	1		T36	1		T37	1		T63	2
valid_sources[0x25]	163	1		T143	1		T29	2		T15	1
valid_sources[0x26]	170	1		T201	2		T214	1		T23	1
valid_sources[0x27]	174	1		T151	5		T215	1		T86	3
valid_sources[0x28]	184	1		T216	1		T217	2		T68	1
valid_sources[0x29]	166	1		T187	1		T71	5		T86	2
valid_sources[0x2a]	184	1		T30	1		T15	1		T218	1
valid_sources[0x2b]	183	1		T148	1		T37	1		T68	2
valid_sources[0x2c]	182	1		T219	1		T162	1		T165	2
valid_sources[0x2d]	162	1		T4	1		T95	3		T96	2
valid_sources[0x2e]	246	1		T153	6		T220	1		T165	1
valid_sources[0x2f]	169	1		T165	1		T68	2		T86	2
valid_sources[0x30]	221	1		T147	1		T185	8		T221	1
valid_sources[0x31]	168	1		T71	3		T69	7		T86	2
valid_sources[0x32]	209	1		T71	3		T68	2		T94	1
valid_sources[0x33]	235	1		T219	1		T45	1		T71	10
valid_sources[0x34]	173	1		T29	3		T210	2		T68	1
valid_sources[0x35]	172	1		T222	7		T68	1		T86	1
valid_sources[0x36]	195	1		T223	1		T86	2		T95	2
valid_sources[0x37]	172	1		T219	1		T71	1		T68	1
valid_sources[0x38]	235	1		T220	1		T71	3		T86	3
valid_sources[0x39]	161	1		T21	1		T68	1		T86	1
valid_sources[0x3a]	118	1		T11	1		T190	4		T66	1
valid_sources[0x3b]	191	1		T68	1		T65	2		T86	1
valid_sources[0x3c]	200	1		T205	1		T181	1		T86	3
valid_sources[0x3d]	181	1		T68	3		T66	2		T94	1
valid_sources[0x3e]	207	1		T37	1		T224	6		T86	1
valid_sources[0x3f]	186	1		T30	1		T133	1		T159	1
valid_sources[0x40]	146	1		T135	3		T15	1		T187	1
valid_sources[0x41]	151	1		T67	2		T95	2		T96	3
valid_sources[0x42]	204	1		T28	1		T71	1		T86	4
valid_sources[0x43]	195	1		T225	2		T68	1		T86	2
valid_sources[0x44]	188	1		T35	2		T63	1		T200	1
valid_sources[0x45]	214	1		T6	6		T135	4		T144	3
valid_sources[0x46]	183	1		T75	1		T226	1		T68	2
valid_sources[0x47]	203	1		T59	1		T37	1		T227	1
valid_sources[0x48]	186	1		T147	1		T158	4		T66	1
valid_sources[0x49]	207	1		T36	1		T143	1		T204	1
valid_sources[0x4a]	193	1		T228	1		T229	1		T71	2
valid_sources[0x4b]	221	1		T8	1		T148	1		T195	1
valid_sources[0x4c]	193	1		T132	1		T75	1		T165	1
valid_sources[0x4d]	167	1		T227	1		T230	1		T71	3
valid_sources[0x4e]	192	1		T43	1		T65	7		T67	1
valid_sources[0x4f]	147	1		T134	1		T231	1		T68	1
valid_sources[0x50]	175	1		T220	2		T16	3		T71	5
valid_sources[0x51]	189	1		T232	1		T233	4		T71	1
valid_sources[0x52]	218	1		T86	1		T95	3		T99	2
valid_sources[0x53]	183	1		T234	1		T68	1		T69	2
valid_sources[0x54]	186	1		T235	5		T71	13		T68	5
valid_sources[0x55]	165	1		T14	4		T181	1		T236	1
valid_sources[0x56]	194	1		T219	1		T42	1		T193	1
valid_sources[0x57]	144	1		T30	1		T156	1		T219	1
valid_sources[0x58]	166	1		T57	2		T34	1		T77	1
valid_sources[0x59]	202	1		T143	1		T237	1		T71	7
valid_sources[0x5a]	207	1		T74	1		T85	1		T71	12
valid_sources[0x5b]	156	1		T238	1		T71	5		T95	1
valid_sources[0x5c]	205	1		T239	7		T86	3		T67	2
valid_sources[0x5d]	194	1		T29	1		T201	1		T69	14
valid_sources[0x5e]	310	1		T162	1		T220	1		T68	1
valid_sources[0x5f]	180	1		T71	2		T68	1		T86	1
valid_sources[0x60]	174	1		T71	4		T86	1		T67	1
valid_sources[0x61]	162	1		T18	1		T71	3		T86	3
valid_sources[0x62]	168	1		T86	3		T70	9		T67	4
valid_sources[0x63]	242	1		T133	3		T37	1		T220	1
valid_sources[0x64]	171	1		T133	2		T19	1		T159	2
valid_sources[0x65]	173	1		T193	1		T86	3		T70	1
valid_sources[0x66]	201	1		T135	1		T138	1		T162	1
valid_sources[0x67]	206	1		T7	1		T61	1		T200	1
valid_sources[0x68]	187	1		T2	11		T139	10		T149	1
valid_sources[0x69]	228	1		T29	1		T66	1		T86	1
valid_sources[0x6a]	174	1		T147	1		T138	3		T220	1
valid_sources[0x6b]	173	1		T142	1		T19	1		T159	1
valid_sources[0x6c]	164	1		T193	1		T68	1		T67	1
valid_sources[0x6d]	150	1		T86	1		T67	4		T95	2
valid_sources[0x6e]	165	1		T57	1		T184	1		T150	2
valid_sources[0x6f]	155	1		T167	1		T66	2		T86	1
valid_sources[0x70]	179	1		T148	1		T147	1		T71	2
valid_sources[0x71]	153	1		T47	1		T134	1		T240	1
valid_sources[0x72]	150	1		T227	1		T96	1		T99	3
valid_sources[0x73]	298	1		T10	1		T28	2		T41	1
valid_sources[0x74]	159	1		T221	1		T86	2		T67	1
valid_sources[0x75]	203	1		T148	1		T86	1		T95	2
valid_sources[0x76]	153	1		T1	1		T147	1		T204	1
valid_sources[0x77]	194	1		T68	1		T86	5		T67	2
valid_sources[0x78]	168	1		T195	1		T16	2		T17	1
valid_sources[0x79]	171	1		T35	1		T71	2		T69	4
valid_sources[0x7a]	172	1		T1	1		T200	1		T216	1
valid_sources[0x7b]	143	1		T75	1		T150	2		T68	1
valid_sources[0x7c]	178	1		T37	1		T24	2		T71	3
valid_sources[0x7d]	199	1		T68	1		T86	1		T67	1
valid_sources[0x7e]	212	1		T241	3		T86	1		T95	1
valid_sources[0x7f]	182	1		T224	1		T68	2		T86	1
valid_sources[0x80]	168	1		T95	3		T96	3		T99	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

12574

1

T71

85

T68

40

T65

16

values[0x0]

all_enables

biggest_size

15645

1

T1

3

T2

3

T10

1

values[0x1]

all_enables

biggest_size

15062

1

T1

1

T11

3

T7

1