Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 315224 1 T7 10 T8 1 T4 4
full_word 523973 1 T7 4 T4 1 T6 10



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 838877 1 T7 14 T8 1 T4 5
auto[TlIntgErrCmd] 113 1 T65 4 T66 5 T67 6
auto[TlIntgErrData] 102 1 T65 3 T66 3 T67 6
auto[TlIntgErrBoth] 105 1 T65 3 T66 2 T67 8



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 424444 1 T7 6 T6 1 T44 8
auto[1] 414753 1 T7 8 T8 1 T4 5



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 163486 1 T7 3 T44 3 T12 2
auto[TlIntgErrNone] partial auto[1] 151440 1 T7 7 T8 1 T4 4
auto[TlIntgErrNone] full_word auto[0] 260808 1 T7 3 T6 1 T44 5
auto[TlIntgErrNone] full_word auto[1] 263143 1 T7 1 T4 1 T6 9
auto[TlIntgErrCmd] partial auto[0] 38 1 T66 3 T67 3 T92 1
auto[TlIntgErrCmd] partial auto[1] 65 1 T65 3 T66 2 T67 3
auto[TlIntgErrCmd] full_word auto[0] 5 1 T65 1 T171 2 T172 1
auto[TlIntgErrCmd] full_word auto[1] 5 1 T170 1 T173 1 T174 1
auto[TlIntgErrData] partial auto[0] 52 1 T65 1 T66 2 T67 2
auto[TlIntgErrData] partial auto[1] 45 1 T65 1 T66 1 T67 2
auto[TlIntgErrData] full_word auto[0] 3 1 T67 2 T171 1 - -
auto[TlIntgErrData] full_word auto[1] 2 1 T65 1 T175 1 - -
auto[TlIntgErrBoth] partial auto[0] 48 1 T65 3 T66 1 T67 3
auto[TlIntgErrBoth] partial auto[1] 50 1 T66 1 T67 5 T92 5
auto[TlIntgErrBoth] full_word auto[0] 4 1 T176 1 T177 1 T178 1
auto[TlIntgErrBoth] full_word auto[1] 3 1 T137 1 T179 1 T180 1

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