Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.35 100.00 76.60 92.63 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 116975156 45476 0 0
late_debug_enable_rd_A 116975156 12423 0 0
late_debug_enable_regwen_rd_A 116975156 11239 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 116975156 45476 0 0
T65 49258 4 0 0
T66 22679 3 0 0
T67 96483 7 0 0
T68 22646 395 0 0
T69 8864 429 0 0
T80 268012 1397 0 0
T86 20199 573 0 0
T89 7454 586 0 0
T90 7137 61 0 0
T91 3555 82 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 116975156 12423 0 0
T70 22752 16 0 0
T81 210931 530 0 0
T96 250063 154 0 0
T100 9994 11 0 0
T101 22749 3 0 0
T102 392092 62 0 0
T108 39553 67 0 0
T125 22167 24 0 0
T136 10904 10 0 0
T137 46470 37 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 116975156 11239 0 0
T70 22752 7 0 0
T81 210931 444 0 0
T96 250063 141 0 0
T100 9994 6 0 0
T101 22749 17 0 0
T102 392092 73 0 0
T108 39553 40 0 0
T125 22167 21 0 0
T136 10904 17 0 0
T137 46470 38 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%