SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 218 | 218 | 0 | 0 |
OutputsKnown_A | 42241229 | 42202199 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 42241229 | 42200429 | 0 | 654 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 218 | 218 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42202199 | 0 | 0 |
T1 | 117278 | 117029 | 0 | 0 |
T2 | 2395 | 2338 | 0 | 0 |
T3 | 1340 | 1263 | 0 | 0 |
T7 | 126691 | 126624 | 0 | 0 |
T10 | 84849 | 84770 | 0 | 0 |
T11 | 153658 | 153371 | 0 | 0 |
T30 | 11426 | 11079 | 0 | 0 |
T47 | 500814 | 500735 | 0 | 0 |
T48 | 197806 | 197745 | 0 | 0 |
T49 | 55490 | 55436 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42200429 | 0 | 654 |
T1 | 117278 | 117017 | 0 | 3 |
T2 | 2395 | 2335 | 0 | 3 |
T3 | 1340 | 1260 | 0 | 3 |
T7 | 126691 | 126621 | 0 | 3 |
T10 | 84849 | 84767 | 0 | 3 |
T11 | 153658 | 153356 | 0 | 3 |
T30 | 11426 | 11064 | 0 | 3 |
T47 | 500814 | 500732 | 0 | 3 |
T48 | 197806 | 197742 | 0 | 3 |
T49 | 55490 | 55433 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |