Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	100.00	100.00					100.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm_enable_checker

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
36	1	1

---

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	42241229	4549907	0	0
MemTLResponseWithoutDebugIsError_A	42241229	5	0	0
NdmResetAckNeedsDebug_A	42241229	16	0	0
SbaTLRequestNeedsDebug_A	42241229	8714	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42241229	4549907	0	0
T4	0	50658	0	0
T5	0	5516	0	0
T6	0	77309	0	0
T7	126691	61139	0	0
T8	0	4886	0	0
T9	9177	4905	0	0
T12	0	263961	0	0
T19	0	52846	0	0
T30	11426	0	0	0
T35	123173	0	0	0
T38	19846	0	0	0
T44	0	23196	0	0
T47	500814	0	0	0
T48	197806	0	0	0
T49	55490	0	0	0
T64	530141	0	0	0
T77	0	7406	0	0
T88	301369	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42241229	5	0	0
T19	105082	0	0	0
T39	13669	0	0	0
T61	0	2	0	0
T62	2320	3	0	0
T138	3436	0	0	0
T139	4400	0	0	0
T140	3896	0	0	0
T141	867810	0	0	0
T142	276171	0	0	0
T143	196565	0	0	0
T144	497683	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42241229	16	0	0
T6	176275	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T18	0	1	0	0
T25	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T34	20451	1	0	0
T36	37278	0	0	0
T44	31915	0	0	0
T51	23358	0	0	0
T74	215347	0	0	0
T75	55191	0	0	0
T76	164001	0	0	0
T77	8587	0	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	2426	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42241229	8714	0	0
T1	117278	63	0	0
T2	2395	0	0	0
T3	1340	0	0	0
T7	126691	0	0	0
T10	84849	113	0	0
T11	153658	40	0	0
T30	11426	9	0	0
T35	0	83	0	0
T47	500814	112	0	0
T48	197806	138	0	0
T49	55490	20	0	0
T64	0	49	0	0
T88	0	59	0	0