Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
8023753 |
8022445 |
0 |
0 |
selKnown1 |
48063998 |
48062690 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8023753 |
8022445 |
0 |
0 |
T1 |
30444 |
30440 |
0 |
0 |
T2 |
552 |
548 |
0 |
0 |
T3 |
1244 |
1240 |
0 |
0 |
T4 |
0 |
18 |
0 |
0 |
T6 |
0 |
8 |
0 |
0 |
T7 |
4928 |
4924 |
0 |
0 |
T10 |
29087 |
29083 |
0 |
0 |
T11 |
12302 |
12298 |
0 |
0 |
T30 |
17477 |
17473 |
0 |
0 |
T35 |
0 |
14 |
0 |
0 |
T47 |
29558 |
29554 |
0 |
0 |
T48 |
34157 |
34153 |
0 |
0 |
T49 |
23018 |
23014 |
0 |
0 |
T51 |
0 |
40 |
0 |
0 |
T56 |
0 |
6 |
0 |
0 |
T57 |
0 |
6 |
0 |
0 |
T58 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
48063998 |
48062690 |
0 |
0 |
T1 |
132504 |
132500 |
0 |
0 |
T2 |
2672 |
2668 |
0 |
0 |
T3 |
1963 |
1959 |
0 |
0 |
T4 |
0 |
8 |
0 |
0 |
T6 |
0 |
6 |
0 |
0 |
T7 |
129156 |
129152 |
0 |
0 |
T10 |
99393 |
99389 |
0 |
0 |
T11 |
159814 |
159810 |
0 |
0 |
T30 |
20169 |
20165 |
0 |
0 |
T35 |
0 |
14 |
0 |
0 |
T47 |
515594 |
515590 |
0 |
0 |
T48 |
214885 |
214881 |
0 |
0 |
T49 |
67000 |
66996 |
0 |
0 |
T51 |
0 |
40 |
0 |
0 |
T56 |
0 |
6 |
0 |
0 |
T57 |
0 |
6 |
0 |
0 |
T58 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2200528 |
2200310 |
0 |
0 |
selKnown1 |
42241229 |
42241011 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2200528 |
2200310 |
0 |
0 |
T1 |
15218 |
15217 |
0 |
0 |
T2 |
275 |
274 |
0 |
0 |
T3 |
621 |
620 |
0 |
0 |
T7 |
2463 |
2462 |
0 |
0 |
T10 |
14542 |
14541 |
0 |
0 |
T11 |
6146 |
6145 |
0 |
0 |
T30 |
8733 |
8732 |
0 |
0 |
T47 |
14778 |
14777 |
0 |
0 |
T48 |
17077 |
17076 |
0 |
0 |
T49 |
11508 |
11507 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
42241229 |
42241011 |
0 |
0 |
T1 |
117278 |
117277 |
0 |
0 |
T2 |
2395 |
2394 |
0 |
0 |
T3 |
1340 |
1339 |
0 |
0 |
T7 |
126691 |
126690 |
0 |
0 |
T10 |
84849 |
84848 |
0 |
0 |
T11 |
153658 |
153657 |
0 |
0 |
T30 |
11426 |
11425 |
0 |
0 |
T47 |
500814 |
500813 |
0 |
0 |
T48 |
197806 |
197805 |
0 |
0 |
T49 |
55490 |
55489 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
617 |
399 |
0 |
0 |
T1 |
4 |
3 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
0 |
6 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
5 |
4 |
0 |
0 |
T30 |
5 |
4 |
0 |
0 |
T35 |
0 |
7 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T51 |
0 |
20 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
T57 |
0 |
3 |
0 |
0 |
T58 |
0 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
590 |
372 |
0 |
0 |
T1 |
4 |
3 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
0 |
4 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
5 |
4 |
0 |
0 |
T30 |
5 |
4 |
0 |
0 |
T35 |
0 |
7 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T51 |
0 |
20 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
T57 |
0 |
3 |
0 |
0 |
T58 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
5820631 |
5820195 |
0 |
0 |
selKnown1 |
5820429 |
5819993 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5820631 |
5820195 |
0 |
0 |
T1 |
15218 |
15217 |
0 |
0 |
T2 |
275 |
274 |
0 |
0 |
T3 |
621 |
620 |
0 |
0 |
T7 |
2463 |
2462 |
0 |
0 |
T10 |
14543 |
14542 |
0 |
0 |
T11 |
6146 |
6145 |
0 |
0 |
T30 |
8734 |
8733 |
0 |
0 |
T47 |
14778 |
14777 |
0 |
0 |
T48 |
17078 |
17077 |
0 |
0 |
T49 |
11508 |
11507 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5820429 |
5819993 |
0 |
0 |
T1 |
15218 |
15217 |
0 |
0 |
T2 |
275 |
274 |
0 |
0 |
T3 |
621 |
620 |
0 |
0 |
T7 |
2463 |
2462 |
0 |
0 |
T10 |
14542 |
14541 |
0 |
0 |
T11 |
6146 |
6145 |
0 |
0 |
T30 |
8733 |
8732 |
0 |
0 |
T47 |
14778 |
14777 |
0 |
0 |
T48 |
17077 |
17076 |
0 |
0 |
T49 |
11508 |
11507 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1977 |
1541 |
0 |
0 |
selKnown1 |
1750 |
1314 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1977 |
1541 |
0 |
0 |
T1 |
4 |
3 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
0 |
12 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
5 |
4 |
0 |
0 |
T30 |
5 |
4 |
0 |
0 |
T35 |
0 |
7 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T51 |
0 |
20 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
T57 |
0 |
3 |
0 |
0 |
T58 |
0 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1750 |
1314 |
0 |
0 |
T1 |
4 |
3 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
0 |
4 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
5 |
4 |
0 |
0 |
T30 |
5 |
4 |
0 |
0 |
T35 |
0 |
7 |
0 |
0 |
T47 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T49 |
1 |
0 |
0 |
0 |
T51 |
0 |
20 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
T57 |
0 |
3 |
0 |
0 |
T58 |
0 |
2 |
0 |
0 |