SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
79.81 | 98.04 | 77.78 | 85.71 | 87.50 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1308 | 1308 | 0 | 0 |
OutputsKnown_A | 253447374 | 253213194 | 0 | 0 |
gen_flops.OutputDelay_A | 126723687 | 126601287 | 0 | 1962 |
gen_no_flops.OutputDelay_A | 126723687 | 126606597 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1308 | 1308 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T10 | 6 | 6 | 0 | 0 |
T11 | 6 | 6 | 0 | 0 |
T30 | 6 | 6 | 0 | 0 |
T47 | 6 | 6 | 0 | 0 |
T48 | 6 | 6 | 0 | 0 |
T49 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 253447374 | 253213194 | 0 | 0 |
T1 | 703668 | 702174 | 0 | 0 |
T2 | 14370 | 14028 | 0 | 0 |
T3 | 8040 | 7578 | 0 | 0 |
T7 | 760146 | 759744 | 0 | 0 |
T10 | 509094 | 508620 | 0 | 0 |
T11 | 921948 | 920226 | 0 | 0 |
T30 | 68556 | 66474 | 0 | 0 |
T47 | 3004884 | 3004410 | 0 | 0 |
T48 | 1186836 | 1186470 | 0 | 0 |
T49 | 332940 | 332616 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 126723687 | 126601287 | 0 | 1962 |
T1 | 351834 | 351051 | 0 | 9 |
T2 | 7185 | 7005 | 0 | 9 |
T3 | 4020 | 3780 | 0 | 9 |
T7 | 380073 | 379863 | 0 | 9 |
T10 | 254547 | 254301 | 0 | 9 |
T11 | 460974 | 460068 | 0 | 9 |
T30 | 34278 | 33192 | 0 | 9 |
T47 | 1502442 | 1502196 | 0 | 9 |
T48 | 593418 | 593226 | 0 | 9 |
T49 | 166470 | 166299 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 126723687 | 126606597 | 0 | 0 |
T1 | 351834 | 351087 | 0 | 0 |
T2 | 7185 | 7014 | 0 | 0 |
T3 | 4020 | 3789 | 0 | 0 |
T7 | 380073 | 379872 | 0 | 0 |
T10 | 254547 | 254310 | 0 | 0 |
T11 | 460974 | 460113 | 0 | 0 |
T30 | 34278 | 33237 | 0 | 0 |
T47 | 1502442 | 1502205 | 0 | 0 |
T48 | 593418 | 593235 | 0 | 0 |
T49 | 166470 | 166308 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 218 | 218 | 0 | 0 |
OutputsKnown_A | 42241229 | 42202199 | 0 | 0 |
gen_flops.OutputDelay_A | 42241229 | 42200429 | 0 | 654 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 218 | 218 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42202199 | 0 | 0 |
T1 | 117278 | 117029 | 0 | 0 |
T2 | 2395 | 2338 | 0 | 0 |
T3 | 1340 | 1263 | 0 | 0 |
T7 | 126691 | 126624 | 0 | 0 |
T10 | 84849 | 84770 | 0 | 0 |
T11 | 153658 | 153371 | 0 | 0 |
T30 | 11426 | 11079 | 0 | 0 |
T47 | 500814 | 500735 | 0 | 0 |
T48 | 197806 | 197745 | 0 | 0 |
T49 | 55490 | 55436 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42200429 | 0 | 654 |
T1 | 117278 | 117017 | 0 | 3 |
T2 | 2395 | 2335 | 0 | 3 |
T3 | 1340 | 1260 | 0 | 3 |
T7 | 126691 | 126621 | 0 | 3 |
T10 | 84849 | 84767 | 0 | 3 |
T11 | 153658 | 153356 | 0 | 3 |
T30 | 11426 | 11064 | 0 | 3 |
T47 | 500814 | 500732 | 0 | 3 |
T48 | 197806 | 197742 | 0 | 3 |
T49 | 55490 | 55433 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 218 | 218 | 0 | 0 |
OutputsKnown_A | 42241229 | 42202199 | 0 | 0 |
gen_flops.OutputDelay_A | 42241229 | 42200429 | 0 | 654 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 218 | 218 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42202199 | 0 | 0 |
T1 | 117278 | 117029 | 0 | 0 |
T2 | 2395 | 2338 | 0 | 0 |
T3 | 1340 | 1263 | 0 | 0 |
T7 | 126691 | 126624 | 0 | 0 |
T10 | 84849 | 84770 | 0 | 0 |
T11 | 153658 | 153371 | 0 | 0 |
T30 | 11426 | 11079 | 0 | 0 |
T47 | 500814 | 500735 | 0 | 0 |
T48 | 197806 | 197745 | 0 | 0 |
T49 | 55490 | 55436 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42200429 | 0 | 654 |
T1 | 117278 | 117017 | 0 | 3 |
T2 | 2395 | 2335 | 0 | 3 |
T3 | 1340 | 1260 | 0 | 3 |
T7 | 126691 | 126621 | 0 | 3 |
T10 | 84849 | 84767 | 0 | 3 |
T11 | 153658 | 153356 | 0 | 3 |
T30 | 11426 | 11064 | 0 | 3 |
T47 | 500814 | 500732 | 0 | 3 |
T48 | 197806 | 197742 | 0 | 3 |
T49 | 55490 | 55433 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 218 | 218 | 0 | 0 |
OutputsKnown_A | 42241229 | 42202199 | 0 | 0 |
gen_no_flops.OutputDelay_A | 42241229 | 42202199 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 218 | 218 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42202199 | 0 | 0 |
T1 | 117278 | 117029 | 0 | 0 |
T2 | 2395 | 2338 | 0 | 0 |
T3 | 1340 | 1263 | 0 | 0 |
T7 | 126691 | 126624 | 0 | 0 |
T10 | 84849 | 84770 | 0 | 0 |
T11 | 153658 | 153371 | 0 | 0 |
T30 | 11426 | 11079 | 0 | 0 |
T47 | 500814 | 500735 | 0 | 0 |
T48 | 197806 | 197745 | 0 | 0 |
T49 | 55490 | 55436 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42202199 | 0 | 0 |
T1 | 117278 | 117029 | 0 | 0 |
T2 | 2395 | 2338 | 0 | 0 |
T3 | 1340 | 1263 | 0 | 0 |
T7 | 126691 | 126624 | 0 | 0 |
T10 | 84849 | 84770 | 0 | 0 |
T11 | 153658 | 153371 | 0 | 0 |
T30 | 11426 | 11079 | 0 | 0 |
T47 | 500814 | 500735 | 0 | 0 |
T48 | 197806 | 197745 | 0 | 0 |
T49 | 55490 | 55436 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 218 | 218 | 0 | 0 |
OutputsKnown_A | 42241229 | 42202199 | 0 | 0 |
gen_flops.OutputDelay_A | 42241229 | 42200429 | 0 | 654 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 218 | 218 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42202199 | 0 | 0 |
T1 | 117278 | 117029 | 0 | 0 |
T2 | 2395 | 2338 | 0 | 0 |
T3 | 1340 | 1263 | 0 | 0 |
T7 | 126691 | 126624 | 0 | 0 |
T10 | 84849 | 84770 | 0 | 0 |
T11 | 153658 | 153371 | 0 | 0 |
T30 | 11426 | 11079 | 0 | 0 |
T47 | 500814 | 500735 | 0 | 0 |
T48 | 197806 | 197745 | 0 | 0 |
T49 | 55490 | 55436 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42200429 | 0 | 654 |
T1 | 117278 | 117017 | 0 | 3 |
T2 | 2395 | 2335 | 0 | 3 |
T3 | 1340 | 1260 | 0 | 3 |
T7 | 126691 | 126621 | 0 | 3 |
T10 | 84849 | 84767 | 0 | 3 |
T11 | 153658 | 153356 | 0 | 3 |
T30 | 11426 | 11064 | 0 | 3 |
T47 | 500814 | 500732 | 0 | 3 |
T48 | 197806 | 197742 | 0 | 3 |
T49 | 55490 | 55433 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 218 | 218 | 0 | 0 |
OutputsKnown_A | 42241229 | 42202199 | 0 | 0 |
gen_no_flops.OutputDelay_A | 42241229 | 42202199 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 218 | 218 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42202199 | 0 | 0 |
T1 | 117278 | 117029 | 0 | 0 |
T2 | 2395 | 2338 | 0 | 0 |
T3 | 1340 | 1263 | 0 | 0 |
T7 | 126691 | 126624 | 0 | 0 |
T10 | 84849 | 84770 | 0 | 0 |
T11 | 153658 | 153371 | 0 | 0 |
T30 | 11426 | 11079 | 0 | 0 |
T47 | 500814 | 500735 | 0 | 0 |
T48 | 197806 | 197745 | 0 | 0 |
T49 | 55490 | 55436 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42202199 | 0 | 0 |
T1 | 117278 | 117029 | 0 | 0 |
T2 | 2395 | 2338 | 0 | 0 |
T3 | 1340 | 1263 | 0 | 0 |
T7 | 126691 | 126624 | 0 | 0 |
T10 | 84849 | 84770 | 0 | 0 |
T11 | 153658 | 153371 | 0 | 0 |
T30 | 11426 | 11079 | 0 | 0 |
T47 | 500814 | 500735 | 0 | 0 |
T48 | 197806 | 197745 | 0 | 0 |
T49 | 55490 | 55436 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 218 | 218 | 0 | 0 |
OutputsKnown_A | 42241229 | 42202199 | 0 | 0 |
gen_no_flops.OutputDelay_A | 42241229 | 42202199 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 218 | 218 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T47 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T49 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42202199 | 0 | 0 |
T1 | 117278 | 117029 | 0 | 0 |
T2 | 2395 | 2338 | 0 | 0 |
T3 | 1340 | 1263 | 0 | 0 |
T7 | 126691 | 126624 | 0 | 0 |
T10 | 84849 | 84770 | 0 | 0 |
T11 | 153658 | 153371 | 0 | 0 |
T30 | 11426 | 11079 | 0 | 0 |
T47 | 500814 | 500735 | 0 | 0 |
T48 | 197806 | 197745 | 0 | 0 |
T49 | 55490 | 55436 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 42241229 | 42202199 | 0 | 0 |
T1 | 117278 | 117029 | 0 | 0 |
T2 | 2395 | 2338 | 0 | 0 |
T3 | 1340 | 1263 | 0 | 0 |
T7 | 126691 | 126624 | 0 | 0 |
T10 | 84849 | 84770 | 0 | 0 |
T11 | 153658 | 153371 | 0 | 0 |
T30 | 11426 | 11079 | 0 | 0 |
T47 | 500814 | 500735 | 0 | 0 |
T48 | 197806 | 197745 | 0 | 0 |
T49 | 55490 | 55436 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |