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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.07 95.77 81.52 89.91 76.25 86.50 98.53 53.02


Total test records in report: 440
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T297 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4090845058 Jul 19 04:54:47 PM PDT 24 Jul 19 04:55:19 PM PDT 24 45987764692 ps
T92 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3430551837 Jul 19 04:54:37 PM PDT 24 Jul 19 04:54:40 PM PDT 24 322061701 ps
T83 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1609952313 Jul 19 04:54:41 PM PDT 24 Jul 19 04:54:50 PM PDT 24 264845155 ps
T84 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.840250555 Jul 19 04:55:07 PM PDT 24 Jul 19 04:55:25 PM PDT 24 1130998499 ps
T85 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4293029047 Jul 19 04:55:15 PM PDT 24 Jul 19 04:55:40 PM PDT 24 2673233751 ps
T95 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.472076713 Jul 19 04:54:49 PM PDT 24 Jul 19 04:55:11 PM PDT 24 1975648172 ps
T93 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3615506374 Jul 19 04:55:14 PM PDT 24 Jul 19 04:55:17 PM PDT 24 130567703 ps
T298 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3710406761 Jul 19 04:54:44 PM PDT 24 Jul 19 04:54:52 PM PDT 24 4477138139 ps
T299 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2817758862 Jul 19 04:55:15 PM PDT 24 Jul 19 04:55:36 PM PDT 24 5599432776 ps
T300 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1440278523 Jul 19 04:54:50 PM PDT 24 Jul 19 04:54:57 PM PDT 24 584962445 ps
T86 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1456661736 Jul 19 04:55:14 PM PDT 24 Jul 19 04:55:19 PM PDT 24 102903275 ps
T301 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.916040994 Jul 19 04:54:40 PM PDT 24 Jul 19 04:54:43 PM PDT 24 67908158 ps
T302 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.554025538 Jul 19 04:55:15 PM PDT 24 Jul 19 04:55:25 PM PDT 24 2983648094 ps
T96 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.616686130 Jul 19 04:54:46 PM PDT 24 Jul 19 04:54:58 PM PDT 24 4963288638 ps
T303 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.538312182 Jul 19 04:54:57 PM PDT 24 Jul 19 04:55:03 PM PDT 24 166358662 ps
T304 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3502720020 Jul 19 04:55:03 PM PDT 24 Jul 19 04:55:10 PM PDT 24 1699717443 ps
T305 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2914714254 Jul 19 04:54:38 PM PDT 24 Jul 19 04:54:54 PM PDT 24 7044628292 ps
T94 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4140152729 Jul 19 04:55:00 PM PDT 24 Jul 19 04:55:10 PM PDT 24 259494907 ps
T306 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1195449350 Jul 19 04:55:00 PM PDT 24 Jul 19 04:55:35 PM PDT 24 10143716287 ps
T307 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2721517170 Jul 19 04:55:06 PM PDT 24 Jul 19 04:55:24 PM PDT 24 9816263452 ps
T101 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1309381120 Jul 19 04:54:50 PM PDT 24 Jul 19 04:54:57 PM PDT 24 151416181 ps
T155 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.580321057 Jul 19 04:55:05 PM PDT 24 Jul 19 04:55:17 PM PDT 24 946967779 ps
T153 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1644701319 Jul 19 04:55:05 PM PDT 24 Jul 19 04:55:11 PM PDT 24 188498471 ps
T102 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3225467 Jul 19 04:54:59 PM PDT 24 Jul 19 04:55:04 PM PDT 24 291239705 ps
T308 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3356586688 Jul 19 04:54:46 PM PDT 24 Jul 19 04:55:02 PM PDT 24 9365346482 ps
T309 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3088272004 Jul 19 04:54:48 PM PDT 24 Jul 19 04:54:54 PM PDT 24 911680016 ps
T103 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1226972360 Jul 19 04:54:55 PM PDT 24 Jul 19 04:55:01 PM PDT 24 246721357 ps
T104 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.786006273 Jul 19 04:54:57 PM PDT 24 Jul 19 04:55:03 PM PDT 24 719842590 ps
T310 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3274422635 Jul 19 04:55:16 PM PDT 24 Jul 19 04:55:23 PM PDT 24 1066231694 ps
T311 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4254540021 Jul 19 04:54:41 PM PDT 24 Jul 19 04:54:45 PM PDT 24 148937394 ps
T125 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.546185671 Jul 19 04:54:49 PM PDT 24 Jul 19 04:57:45 PM PDT 24 33160774817 ps
T312 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1815070856 Jul 19 04:54:45 PM PDT 24 Jul 19 04:56:07 PM PDT 24 30469296072 ps
T154 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1294286955 Jul 19 04:54:58 PM PDT 24 Jul 19 04:55:21 PM PDT 24 1741541664 ps
T313 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3162743543 Jul 19 04:54:58 PM PDT 24 Jul 19 04:55:02 PM PDT 24 191714605 ps
T105 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3743227549 Jul 19 04:54:51 PM PDT 24 Jul 19 04:55:00 PM PDT 24 751589485 ps
T126 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3472298852 Jul 19 04:54:50 PM PDT 24 Jul 19 04:55:16 PM PDT 24 4541261451 ps
T314 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3934075149 Jul 19 04:55:00 PM PDT 24 Jul 19 04:55:05 PM PDT 24 903927257 ps
T315 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.800630155 Jul 19 04:54:39 PM PDT 24 Jul 19 04:54:43 PM PDT 24 593486882 ps
T316 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.195341050 Jul 19 04:54:47 PM PDT 24 Jul 19 04:54:50 PM PDT 24 105935854 ps
T317 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3733157555 Jul 19 04:55:15 PM PDT 24 Jul 19 04:55:21 PM PDT 24 384428397 ps
T318 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3495707436 Jul 19 04:54:56 PM PDT 24 Jul 19 04:55:01 PM PDT 24 221298910 ps
T319 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1493491887 Jul 19 04:54:39 PM PDT 24 Jul 19 04:54:42 PM PDT 24 161984376 ps
T127 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4245990360 Jul 19 04:55:16 PM PDT 24 Jul 19 04:55:25 PM PDT 24 215482483 ps
T106 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2974814725 Jul 19 04:54:40 PM PDT 24 Jul 19 04:55:11 PM PDT 24 2419188379 ps
T320 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1357698012 Jul 19 04:55:04 PM PDT 24 Jul 19 04:55:11 PM PDT 24 220676211 ps
T321 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1305166573 Jul 19 04:55:15 PM PDT 24 Jul 19 04:55:24 PM PDT 24 1293116279 ps
T322 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1866613747 Jul 19 04:55:05 PM PDT 24 Jul 19 04:55:09 PM PDT 24 271338887 ps
T323 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1155159334 Jul 19 04:54:55 PM PDT 24 Jul 19 04:55:13 PM PDT 24 17794239000 ps
T324 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3555137026 Jul 19 04:55:14 PM PDT 24 Jul 19 04:55:20 PM PDT 24 146009481 ps
T111 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2357992507 Jul 19 04:54:48 PM PDT 24 Jul 19 04:54:56 PM PDT 24 220692233 ps
T119 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2252809342 Jul 19 04:55:06 PM PDT 24 Jul 19 04:55:16 PM PDT 24 859930234 ps
T325 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4021071346 Jul 19 04:54:45 PM PDT 24 Jul 19 04:54:51 PM PDT 24 5067255115 ps
T326 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.544949646 Jul 19 04:55:13 PM PDT 24 Jul 19 04:55:23 PM PDT 24 2328977227 ps
T107 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2612666864 Jul 19 04:55:06 PM PDT 24 Jul 19 04:55:13 PM PDT 24 511494788 ps
T112 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2143097091 Jul 19 04:54:55 PM PDT 24 Jul 19 04:55:00 PM PDT 24 266311440 ps
T128 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2900848310 Jul 19 04:55:06 PM PDT 24 Jul 19 04:55:11 PM PDT 24 216859390 ps
T113 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1066813096 Jul 19 04:55:16 PM PDT 24 Jul 19 04:55:25 PM PDT 24 161874648 ps
T327 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2541794291 Jul 19 04:54:38 PM PDT 24 Jul 19 04:54:44 PM PDT 24 1082938499 ps
T120 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3857615204 Jul 19 04:54:48 PM PDT 24 Jul 19 04:55:01 PM PDT 24 1368857313 ps
T114 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3922750835 Jul 19 04:54:47 PM PDT 24 Jul 19 04:55:31 PM PDT 24 7287085512 ps
T162 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2952281926 Jul 19 04:54:59 PM PDT 24 Jul 19 04:56:16 PM PDT 24 24546750390 ps
T328 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2126785158 Jul 19 04:55:16 PM PDT 24 Jul 19 04:55:41 PM PDT 24 26343135762 ps
T329 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.548526004 Jul 19 04:54:51 PM PDT 24 Jul 19 04:55:02 PM PDT 24 6749998989 ps
T330 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1380622895 Jul 19 04:55:15 PM PDT 24 Jul 19 04:55:44 PM PDT 24 13833751668 ps
T331 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2596491809 Jul 19 04:54:53 PM PDT 24 Jul 19 04:55:00 PM PDT 24 814094242 ps
T332 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3768364167 Jul 19 04:54:39 PM PDT 24 Jul 19 04:54:42 PM PDT 24 114320652 ps
T333 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.473402370 Jul 19 04:55:16 PM PDT 24 Jul 19 04:56:02 PM PDT 24 14401860811 ps
T334 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.621904587 Jul 19 04:54:51 PM PDT 24 Jul 19 04:55:02 PM PDT 24 3157462962 ps
T335 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3502635837 Jul 19 04:55:05 PM PDT 24 Jul 19 04:55:35 PM PDT 24 12229061171 ps
T336 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3340971047 Jul 19 04:54:51 PM PDT 24 Jul 19 04:54:57 PM PDT 24 117869078 ps
T115 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3672407035 Jul 19 04:54:56 PM PDT 24 Jul 19 04:55:02 PM PDT 24 56931804 ps
T337 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1514494118 Jul 19 04:54:38 PM PDT 24 Jul 19 04:58:36 PM PDT 24 21761020347 ps
T338 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1815261444 Jul 19 04:54:47 PM PDT 24 Jul 19 04:55:08 PM PDT 24 6418103373 ps
T339 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3268747593 Jul 19 04:54:50 PM PDT 24 Jul 19 04:55:00 PM PDT 24 590749419 ps
T340 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.627296052 Jul 19 04:55:05 PM PDT 24 Jul 19 04:57:49 PM PDT 24 100313688827 ps
T341 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3743315811 Jul 19 04:54:47 PM PDT 24 Jul 19 04:55:59 PM PDT 24 2228058811 ps
T160 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3926072073 Jul 19 04:55:05 PM PDT 24 Jul 19 04:55:32 PM PDT 24 3139148316 ps
T342 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2037959445 Jul 19 04:55:17 PM PDT 24 Jul 19 04:55:30 PM PDT 24 4532635194 ps
T343 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.414214035 Jul 19 04:55:15 PM PDT 24 Jul 19 04:55:24 PM PDT 24 86110979 ps
T344 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3640162453 Jul 19 04:54:50 PM PDT 24 Jul 19 04:55:04 PM PDT 24 7327474774 ps
T157 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3203266078 Jul 19 04:55:03 PM PDT 24 Jul 19 04:55:28 PM PDT 24 10654778578 ps
T345 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4236503635 Jul 19 04:54:45 PM PDT 24 Jul 19 04:55:25 PM PDT 24 44237099649 ps
T346 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.867189168 Jul 19 04:54:57 PM PDT 24 Jul 19 04:55:12 PM PDT 24 872966048 ps
T347 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2371415322 Jul 19 04:55:01 PM PDT 24 Jul 19 04:55:09 PM PDT 24 212112344 ps
T348 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.357964560 Jul 19 04:55:16 PM PDT 24 Jul 19 04:55:25 PM PDT 24 641441421 ps
T349 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3975040224 Jul 19 04:54:47 PM PDT 24 Jul 19 04:54:51 PM PDT 24 79688445 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2976985076 Jul 19 04:54:38 PM PDT 24 Jul 19 04:54:41 PM PDT 24 81094438 ps
T351 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.482909521 Jul 19 04:54:46 PM PDT 24 Jul 19 04:54:50 PM PDT 24 229160788 ps
T352 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2549163040 Jul 19 04:54:38 PM PDT 24 Jul 19 04:54:57 PM PDT 24 19117606097 ps
T108 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3356415085 Jul 19 04:55:16 PM PDT 24 Jul 19 04:55:26 PM PDT 24 528683938 ps
T353 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2063946937 Jul 19 04:54:58 PM PDT 24 Jul 19 04:55:23 PM PDT 24 8512602244 ps
T354 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2187324152 Jul 19 04:55:06 PM PDT 24 Jul 19 04:55:13 PM PDT 24 291343900 ps
T355 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.225745123 Jul 19 04:54:51 PM PDT 24 Jul 19 04:54:57 PM PDT 24 118157350 ps
T116 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3989504991 Jul 19 04:54:50 PM PDT 24 Jul 19 04:54:57 PM PDT 24 130557117 ps
T161 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2809526496 Jul 19 04:54:49 PM PDT 24 Jul 19 05:03:10 PM PDT 24 58130938613 ps
T356 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3654149427 Jul 19 04:54:40 PM PDT 24 Jul 19 04:54:49 PM PDT 24 1488511043 ps
T158 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3997339701 Jul 19 04:54:58 PM PDT 24 Jul 19 04:55:18 PM PDT 24 1668283869 ps
T357 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1949914303 Jul 19 04:54:48 PM PDT 24 Jul 19 04:55:06 PM PDT 24 4891209013 ps
T358 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.281013053 Jul 19 04:55:00 PM PDT 24 Jul 19 04:55:06 PM PDT 24 59302668 ps
T359 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.288604464 Jul 19 04:55:00 PM PDT 24 Jul 19 04:55:10 PM PDT 24 9902531928 ps
T360 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1478667820 Jul 19 04:54:58 PM PDT 24 Jul 19 04:55:04 PM PDT 24 99632963 ps
T77 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3663401517 Jul 19 04:54:57 PM PDT 24 Jul 19 04:56:03 PM PDT 24 76982030029 ps
T361 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4092176059 Jul 19 04:55:04 PM PDT 24 Jul 19 04:55:08 PM PDT 24 287144796 ps
T121 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3347571155 Jul 19 04:55:14 PM PDT 24 Jul 19 04:55:28 PM PDT 24 1386143042 ps
T362 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4116226010 Jul 19 04:55:14 PM PDT 24 Jul 19 04:55:35 PM PDT 24 2754715742 ps
T363 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1545765323 Jul 19 04:54:42 PM PDT 24 Jul 19 04:54:54 PM PDT 24 2571337433 ps
T364 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1727577867 Jul 19 04:54:39 PM PDT 24 Jul 19 04:54:49 PM PDT 24 2087709246 ps
T365 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1984394034 Jul 19 04:54:57 PM PDT 24 Jul 19 04:55:02 PM PDT 24 180623229 ps
T366 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.292013892 Jul 19 04:54:39 PM PDT 24 Jul 19 04:54:42 PM PDT 24 625749407 ps
T367 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2404239631 Jul 19 04:54:38 PM PDT 24 Jul 19 04:54:41 PM PDT 24 164679074 ps
T368 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2396866751 Jul 19 04:55:14 PM PDT 24 Jul 19 04:55:23 PM PDT 24 982103589 ps
T117 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.105583452 Jul 19 04:54:41 PM PDT 24 Jul 19 04:54:46 PM PDT 24 111403369 ps
T369 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4063189613 Jul 19 04:54:45 PM PDT 24 Jul 19 04:54:49 PM PDT 24 440840598 ps
T118 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1108738895 Jul 19 04:54:50 PM PDT 24 Jul 19 04:54:57 PM PDT 24 220419837 ps
T370 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3551764433 Jul 19 04:54:45 PM PDT 24 Jul 19 04:54:52 PM PDT 24 257549168 ps
T371 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2301497327 Jul 19 04:54:47 PM PDT 24 Jul 19 04:54:54 PM PDT 24 131526898 ps
T372 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3060995977 Jul 19 04:54:51 PM PDT 24 Jul 19 04:55:01 PM PDT 24 312868166 ps
T373 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4251006294 Jul 19 04:55:13 PM PDT 24 Jul 19 04:55:22 PM PDT 24 5574220375 ps
T374 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1505221141 Jul 19 04:54:56 PM PDT 24 Jul 19 04:55:02 PM PDT 24 626267365 ps
T375 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2179192595 Jul 19 04:55:04 PM PDT 24 Jul 19 04:55:19 PM PDT 24 6229566320 ps
T376 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.786993234 Jul 19 04:54:49 PM PDT 24 Jul 19 04:54:59 PM PDT 24 1300370063 ps
T377 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3983439870 Jul 19 04:54:50 PM PDT 24 Jul 19 04:55:00 PM PDT 24 170933522 ps
T378 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3973515686 Jul 19 04:54:38 PM PDT 24 Jul 19 04:55:21 PM PDT 24 13393764129 ps
T379 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2335713196 Jul 19 04:55:14 PM PDT 24 Jul 19 04:55:19 PM PDT 24 1913705629 ps
T380 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.4177815375 Jul 19 04:55:03 PM PDT 24 Jul 19 04:55:10 PM PDT 24 183129265 ps
T381 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3349080786 Jul 19 04:55:16 PM PDT 24 Jul 19 04:55:25 PM PDT 24 135563872 ps
T382 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3171596847 Jul 19 04:55:15 PM PDT 24 Jul 19 04:55:26 PM PDT 24 1962735447 ps
T383 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2250293461 Jul 19 04:54:41 PM PDT 24 Jul 19 04:54:46 PM PDT 24 1871173602 ps
T384 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2805180772 Jul 19 04:55:16 PM PDT 24 Jul 19 04:55:24 PM PDT 24 177887466 ps
T385 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1868335905 Jul 19 04:54:39 PM PDT 24 Jul 19 04:54:48 PM PDT 24 2328458023 ps
T386 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4097074126 Jul 19 04:54:59 PM PDT 24 Jul 19 04:55:20 PM PDT 24 12462099752 ps
T387 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1127699597 Jul 19 04:54:42 PM PDT 24 Jul 19 04:55:03 PM PDT 24 7549769242 ps
T388 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2508572392 Jul 19 04:54:49 PM PDT 24 Jul 19 04:54:57 PM PDT 24 1856373668 ps
T389 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3261534642 Jul 19 04:55:15 PM PDT 24 Jul 19 04:55:25 PM PDT 24 2815719282 ps
T390 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1778892880 Jul 19 04:55:00 PM PDT 24 Jul 19 04:55:09 PM PDT 24 1035691146 ps
T391 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2987762771 Jul 19 04:54:58 PM PDT 24 Jul 19 04:55:08 PM PDT 24 2324279763 ps
T392 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2147149669 Jul 19 04:54:47 PM PDT 24 Jul 19 04:55:46 PM PDT 24 86122745061 ps
T393 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1540508512 Jul 19 04:54:42 PM PDT 24 Jul 19 04:55:51 PM PDT 24 1093178524 ps
T159 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3863352599 Jul 19 04:54:44 PM PDT 24 Jul 19 04:54:57 PM PDT 24 2413404056 ps
T394 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.382522506 Jul 19 04:54:39 PM PDT 24 Jul 19 04:54:44 PM PDT 24 71119644 ps
T395 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.4242672729 Jul 19 04:54:47 PM PDT 24 Jul 19 04:57:17 PM PDT 24 42720351700 ps
T396 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1184517660 Jul 19 04:55:01 PM PDT 24 Jul 19 04:55:06 PM PDT 24 251687760 ps
T397 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2769901534 Jul 19 04:54:46 PM PDT 24 Jul 19 04:54:52 PM PDT 24 4105937998 ps
T398 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3446475351 Jul 19 04:54:55 PM PDT 24 Jul 19 04:54:59 PM PDT 24 154918932 ps
T399 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3375184134 Jul 19 04:55:07 PM PDT 24 Jul 19 04:55:19 PM PDT 24 3821417803 ps
T400 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3369379342 Jul 19 04:54:38 PM PDT 24 Jul 19 04:55:19 PM PDT 24 17467638540 ps
T401 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2072600373 Jul 19 04:54:36 PM PDT 24 Jul 19 04:54:54 PM PDT 24 5988157623 ps
T402 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3997824703 Jul 19 04:54:38 PM PDT 24 Jul 19 04:54:55 PM PDT 24 15389487467 ps
T403 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1504888505 Jul 19 04:55:15 PM PDT 24 Jul 19 04:55:26 PM PDT 24 306596777 ps
T404 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2421478816 Jul 19 04:54:50 PM PDT 24 Jul 19 04:55:06 PM PDT 24 2930900488 ps
T405 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.935082008 Jul 19 04:54:46 PM PDT 24 Jul 19 04:54:50 PM PDT 24 53165232 ps
T100 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3754758238 Jul 19 04:54:41 PM PDT 24 Jul 19 04:54:47 PM PDT 24 3455441879 ps
T406 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.712063019 Jul 19 04:54:38 PM PDT 24 Jul 19 04:54:57 PM PDT 24 3551934895 ps
T407 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3492133511 Jul 19 04:55:14 PM PDT 24 Jul 19 04:55:31 PM PDT 24 882595520 ps
T408 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2286989449 Jul 19 04:54:59 PM PDT 24 Jul 19 04:58:46 PM PDT 24 34623306793 ps
T409 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3852361658 Jul 19 04:55:05 PM PDT 24 Jul 19 04:55:14 PM PDT 24 355803891 ps
T410 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1495831195 Jul 19 04:55:00 PM PDT 24 Jul 19 04:55:06 PM PDT 24 234869484 ps
T411 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1619559567 Jul 19 04:54:57 PM PDT 24 Jul 19 04:55:08 PM PDT 24 212146572 ps
T412 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1223309051 Jul 19 04:55:13 PM PDT 24 Jul 19 04:55:20 PM PDT 24 351195626 ps
T413 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.492045998 Jul 19 04:55:14 PM PDT 24 Jul 19 04:55:18 PM PDT 24 66466232 ps
T414 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.428372556 Jul 19 04:54:59 PM PDT 24 Jul 19 04:55:07 PM PDT 24 760154712 ps
T109 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1154337090 Jul 19 04:54:28 PM PDT 24 Jul 19 04:55:05 PM PDT 24 5565155598 ps
T415 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.4150831376 Jul 19 04:55:06 PM PDT 24 Jul 19 04:55:10 PM PDT 24 56918131 ps
T416 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3261036142 Jul 19 04:54:58 PM PDT 24 Jul 19 04:55:04 PM PDT 24 224552727 ps
T417 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2357327268 Jul 19 04:55:04 PM PDT 24 Jul 19 04:55:13 PM PDT 24 3458662197 ps
T418 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3383070248 Jul 19 04:54:41 PM PDT 24 Jul 19 04:54:45 PM PDT 24 64366590 ps
T419 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3609729981 Jul 19 04:54:50 PM PDT 24 Jul 19 04:55:29 PM PDT 24 9789716023 ps
T420 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2257872095 Jul 19 04:54:50 PM PDT 24 Jul 19 04:55:03 PM PDT 24 1067682210 ps
T421 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2939631397 Jul 19 04:54:38 PM PDT 24 Jul 19 04:55:34 PM PDT 24 1531134477 ps
T422 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3613404428 Jul 19 04:54:40 PM PDT 24 Jul 19 04:54:48 PM PDT 24 1541078295 ps
T423 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2937004750 Jul 19 04:54:50 PM PDT 24 Jul 19 04:54:58 PM PDT 24 201109611 ps
T424 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.973486087 Jul 19 04:54:42 PM PDT 24 Jul 19 04:54:47 PM PDT 24 69779542 ps
T425 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3591663369 Jul 19 04:55:15 PM PDT 24 Jul 19 04:55:23 PM PDT 24 192851988 ps
T110 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.950548551 Jul 19 04:55:14 PM PDT 24 Jul 19 04:55:28 PM PDT 24 584090867 ps
T426 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.601694273 Jul 19 04:55:00 PM PDT 24 Jul 19 04:55:15 PM PDT 24 7897810527 ps
T427 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3941436729 Jul 19 04:55:04 PM PDT 24 Jul 19 04:55:11 PM PDT 24 115321881 ps
T428 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1208943202 Jul 19 04:54:36 PM PDT 24 Jul 19 04:57:21 PM PDT 24 62424401658 ps
T429 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3330852199 Jul 19 04:54:38 PM PDT 24 Jul 19 04:54:44 PM PDT 24 3047183725 ps
T430 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.560014675 Jul 19 04:54:45 PM PDT 24 Jul 19 04:54:59 PM PDT 24 17745026912 ps
T431 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1533526280 Jul 19 04:55:01 PM PDT 24 Jul 19 04:55:29 PM PDT 24 16705117740 ps
T432 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1000323778 Jul 19 04:54:40 PM PDT 24 Jul 19 04:54:43 PM PDT 24 675442672 ps
T433 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1998885721 Jul 19 04:55:16 PM PDT 24 Jul 19 04:55:24 PM PDT 24 310071201 ps
T434 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3575040834 Jul 19 04:54:57 PM PDT 24 Jul 19 04:55:10 PM PDT 24 1397691433 ps
T435 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.340595798 Jul 19 04:55:00 PM PDT 24 Jul 19 04:55:06 PM PDT 24 200736268 ps
T156 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1167558789 Jul 19 04:54:49 PM PDT 24 Jul 19 04:55:23 PM PDT 24 5913994551 ps
T436 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1705078141 Jul 19 04:55:14 PM PDT 24 Jul 19 04:55:21 PM PDT 24 114839217 ps
T437 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2969083880 Jul 19 04:54:46 PM PDT 24 Jul 19 04:55:53 PM PDT 24 83798896109 ps
T438 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1826717082 Jul 19 04:54:49 PM PDT 24 Jul 19 04:54:59 PM PDT 24 287537980 ps
T439 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1114713094 Jul 19 04:54:39 PM PDT 24 Jul 19 04:57:14 PM PDT 24 51449284048 ps
T440 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.967089451 Jul 19 04:55:06 PM PDT 24 Jul 19 04:55:10 PM PDT 24 240460354 ps

Test location /workspace/coverage/default/33.rv_dm_stress_all.2767330311
Short name T4
Test name
Test status
Simulation time 7035551639 ps
CPU time 17.85 seconds
Started Jul 19 04:59:54 PM PDT 24
Finished Jul 19 05:00:15 PM PDT 24
Peak memory 213504 kb
Host smart-7db0cb71-bf1e-443a-8e1f-0ba355ac3c99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767330311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2767330311
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1465304946
Short name T29
Test name
Test status
Simulation time 12950861066 ps
CPU time 39.8 seconds
Started Jul 19 04:59:27 PM PDT 24
Finished Jul 19 05:00:12 PM PDT 24
Peak memory 213732 kb
Host smart-2c4289c0-e007-40f5-adb1-251d97a0e4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465304946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1465304946
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1686576692
Short name T59
Test name
Test status
Simulation time 47554865508 ps
CPU time 123.88 seconds
Started Jul 19 04:54:48 PM PDT 24
Finished Jul 19 04:56:57 PM PDT 24
Peak memory 221936 kb
Host smart-8c07a708-91b6-4225-9718-b40ada55e351
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686576692 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.1686576692
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.3015982574
Short name T6
Test name
Test status
Simulation time 7799236952 ps
CPU time 11.97 seconds
Started Jul 19 04:59:43 PM PDT 24
Finished Jul 19 04:59:56 PM PDT 24
Peak memory 213564 kb
Host smart-ffdb98e3-ec73-418c-a841-630d1aad57f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015982574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.3015982574
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.288492670
Short name T58
Test name
Test status
Simulation time 1388235578 ps
CPU time 17.63 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:39 PM PDT 24
Peak memory 213568 kb
Host smart-fdc95274-d4ad-4f70-85b2-df6cb326c279
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288492670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.288492670
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.4267614282
Short name T33
Test name
Test status
Simulation time 49454252976 ps
CPU time 36.37 seconds
Started Jul 19 04:59:28 PM PDT 24
Finished Jul 19 05:00:09 PM PDT 24
Peak memory 213704 kb
Host smart-50ed7721-f554-40cb-8c54-f918c8101afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267614282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.4267614282
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.355156083
Short name T123
Test name
Test status
Simulation time 148681612 ps
CPU time 0.91 seconds
Started Jul 19 04:59:59 PM PDT 24
Finished Jul 19 05:00:05 PM PDT 24
Peak memory 204984 kb
Host smart-d43beff0-25fd-4f9c-849c-30a443990517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355156083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.355156083
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1294286955
Short name T154
Test name
Test status
Simulation time 1741541664 ps
CPU time 19.55 seconds
Started Jul 19 04:54:58 PM PDT 24
Finished Jul 19 04:55:21 PM PDT 24
Peak memory 213552 kb
Host smart-2ef2ea58-d0ce-45f0-bb59-017e41e48186
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294286955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
294286955
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.663549392
Short name T41
Test name
Test status
Simulation time 3989789056 ps
CPU time 11.63 seconds
Started Jul 19 04:58:34 PM PDT 24
Finished Jul 19 04:58:47 PM PDT 24
Peak memory 205240 kb
Host smart-639bdde5-e576-41e3-8568-153b0070ad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663549392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.663549392
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.1098254988
Short name T26
Test name
Test status
Simulation time 4557243483 ps
CPU time 11 seconds
Started Jul 19 04:59:27 PM PDT 24
Finished Jul 19 04:59:43 PM PDT 24
Peak memory 205208 kb
Host smart-3d28f2a4-cf40-442c-a333-e280e8a22f3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098254988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1098254988
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.2027067927
Short name T56
Test name
Test status
Simulation time 41636371 ps
CPU time 0.9 seconds
Started Jul 19 04:58:43 PM PDT 24
Finished Jul 19 04:58:45 PM PDT 24
Peak memory 215428 kb
Host smart-496703fd-341d-4d37-b4ea-9e904ea107d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027067927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2027067927
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1615862412
Short name T73
Test name
Test status
Simulation time 712409668 ps
CPU time 2.68 seconds
Started Jul 19 04:58:37 PM PDT 24
Finished Jul 19 04:58:41 PM PDT 24
Peak memory 205172 kb
Host smart-d0cf371b-369d-4443-90ed-5982baf9a834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615862412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1615862412
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3663401517
Short name T77
Test name
Test status
Simulation time 76982030029 ps
CPU time 62.71 seconds
Started Jul 19 04:54:57 PM PDT 24
Finished Jul 19 04:56:03 PM PDT 24
Peak memory 230172 kb
Host smart-f33167ec-daa3-4039-9972-a4e7b2260e3c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663401517 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3663401517
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.762675604
Short name T12
Test name
Test status
Simulation time 2698399439 ps
CPU time 4.93 seconds
Started Jul 19 04:59:36 PM PDT 24
Finished Jul 19 04:59:44 PM PDT 24
Peak memory 205304 kb
Host smart-e26af00a-38aa-4218-a298-8cc6d68b695d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762675604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.762675604
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1977398835
Short name T90
Test name
Test status
Simulation time 419917777 ps
CPU time 7.94 seconds
Started Jul 19 04:54:40 PM PDT 24
Finished Jul 19 04:54:51 PM PDT 24
Peak memory 205352 kb
Host smart-7318b761-e721-4c24-998a-1e3498e5378f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977398835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1977398835
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3789442959
Short name T38
Test name
Test status
Simulation time 55809426 ps
CPU time 0.89 seconds
Started Jul 19 04:59:04 PM PDT 24
Finished Jul 19 04:59:06 PM PDT 24
Peak memory 213264 kb
Host smart-7d7107e7-40d6-4f0c-ae15-2dd3881a9b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789442959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3789442959
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.833477016
Short name T66
Test name
Test status
Simulation time 341742905 ps
CPU time 1.4 seconds
Started Jul 19 04:59:16 PM PDT 24
Finished Jul 19 04:59:19 PM PDT 24
Peak memory 228668 kb
Host smart-6b242d2e-8247-455c-94a2-0b3c93902f3a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833477016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.833477016
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3139256913
Short name T40
Test name
Test status
Simulation time 155507405 ps
CPU time 0.94 seconds
Started Jul 19 04:58:43 PM PDT 24
Finished Jul 19 04:58:45 PM PDT 24
Peak memory 204932 kb
Host smart-c78795e0-d292-4525-b879-2b2050091fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139256913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3139256913
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1994668807
Short name T150
Test name
Test status
Simulation time 5915210104 ps
CPU time 7.69 seconds
Started Jul 19 04:59:44 PM PDT 24
Finished Jul 19 04:59:54 PM PDT 24
Peak memory 213660 kb
Host smart-6787ecc3-fcd3-4ce8-8b8f-52dc19753a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994668807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1994668807
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.993836002
Short name T52
Test name
Test status
Simulation time 89086355 ps
CPU time 0.8 seconds
Started Jul 19 04:58:43 PM PDT 24
Finished Jul 19 04:58:45 PM PDT 24
Peak memory 205012 kb
Host smart-556d6093-0bc8-410a-b237-4f879c3130ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993836002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.993836002
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3615506374
Short name T93
Test name
Test status
Simulation time 130567703 ps
CPU time 1.4 seconds
Started Jul 19 04:55:14 PM PDT 24
Finished Jul 19 04:55:17 PM PDT 24
Peak memory 213500 kb
Host smart-3e28fe8c-7cc6-4fe5-8662-a03e73f34fe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615506374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3615506374
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.1663511398
Short name T28
Test name
Test status
Simulation time 15905042729 ps
CPU time 21.04 seconds
Started Jul 19 04:59:52 PM PDT 24
Finished Jul 19 05:00:15 PM PDT 24
Peak memory 205396 kb
Host smart-a5122e0d-ef43-4e86-a9f2-63257bb72b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663511398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.1663511398
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1154337090
Short name T109
Test name
Test status
Simulation time 5565155598 ps
CPU time 33.79 seconds
Started Jul 19 04:54:28 PM PDT 24
Finished Jul 19 04:55:05 PM PDT 24
Peak memory 205492 kb
Host smart-9b8e1cbe-2767-45ff-836e-f0dcce0d511f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154337090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1154337090
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2295073677
Short name T1
Test name
Test status
Simulation time 9702278466 ps
CPU time 8.54 seconds
Started Jul 19 04:58:36 PM PDT 24
Finished Jul 19 04:58:47 PM PDT 24
Peak memory 213716 kb
Host smart-17126753-5480-40d7-9892-f77a424d20ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295073677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2295073677
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.3676260090
Short name T20
Test name
Test status
Simulation time 8704769902 ps
CPU time 13.65 seconds
Started Jul 19 04:59:51 PM PDT 24
Finished Jul 19 05:00:06 PM PDT 24
Peak memory 213520 kb
Host smart-72f41aba-4c08-4bd0-8012-a0b1c08c5c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676260090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3676260090
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.330642055
Short name T46
Test name
Test status
Simulation time 10965907779 ps
CPU time 33.76 seconds
Started Jul 19 05:00:08 PM PDT 24
Finished Jul 19 05:00:45 PM PDT 24
Peak memory 213528 kb
Host smart-448e5c98-6113-466f-9c06-bff733089696
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330642055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.330642055
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.404361451
Short name T21
Test name
Test status
Simulation time 2086044386 ps
CPU time 5.93 seconds
Started Jul 19 04:58:42 PM PDT 24
Finished Jul 19 04:58:49 PM PDT 24
Peak memory 204992 kb
Host smart-587e64b3-055e-46df-b6c5-bc1070a257a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404361451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.404361451
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.38007188
Short name T43
Test name
Test status
Simulation time 574514285 ps
CPU time 1.13 seconds
Started Jul 19 04:58:44 PM PDT 24
Finished Jul 19 04:58:46 PM PDT 24
Peak memory 204984 kb
Host smart-a372a8ee-dd92-49f3-86d1-51dc75899eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38007188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.38007188
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.2755958310
Short name T30
Test name
Test status
Simulation time 248687897 ps
CPU time 1.45 seconds
Started Jul 19 04:58:42 PM PDT 24
Finished Jul 19 04:58:45 PM PDT 24
Peak memory 204992 kb
Host smart-17488411-f8eb-4f2f-b215-508dc97d4141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755958310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.2755958310
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.840250555
Short name T84
Test name
Test status
Simulation time 1130998499 ps
CPU time 16.37 seconds
Started Jul 19 04:55:07 PM PDT 24
Finished Jul 19 04:55:25 PM PDT 24
Peak memory 213644 kb
Host smart-61af862d-126c-4900-a275-a5a501dae3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840250555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.840250555
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2674946366
Short name T99
Test name
Test status
Simulation time 18650752867 ps
CPU time 13.99 seconds
Started Jul 19 04:54:45 PM PDT 24
Finished Jul 19 04:55:02 PM PDT 24
Peak memory 205388 kb
Host smart-89f191bd-148d-4893-823a-5fe0e3177a9c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674946366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2674946366
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2111694443
Short name T294
Test name
Test status
Simulation time 215714182 ps
CPU time 1.23 seconds
Started Jul 19 04:54:41 PM PDT 24
Finished Jul 19 04:54:45 PM PDT 24
Peak memory 205016 kb
Host smart-d2f9daa1-4657-4158-9ad5-d57d7ab6b5fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111694443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2111694443
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3926072073
Short name T160
Test name
Test status
Simulation time 3139148316 ps
CPU time 24.2 seconds
Started Jul 19 04:55:05 PM PDT 24
Finished Jul 19 04:55:32 PM PDT 24
Peak memory 213636 kb
Host smart-435e5ee2-8a7c-42a5-ae45-ab300ed3784e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926072073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
926072073
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.415426834
Short name T131
Test name
Test status
Simulation time 10002939511 ps
CPU time 7.89 seconds
Started Jul 19 04:59:35 PM PDT 24
Finished Jul 19 04:59:45 PM PDT 24
Peak memory 213424 kb
Host smart-f208cd50-8aaa-4e1c-8740-e2cac245abbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415426834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.415426834
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.4248237205
Short name T37
Test name
Test status
Simulation time 1784996099 ps
CPU time 1.42 seconds
Started Jul 19 04:58:36 PM PDT 24
Finished Jul 19 04:58:39 PM PDT 24
Peak memory 204976 kb
Host smart-50dc5508-0b42-426a-9af7-bdc56eec151d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248237205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.4248237205
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.580321057
Short name T155
Test name
Test status
Simulation time 946967779 ps
CPU time 8.9 seconds
Started Jul 19 04:55:05 PM PDT 24
Finished Jul 19 04:55:17 PM PDT 24
Peak memory 213592 kb
Host smart-f40486f9-3324-4123-9736-dd47222c27e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580321057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.580321057
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3502720020
Short name T304
Test name
Test status
Simulation time 1699717443 ps
CPU time 3.96 seconds
Started Jul 19 04:55:03 PM PDT 24
Finished Jul 19 04:55:10 PM PDT 24
Peak memory 219932 kb
Host smart-31aec02e-3a08-4659-bb39-fec324e436a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502720020 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3502720020
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3357312926
Short name T147
Test name
Test status
Simulation time 974147810 ps
CPU time 3.54 seconds
Started Jul 19 04:58:42 PM PDT 24
Finished Jul 19 04:58:46 PM PDT 24
Peak memory 204908 kb
Host smart-078c915e-2dd8-47d6-a157-1c081f13a0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357312926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3357312926
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.4160534932
Short name T151
Test name
Test status
Simulation time 3857917824 ps
CPU time 11.17 seconds
Started Jul 19 04:58:34 PM PDT 24
Finished Jul 19 04:58:47 PM PDT 24
Peak memory 205176 kb
Host smart-7eb907ec-616c-4c1c-badf-b03e2a072afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160534932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.4160534932
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2388424207
Short name T129
Test name
Test status
Simulation time 8194606486 ps
CPU time 12.74 seconds
Started Jul 19 04:59:18 PM PDT 24
Finished Jul 19 04:59:33 PM PDT 24
Peak memory 213648 kb
Host smart-48aab5c7-2935-43c0-9067-5859a4d50215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388424207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2388424207
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1514494118
Short name T337
Test name
Test status
Simulation time 21761020347 ps
CPU time 236.21 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:58:36 PM PDT 24
Peak memory 221820 kb
Host smart-6be38246-b972-4e23-bda2-d56a8f2569d5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514494118 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1514494118
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3272586683
Short name T275
Test name
Test status
Simulation time 1556253537 ps
CPU time 3.43 seconds
Started Jul 19 04:59:28 PM PDT 24
Finished Jul 19 04:59:37 PM PDT 24
Peak memory 205356 kb
Host smart-7960820b-ba50-42c7-b9fe-b54a3e875423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272586683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3272586683
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2939631397
Short name T421
Test name
Test status
Simulation time 1531134477 ps
CPU time 54.1 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:55:34 PM PDT 24
Peak memory 205360 kb
Host smart-bc5c41b0-59bb-4214-a077-2f7f3734c5a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939631397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2939631397
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3430551837
Short name T92
Test name
Test status
Simulation time 322061701 ps
CPU time 1.69 seconds
Started Jul 19 04:54:37 PM PDT 24
Finished Jul 19 04:54:40 PM PDT 24
Peak memory 213528 kb
Host smart-6ffd4e45-be28-48de-8ad3-f65ae894e795
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430551837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3430551837
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3654149427
Short name T356
Test name
Test status
Simulation time 1488511043 ps
CPU time 6.46 seconds
Started Jul 19 04:54:40 PM PDT 24
Finished Jul 19 04:54:49 PM PDT 24
Peak memory 220348 kb
Host smart-0c74a6e7-859e-48a3-938e-e9427adcdd00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654149427 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3654149427
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.973486087
Short name T424
Test name
Test status
Simulation time 69779542 ps
CPU time 2.19 seconds
Started Jul 19 04:54:42 PM PDT 24
Finished Jul 19 04:54:47 PM PDT 24
Peak memory 213516 kb
Host smart-6121f025-3127-4c12-b551-d9d35e66d0a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973486087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.973486087
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2549163040
Short name T352
Test name
Test status
Simulation time 19117606097 ps
CPU time 18.26 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:54:57 PM PDT 24
Peak memory 205392 kb
Host smart-b182e542-8ba2-4fc1-b6bc-900091314cd9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549163040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2549163040
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.382522506
Short name T394
Test name
Test status
Simulation time 71119644 ps
CPU time 0.85 seconds
Started Jul 19 04:54:39 PM PDT 24
Finished Jul 19 04:54:44 PM PDT 24
Peak memory 204984 kb
Host smart-90d38b9f-6faa-4855-8e19-677eda4bb6c9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382522506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
v_dm_jtag_dmi_csr_bit_bash.382522506
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2552715419
Short name T98
Test name
Test status
Simulation time 2464515994 ps
CPU time 7.62 seconds
Started Jul 19 04:54:39 PM PDT 24
Finished Jul 19 04:54:49 PM PDT 24
Peak memory 205220 kb
Host smart-50ab6c84-567c-46c6-9cec-e2a41b921dd7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552715419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2552715419
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.844126800
Short name T292
Test name
Test status
Simulation time 7053148288 ps
CPU time 6.16 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:54:45 PM PDT 24
Peak memory 205232 kb
Host smart-f34f7bdc-ef7f-4581-82f7-c188455c2a9b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844126800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.844126800
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.800630155
Short name T315
Test name
Test status
Simulation time 593486882 ps
CPU time 0.94 seconds
Started Jul 19 04:54:39 PM PDT 24
Finished Jul 19 04:54:43 PM PDT 24
Peak memory 204992 kb
Host smart-e86d48cf-676a-4f0a-9a9b-51d723bda497
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800630155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.800630155
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1127699597
Short name T387
Test name
Test status
Simulation time 7549769242 ps
CPU time 17.74 seconds
Started Jul 19 04:54:42 PM PDT 24
Finished Jul 19 04:55:03 PM PDT 24
Peak memory 205384 kb
Host smart-339a27fc-4c2b-464a-a493-466c3113bce2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127699597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1127699597
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2541794291
Short name T327
Test name
Test status
Simulation time 1082938499 ps
CPU time 3.77 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:54:44 PM PDT 24
Peak memory 205032 kb
Host smart-269a0cf9-fab6-4338-a5d6-08bbbcf3b5f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541794291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2541794291
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1000323778
Short name T432
Test name
Test status
Simulation time 675442672 ps
CPU time 1.12 seconds
Started Jul 19 04:54:40 PM PDT 24
Finished Jul 19 04:54:43 PM PDT 24
Peak memory 204976 kb
Host smart-9c1f2fff-97f6-4a1c-90fa-d77ddde2ce90
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000323778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
000323778
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4254540021
Short name T311
Test name
Test status
Simulation time 148937394 ps
CPU time 0.76 seconds
Started Jul 19 04:54:41 PM PDT 24
Finished Jul 19 04:54:45 PM PDT 24
Peak memory 205000 kb
Host smart-42393e46-1e1c-45c7-b141-1fa306665744
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254540021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.4254540021
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2976985076
Short name T350
Test name
Test status
Simulation time 81094438 ps
CPU time 0.78 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:54:41 PM PDT 24
Peak memory 204968 kb
Host smart-b15cb8d8-ad46-4a78-b227-06204f44cf0b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976985076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2976985076
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1727577867
Short name T364
Test name
Test status
Simulation time 2087709246 ps
CPU time 7.83 seconds
Started Jul 19 04:54:39 PM PDT 24
Finished Jul 19 04:54:49 PM PDT 24
Peak memory 205392 kb
Host smart-e43fe59c-9508-4690-a5a7-5c4cf4278b83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727577867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1727577867
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3973515686
Short name T378
Test name
Test status
Simulation time 13393764129 ps
CPU time 40.88 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:55:21 PM PDT 24
Peak memory 221940 kb
Host smart-c3b288dc-b2e7-4316-8d61-0d80d4e35e5c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973515686 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3973515686
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3613404428
Short name T422
Test name
Test status
Simulation time 1541078295 ps
CPU time 5.3 seconds
Started Jul 19 04:54:40 PM PDT 24
Finished Jul 19 04:54:48 PM PDT 24
Peak memory 213660 kb
Host smart-f3379ced-041b-4dc0-8249-ace683321306
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613404428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3613404428
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.712063019
Short name T406
Test name
Test status
Simulation time 3551934895 ps
CPU time 17.65 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:54:57 PM PDT 24
Peak memory 213664 kb
Host smart-8e53383b-c502-4d72-9e0d-cce1dc4c9188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712063019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.712063019
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2974814725
Short name T106
Test name
Test status
Simulation time 2419188379 ps
CPU time 27.77 seconds
Started Jul 19 04:54:40 PM PDT 24
Finished Jul 19 04:55:11 PM PDT 24
Peak memory 205412 kb
Host smart-d256ef69-840f-40a5-bab5-c8b98786ab8b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974814725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2974814725
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3369379342
Short name T400
Test name
Test status
Simulation time 17467638540 ps
CPU time 38.71 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:55:19 PM PDT 24
Peak memory 205432 kb
Host smart-8140ee14-d7fc-432e-a5f6-6e4a50b6c1d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369379342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3369379342
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.105583452
Short name T117
Test name
Test status
Simulation time 111403369 ps
CPU time 1.61 seconds
Started Jul 19 04:54:41 PM PDT 24
Finished Jul 19 04:54:46 PM PDT 24
Peak memory 213588 kb
Host smart-06fe7ca2-1563-4d14-ae3a-9eed923102bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105583452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.105583452
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3330852199
Short name T429
Test name
Test status
Simulation time 3047183725 ps
CPU time 5.11 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:54:44 PM PDT 24
Peak memory 218148 kb
Host smart-911c6971-7e83-4424-a144-03155da7f64f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330852199 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3330852199
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2388945064
Short name T91
Test name
Test status
Simulation time 65426186 ps
CPU time 1.58 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:54:41 PM PDT 24
Peak memory 213544 kb
Host smart-1f791611-c736-47f8-b09e-b836feec475a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388945064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2388945064
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1114713094
Short name T439
Test name
Test status
Simulation time 51449284048 ps
CPU time 153.37 seconds
Started Jul 19 04:54:39 PM PDT 24
Finished Jul 19 04:57:14 PM PDT 24
Peak memory 205336 kb
Host smart-e6eab777-ea3b-4610-885e-aa291a6adf49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114713094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1114713094
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1208943202
Short name T428
Test name
Test status
Simulation time 62424401658 ps
CPU time 163.17 seconds
Started Jul 19 04:54:36 PM PDT 24
Finished Jul 19 04:57:21 PM PDT 24
Peak memory 205308 kb
Host smart-376922ca-1e6c-42aa-91b4-06bccb9b3407
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208943202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1208943202
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2250293461
Short name T383
Test name
Test status
Simulation time 1871173602 ps
CPU time 2.49 seconds
Started Jul 19 04:54:41 PM PDT 24
Finished Jul 19 04:54:46 PM PDT 24
Peak memory 205228 kb
Host smart-830f69a6-0256-4f6b-b6ed-a2569abb74e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250293461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2250293461
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1868335905
Short name T385
Test name
Test status
Simulation time 2328458023 ps
CPU time 5.97 seconds
Started Jul 19 04:54:39 PM PDT 24
Finished Jul 19 04:54:48 PM PDT 24
Peak memory 205264 kb
Host smart-f63a61c4-3b4f-4f47-8422-31ba3f7dbc85
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868335905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
868335905
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3997824703
Short name T402
Test name
Test status
Simulation time 15389487467 ps
CPU time 15.89 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:54:55 PM PDT 24
Peak memory 205576 kb
Host smart-8aa23d2b-c8e1-4352-aa92-8655cbd66d75
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997824703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3997824703
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3768364167
Short name T332
Test name
Test status
Simulation time 114320652 ps
CPU time 1 seconds
Started Jul 19 04:54:39 PM PDT 24
Finished Jul 19 04:54:42 PM PDT 24
Peak memory 204920 kb
Host smart-f153dfe9-622e-443a-849c-4d469a7e2575
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768364167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3768364167
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1262785071
Short name T80
Test name
Test status
Simulation time 321728406 ps
CPU time 1.08 seconds
Started Jul 19 04:54:42 PM PDT 24
Finished Jul 19 04:54:46 PM PDT 24
Peak memory 204964 kb
Host smart-22e58c15-39e6-4b90-ab38-44c402e14c42
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262785071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
262785071
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.916040994
Short name T301
Test name
Test status
Simulation time 67908158 ps
CPU time 0.73 seconds
Started Jul 19 04:54:40 PM PDT 24
Finished Jul 19 04:54:43 PM PDT 24
Peak memory 204988 kb
Host smart-b6181a98-a790-468d-a366-e14b0752f239
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916040994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.916040994
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3383070248
Short name T418
Test name
Test status
Simulation time 64366590 ps
CPU time 0.72 seconds
Started Jul 19 04:54:41 PM PDT 24
Finished Jul 19 04:54:45 PM PDT 24
Peak memory 205016 kb
Host smart-5e3de17e-7919-43b5-ab26-884dd8113609
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383070248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3383070248
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1609952313
Short name T83
Test name
Test status
Simulation time 264845155 ps
CPU time 5.97 seconds
Started Jul 19 04:54:41 PM PDT 24
Finished Jul 19 04:54:50 PM PDT 24
Peak memory 213520 kb
Host smart-23cc6b24-54c5-41fa-a1b0-98552bea2fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609952313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1609952313
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1545765323
Short name T363
Test name
Test status
Simulation time 2571337433 ps
CPU time 9.24 seconds
Started Jul 19 04:54:42 PM PDT 24
Finished Jul 19 04:54:54 PM PDT 24
Peak memory 213664 kb
Host smart-be068f44-de44-4d6a-b861-de0c87a94a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545765323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1545765323
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.340595798
Short name T435
Test name
Test status
Simulation time 200736268 ps
CPU time 2.57 seconds
Started Jul 19 04:55:00 PM PDT 24
Finished Jul 19 04:55:06 PM PDT 24
Peak memory 213656 kb
Host smart-8d336905-f7e8-4764-9f69-eb1ff3fe3a07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340595798 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.340595798
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3672407035
Short name T115
Test name
Test status
Simulation time 56931804 ps
CPU time 1.53 seconds
Started Jul 19 04:54:56 PM PDT 24
Finished Jul 19 04:55:02 PM PDT 24
Peak memory 213588 kb
Host smart-304bfe93-22a4-4a59-b868-32117a0660f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672407035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3672407035
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.288604464
Short name T359
Test name
Test status
Simulation time 9902531928 ps
CPU time 6.31 seconds
Started Jul 19 04:55:00 PM PDT 24
Finished Jul 19 04:55:10 PM PDT 24
Peak memory 205224 kb
Host smart-7df1827f-6cea-414c-8326-a7d0807e2eda
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288604464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rv_dm_jtag_dmi_csr_bit_bash.288604464
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.378673236
Short name T296
Test name
Test status
Simulation time 1574372053 ps
CPU time 4.12 seconds
Started Jul 19 04:54:58 PM PDT 24
Finished Jul 19 04:55:06 PM PDT 24
Peak memory 205156 kb
Host smart-fef52380-ff80-4b27-b1a9-00f426aef89e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378673236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.378673236
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3495707436
Short name T318
Test name
Test status
Simulation time 221298910 ps
CPU time 0.96 seconds
Started Jul 19 04:54:56 PM PDT 24
Finished Jul 19 04:55:01 PM PDT 24
Peak memory 204968 kb
Host smart-67e83ae3-aa1b-4674-b381-c1850d1fa3ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495707436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3495707436
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4140152729
Short name T94
Test name
Test status
Simulation time 259494907 ps
CPU time 7.02 seconds
Started Jul 19 04:55:00 PM PDT 24
Finished Jul 19 04:55:10 PM PDT 24
Peak memory 205380 kb
Host smart-f9905f1b-b031-40a2-889a-06588f2d0de1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140152729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.4140152729
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3261036142
Short name T416
Test name
Test status
Simulation time 224552727 ps
CPU time 2.54 seconds
Started Jul 19 04:54:58 PM PDT 24
Finished Jul 19 04:55:04 PM PDT 24
Peak memory 213668 kb
Host smart-77b48759-9ee6-4980-8b87-a56e73454fda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261036142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3261036142
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3375184134
Short name T399
Test name
Test status
Simulation time 3821417803 ps
CPU time 10.16 seconds
Started Jul 19 04:55:07 PM PDT 24
Finished Jul 19 04:55:19 PM PDT 24
Peak memory 221784 kb
Host smart-4801fea9-ee42-4dd2-ba5d-c69ebad50554
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375184134 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3375184134
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1064258347
Short name T291
Test name
Test status
Simulation time 12135667928 ps
CPU time 8.73 seconds
Started Jul 19 04:55:03 PM PDT 24
Finished Jul 19 04:55:15 PM PDT 24
Peak memory 205324 kb
Host smart-4cfb495a-b333-4800-b257-98fd154e4430
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064258347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1064258347
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3502635837
Short name T335
Test name
Test status
Simulation time 12229061171 ps
CPU time 27.39 seconds
Started Jul 19 04:55:05 PM PDT 24
Finished Jul 19 04:55:35 PM PDT 24
Peak memory 205308 kb
Host smart-2a6b0274-1c7d-4669-a2fd-0d77cb900459
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502635837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3502635837
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1505221141
Short name T374
Test name
Test status
Simulation time 626267365 ps
CPU time 1.72 seconds
Started Jul 19 04:54:56 PM PDT 24
Finished Jul 19 04:55:02 PM PDT 24
Peak memory 205000 kb
Host smart-813363f3-afa6-4f55-a930-c40a84634056
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505221141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1505221141
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3941436729
Short name T427
Test name
Test status
Simulation time 115321881 ps
CPU time 3.73 seconds
Started Jul 19 04:55:04 PM PDT 24
Finished Jul 19 04:55:11 PM PDT 24
Peak memory 205352 kb
Host smart-41ebd2cc-f100-41ef-8eee-cde55fb04463
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941436729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3941436729
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1357698012
Short name T320
Test name
Test status
Simulation time 220676211 ps
CPU time 3.53 seconds
Started Jul 19 04:55:04 PM PDT 24
Finished Jul 19 04:55:11 PM PDT 24
Peak memory 213700 kb
Host smart-f4b89365-949d-47fe-8be2-27723efeb5b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357698012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1357698012
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3261534642
Short name T389
Test name
Test status
Simulation time 2815719282 ps
CPU time 4.63 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:25 PM PDT 24
Peak memory 219972 kb
Host smart-e82c9ee4-4911-4698-b95a-4cf208fc3d16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261534642 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3261534642
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2177358164
Short name T89
Test name
Test status
Simulation time 75616145 ps
CPU time 1.51 seconds
Started Jul 19 04:55:03 PM PDT 24
Finished Jul 19 04:55:08 PM PDT 24
Peak memory 213564 kb
Host smart-112f475e-b78a-49dc-9791-1f23500af176
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177358164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2177358164
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.4150831376
Short name T415
Test name
Test status
Simulation time 56918131 ps
CPU time 0.73 seconds
Started Jul 19 04:55:06 PM PDT 24
Finished Jul 19 04:55:10 PM PDT 24
Peak memory 204980 kb
Host smart-bf749ac8-ac9d-48be-8d8a-fbc7d7c7cfa7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150831376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.4150831376
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2400132275
Short name T288
Test name
Test status
Simulation time 3148483931 ps
CPU time 9.25 seconds
Started Jul 19 04:55:04 PM PDT 24
Finished Jul 19 04:55:17 PM PDT 24
Peak memory 205196 kb
Host smart-dde1e350-1c96-495b-bb1e-f45694141b12
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400132275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2400132275
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1279129499
Short name T293
Test name
Test status
Simulation time 195726636 ps
CPU time 1.2 seconds
Started Jul 19 04:55:04 PM PDT 24
Finished Jul 19 04:55:08 PM PDT 24
Peak memory 205044 kb
Host smart-5d08a69a-2c6f-43f7-b566-28f1e2e27eba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279129499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1279129499
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3852361658
Short name T409
Test name
Test status
Simulation time 355803891 ps
CPU time 6.83 seconds
Started Jul 19 04:55:05 PM PDT 24
Finished Jul 19 04:55:14 PM PDT 24
Peak memory 205380 kb
Host smart-231454e2-70d8-482a-9b52-65cecc04914f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852361658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3852361658
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1644701319
Short name T153
Test name
Test status
Simulation time 188498471 ps
CPU time 3.52 seconds
Started Jul 19 04:55:05 PM PDT 24
Finished Jul 19 04:55:11 PM PDT 24
Peak memory 213652 kb
Host smart-3c154363-aed6-4666-9fbc-4316bde1bc99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644701319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1644701319
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2179192595
Short name T375
Test name
Test status
Simulation time 6229566320 ps
CPU time 11.38 seconds
Started Jul 19 04:55:04 PM PDT 24
Finished Jul 19 04:55:19 PM PDT 24
Peak memory 213780 kb
Host smart-88b78aa6-dd39-46f0-b2ac-7fcec8d9eedf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179192595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
179192595
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.967089451
Short name T440
Test name
Test status
Simulation time 240460354 ps
CPU time 1.64 seconds
Started Jul 19 04:55:06 PM PDT 24
Finished Jul 19 04:55:10 PM PDT 24
Peak memory 213444 kb
Host smart-17027545-8df6-41b3-98ab-55539e1640ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967089451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.967089451
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2721517170
Short name T307
Test name
Test status
Simulation time 9816263452 ps
CPU time 15.68 seconds
Started Jul 19 04:55:06 PM PDT 24
Finished Jul 19 04:55:24 PM PDT 24
Peak memory 205320 kb
Host smart-f4c5155b-4672-4999-893c-bc500d707f51
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721517170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2721517170
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.544949646
Short name T326
Test name
Test status
Simulation time 2328977227 ps
CPU time 7.55 seconds
Started Jul 19 04:55:13 PM PDT 24
Finished Jul 19 04:55:23 PM PDT 24
Peak memory 205232 kb
Host smart-feef6d98-9a84-466a-a615-b6510966113c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544949646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.544949646
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.471405081
Short name T79
Test name
Test status
Simulation time 154374176 ps
CPU time 0.98 seconds
Started Jul 19 04:55:14 PM PDT 24
Finished Jul 19 04:55:21 PM PDT 24
Peak memory 204920 kb
Host smart-d01408de-8e49-4d99-91a9-e1c7c3051230
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471405081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.471405081
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2612666864
Short name T107
Test name
Test status
Simulation time 511494788 ps
CPU time 4.12 seconds
Started Jul 19 04:55:06 PM PDT 24
Finished Jul 19 04:55:13 PM PDT 24
Peak memory 205432 kb
Host smart-6e040695-9520-4c13-bbdd-5507857a0082
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612666864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2612666864
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3884484605
Short name T61
Test name
Test status
Simulation time 153949607 ps
CPU time 4.66 seconds
Started Jul 19 04:55:05 PM PDT 24
Finished Jul 19 04:55:13 PM PDT 24
Peak memory 213652 kb
Host smart-b0717b05-2970-4861-8ad9-8f2704e2d1ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884484605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3884484605
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1705315402
Short name T60
Test name
Test status
Simulation time 114108952 ps
CPU time 2.21 seconds
Started Jul 19 04:55:06 PM PDT 24
Finished Jul 19 04:55:11 PM PDT 24
Peak memory 215624 kb
Host smart-c27fe9cb-75ef-49ca-bdd5-90bb9b9c2849
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705315402 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1705315402
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2900848310
Short name T128
Test name
Test status
Simulation time 216859390 ps
CPU time 1.67 seconds
Started Jul 19 04:55:06 PM PDT 24
Finished Jul 19 04:55:11 PM PDT 24
Peak memory 213540 kb
Host smart-a98f090a-e49c-4b71-8542-12e5cfba6a5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900848310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2900848310
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2357327268
Short name T417
Test name
Test status
Simulation time 3458662197 ps
CPU time 5.9 seconds
Started Jul 19 04:55:04 PM PDT 24
Finished Jul 19 04:55:13 PM PDT 24
Peak memory 205260 kb
Host smart-94fb20e0-9325-47c4-b909-40f8c33dd0f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357327268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.2357327268
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2335713196
Short name T379
Test name
Test status
Simulation time 1913705629 ps
CPU time 2.82 seconds
Started Jul 19 04:55:14 PM PDT 24
Finished Jul 19 04:55:19 PM PDT 24
Peak memory 205136 kb
Host smart-2f7dcc34-abb7-47e6-a1fe-8b4ce8187696
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335713196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2335713196
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4092176059
Short name T361
Test name
Test status
Simulation time 287144796 ps
CPU time 0.89 seconds
Started Jul 19 04:55:04 PM PDT 24
Finished Jul 19 04:55:08 PM PDT 24
Peak memory 205024 kb
Host smart-14d85c35-5f60-4c17-ba83-9fac2ff9a259
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092176059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
4092176059
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2252809342
Short name T119
Test name
Test status
Simulation time 859930234 ps
CPU time 7.3 seconds
Started Jul 19 04:55:06 PM PDT 24
Finished Jul 19 04:55:16 PM PDT 24
Peak memory 205352 kb
Host smart-d9faafa2-f253-4539-a708-38e5e7f9bb4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252809342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2252809342
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.4177815375
Short name T380
Test name
Test status
Simulation time 183129265 ps
CPU time 3.49 seconds
Started Jul 19 04:55:03 PM PDT 24
Finished Jul 19 04:55:10 PM PDT 24
Peak memory 213624 kb
Host smart-77d6e162-62c4-4d13-8e82-92a2b8bff631
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177815375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.4177815375
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3203266078
Short name T157
Test name
Test status
Simulation time 10654778578 ps
CPU time 22.04 seconds
Started Jul 19 04:55:03 PM PDT 24
Finished Jul 19 04:55:28 PM PDT 24
Peak memory 213652 kb
Host smart-c1dd2558-162b-4db7-bedc-d449a3651740
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203266078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
203266078
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1456661736
Short name T86
Test name
Test status
Simulation time 102903275 ps
CPU time 2.54 seconds
Started Jul 19 04:55:14 PM PDT 24
Finished Jul 19 04:55:19 PM PDT 24
Peak memory 221752 kb
Host smart-a2025b39-70ed-4381-8845-0423b3d6aa81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456661736 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1456661736
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.492045998
Short name T413
Test name
Test status
Simulation time 66466232 ps
CPU time 1.56 seconds
Started Jul 19 04:55:14 PM PDT 24
Finished Jul 19 04:55:18 PM PDT 24
Peak memory 213512 kb
Host smart-801852d4-0138-47ea-9643-67a60914ec47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492045998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.492045998
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.627296052
Short name T340
Test name
Test status
Simulation time 100313688827 ps
CPU time 161.79 seconds
Started Jul 19 04:55:05 PM PDT 24
Finished Jul 19 04:57:49 PM PDT 24
Peak memory 205336 kb
Host smart-e4a715b7-6212-4b74-a5db-da22bf031911
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627296052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rv_dm_jtag_dmi_csr_bit_bash.627296052
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3387291979
Short name T289
Test name
Test status
Simulation time 1259891904 ps
CPU time 2.08 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:22 PM PDT 24
Peak memory 205136 kb
Host smart-26149b54-30e5-4c12-a860-ace9bcfaded4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387291979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3387291979
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1866613747
Short name T322
Test name
Test status
Simulation time 271338887 ps
CPU time 0.95 seconds
Started Jul 19 04:55:05 PM PDT 24
Finished Jul 19 04:55:09 PM PDT 24
Peak memory 204992 kb
Host smart-a334d0a6-fa05-4e56-bb91-b351aefab822
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866613747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1866613747
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3347571155
Short name T121
Test name
Test status
Simulation time 1386143042 ps
CPU time 8.1 seconds
Started Jul 19 04:55:14 PM PDT 24
Finished Jul 19 04:55:28 PM PDT 24
Peak memory 205360 kb
Host smart-24727dbb-ea35-46a8-8e48-2cc77be77801
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347571155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3347571155
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2187324152
Short name T354
Test name
Test status
Simulation time 291343900 ps
CPU time 4.55 seconds
Started Jul 19 04:55:06 PM PDT 24
Finished Jul 19 04:55:13 PM PDT 24
Peak memory 213608 kb
Host smart-0aa4ea50-f39b-4c79-874d-a1d85fc590f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187324152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2187324152
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3171596847
Short name T382
Test name
Test status
Simulation time 1962735447 ps
CPU time 4.77 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:26 PM PDT 24
Peak memory 221752 kb
Host smart-867f1ec4-066f-4195-8c96-1f19dfc8f913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171596847 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3171596847
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1998885721
Short name T433
Test name
Test status
Simulation time 310071201 ps
CPU time 2.43 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:55:24 PM PDT 24
Peak memory 213460 kb
Host smart-dfe05474-cf0c-43b3-8054-39250de69882
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998885721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1998885721
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.473402370
Short name T333
Test name
Test status
Simulation time 14401860811 ps
CPU time 39.87 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:56:02 PM PDT 24
Peak memory 205328 kb
Host smart-106e6006-b2a5-4fdf-880b-2d4132e1fb0a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473402370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
rv_dm_jtag_dmi_csr_bit_bash.473402370
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4251006294
Short name T373
Test name
Test status
Simulation time 5574220375 ps
CPU time 6.23 seconds
Started Jul 19 04:55:13 PM PDT 24
Finished Jul 19 04:55:22 PM PDT 24
Peak memory 205280 kb
Host smart-48e5d8c9-5732-4b13-a4c9-1742c7a777d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251006294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
4251006294
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3274422635
Short name T310
Test name
Test status
Simulation time 1066231694 ps
CPU time 1.38 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:55:23 PM PDT 24
Peak memory 204992 kb
Host smart-f24c6e67-64cf-4663-92d9-03f706cec95d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274422635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3274422635
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.950548551
Short name T110
Test name
Test status
Simulation time 584090867 ps
CPU time 8.44 seconds
Started Jul 19 04:55:14 PM PDT 24
Finished Jul 19 04:55:28 PM PDT 24
Peak memory 205384 kb
Host smart-0de0d833-66ca-4883-afbe-46569c9e89af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950548551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.950548551
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3591663369
Short name T425
Test name
Test status
Simulation time 192851988 ps
CPU time 3.41 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:23 PM PDT 24
Peak memory 213696 kb
Host smart-e39a31d2-af0b-4ba5-abf8-184f8e7060cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591663369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3591663369
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4293029047
Short name T85
Test name
Test status
Simulation time 2673233751 ps
CPU time 20.35 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:40 PM PDT 24
Peak memory 213628 kb
Host smart-6a6853d4-2a4d-4fae-b218-525bfd9e3510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293029047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.4
293029047
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1305166573
Short name T321
Test name
Test status
Simulation time 1293116279 ps
CPU time 4.08 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:24 PM PDT 24
Peak memory 217660 kb
Host smart-1912c424-ee3e-4682-bbfe-288a6d7a3acb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305166573 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1305166573
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2805180772
Short name T384
Test name
Test status
Simulation time 177887466 ps
CPU time 1.65 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:55:24 PM PDT 24
Peak memory 213568 kb
Host smart-dc1fa128-6bbc-49cd-ba08-7c5e1be8ed1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805180772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2805180772
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.554025538
Short name T302
Test name
Test status
Simulation time 2983648094 ps
CPU time 5.27 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:25 PM PDT 24
Peak memory 205284 kb
Host smart-c06f1eb1-89ea-4ea2-add9-9d3b0e49b404
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554025538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.554025538
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2817758862
Short name T299
Test name
Test status
Simulation time 5599432776 ps
CPU time 14.87 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:36 PM PDT 24
Peak memory 205392 kb
Host smart-f3105e9b-a712-427f-bf77-2094b17d355d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817758862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2817758862
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3733157555
Short name T317
Test name
Test status
Simulation time 384428397 ps
CPU time 0.96 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:21 PM PDT 24
Peak memory 204996 kb
Host smart-43315289-c51d-4590-aba3-e3e16453ae9d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733157555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3733157555
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4124565327
Short name T63
Test name
Test status
Simulation time 1824004214 ps
CPU time 8.47 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:55:31 PM PDT 24
Peak memory 205440 kb
Host smart-3b8e30b5-3617-4be3-bf2e-c3abf0f1e8e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124565327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.4124565327
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3349080786
Short name T381
Test name
Test status
Simulation time 135563872 ps
CPU time 2.7 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:55:25 PM PDT 24
Peak memory 213680 kb
Host smart-b59e1b4c-6c48-445b-bade-b0d48370b47c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349080786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3349080786
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3492133511
Short name T407
Test name
Test status
Simulation time 882595520 ps
CPU time 11.43 seconds
Started Jul 19 04:55:14 PM PDT 24
Finished Jul 19 04:55:31 PM PDT 24
Peak memory 213532 kb
Host smart-249bc5ef-5ede-41f1-8a6a-05486cf92a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492133511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
492133511
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1223309051
Short name T412
Test name
Test status
Simulation time 351195626 ps
CPU time 4.12 seconds
Started Jul 19 04:55:13 PM PDT 24
Finished Jul 19 04:55:20 PM PDT 24
Peak memory 219048 kb
Host smart-d20907e8-a697-4a50-87d4-a08fcf2257e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223309051 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1223309051
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4245990360
Short name T127
Test name
Test status
Simulation time 215482483 ps
CPU time 2.35 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:55:25 PM PDT 24
Peak memory 213508 kb
Host smart-06df1860-c230-4cb5-b12f-8bed0ee187c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245990360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.4245990360
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1380622895
Short name T330
Test name
Test status
Simulation time 13833751668 ps
CPU time 24.22 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:44 PM PDT 24
Peak memory 205332 kb
Host smart-39abc73e-0eba-468c-be74-ee279b64c2dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380622895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.1380622895
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2037959445
Short name T342
Test name
Test status
Simulation time 4532635194 ps
CPU time 6.71 seconds
Started Jul 19 04:55:17 PM PDT 24
Finished Jul 19 04:55:30 PM PDT 24
Peak memory 205300 kb
Host smart-6d2aba18-7954-4e90-a66f-52247ab5456b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037959445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2037959445
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3555137026
Short name T324
Test name
Test status
Simulation time 146009481 ps
CPU time 0.82 seconds
Started Jul 19 04:55:14 PM PDT 24
Finished Jul 19 04:55:20 PM PDT 24
Peak memory 205020 kb
Host smart-f63a48df-89f1-44b3-b3fc-f97ba39ba1f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555137026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3555137026
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3356415085
Short name T108
Test name
Test status
Simulation time 528683938 ps
CPU time 3.93 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:55:26 PM PDT 24
Peak memory 205420 kb
Host smart-fcf11853-d635-4683-8fcf-9bb5c42aaeaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356415085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3356415085
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2396866751
Short name T368
Test name
Test status
Simulation time 982103589 ps
CPU time 3.69 seconds
Started Jul 19 04:55:14 PM PDT 24
Finished Jul 19 04:55:23 PM PDT 24
Peak memory 213624 kb
Host smart-7ae4ef5d-03e0-460d-ac7a-037c29629f90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396866751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2396866751
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.414214035
Short name T343
Test name
Test status
Simulation time 86110979 ps
CPU time 2.73 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:24 PM PDT 24
Peak memory 217712 kb
Host smart-ddc28f5e-0ae8-452b-b041-9de915e4ccf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414214035 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.414214035
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1066813096
Short name T113
Test name
Test status
Simulation time 161874648 ps
CPU time 2.61 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:55:25 PM PDT 24
Peak memory 213552 kb
Host smart-2c9ad734-11a8-4cb3-8efd-de384b0e10aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066813096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1066813096
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2126785158
Short name T328
Test name
Test status
Simulation time 26343135762 ps
CPU time 19.15 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:55:41 PM PDT 24
Peak memory 205292 kb
Host smart-2bc71a1e-91b3-400b-803a-68b483566a07
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126785158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2126785158
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2397404933
Short name T287
Test name
Test status
Simulation time 3921956653 ps
CPU time 1.94 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:22 PM PDT 24
Peak memory 205248 kb
Host smart-1a5a1225-312d-4b0f-ad56-6394392e4b20
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397404933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2397404933
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.357964560
Short name T348
Test name
Test status
Simulation time 641441421 ps
CPU time 2.4 seconds
Started Jul 19 04:55:16 PM PDT 24
Finished Jul 19 04:55:25 PM PDT 24
Peak memory 204924 kb
Host smart-101a1ddb-1d30-48a5-8140-d54e467f9380
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357964560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.357964560
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1504888505
Short name T403
Test name
Test status
Simulation time 306596777 ps
CPU time 4.49 seconds
Started Jul 19 04:55:15 PM PDT 24
Finished Jul 19 04:55:26 PM PDT 24
Peak memory 205424 kb
Host smart-b7942d28-78de-4d1e-94b4-8c730eb560a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504888505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1504888505
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1705078141
Short name T436
Test name
Test status
Simulation time 114839217 ps
CPU time 2.34 seconds
Started Jul 19 04:55:14 PM PDT 24
Finished Jul 19 04:55:21 PM PDT 24
Peak memory 213664 kb
Host smart-18157b0e-42e3-4aaf-824d-ede34f62a654
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705078141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1705078141
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4116226010
Short name T362
Test name
Test status
Simulation time 2754715742 ps
CPU time 15.29 seconds
Started Jul 19 04:55:14 PM PDT 24
Finished Jul 19 04:55:35 PM PDT 24
Peak memory 213596 kb
Host smart-e0768634-0953-486e-b42c-5eb249310bb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116226010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4
116226010
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1540508512
Short name T393
Test name
Test status
Simulation time 1093178524 ps
CPU time 65.63 seconds
Started Jul 19 04:54:42 PM PDT 24
Finished Jul 19 04:55:51 PM PDT 24
Peak memory 217972 kb
Host smart-59a8bfa4-1f23-4809-ba60-f2136043fc43
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540508512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1540508512
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3609729981
Short name T419
Test name
Test status
Simulation time 9789716023 ps
CPU time 33.89 seconds
Started Jul 19 04:54:50 PM PDT 24
Finished Jul 19 04:55:29 PM PDT 24
Peak memory 205484 kb
Host smart-2574ca5a-eb2a-4bcc-b82f-168e4f56eadd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609729981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3609729981
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2357992507
Short name T111
Test name
Test status
Simulation time 220692233 ps
CPU time 2.63 seconds
Started Jul 19 04:54:48 PM PDT 24
Finished Jul 19 04:54:56 PM PDT 24
Peak memory 213536 kb
Host smart-8c113611-71cc-43e5-af9b-cdee9a719b6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357992507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2357992507
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3268747593
Short name T339
Test name
Test status
Simulation time 590749419 ps
CPU time 3.9 seconds
Started Jul 19 04:54:50 PM PDT 24
Finished Jul 19 04:55:00 PM PDT 24
Peak memory 219032 kb
Host smart-b37b45a8-7267-4f9e-9123-a17393c57a85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268747593 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3268747593
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2937004750
Short name T423
Test name
Test status
Simulation time 201109611 ps
CPU time 2.37 seconds
Started Jul 19 04:54:50 PM PDT 24
Finished Jul 19 04:54:58 PM PDT 24
Peak memory 213520 kb
Host smart-db57f453-04f8-4b68-b941-7650bfb14d00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937004750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2937004750
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2147149669
Short name T392
Test name
Test status
Simulation time 86122745061 ps
CPU time 55.65 seconds
Started Jul 19 04:54:47 PM PDT 24
Finished Jul 19 04:55:46 PM PDT 24
Peak memory 205284 kb
Host smart-41cd592a-f68e-49e5-ab05-d1d5acae3425
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147149669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2147149669
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3365688466
Short name T290
Test name
Test status
Simulation time 15911547531 ps
CPU time 18.34 seconds
Started Jul 19 04:54:42 PM PDT 24
Finished Jul 19 04:55:03 PM PDT 24
Peak memory 205372 kb
Host smart-aad468d8-febc-4451-95ed-fd63f695e59b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365688466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.3365688466
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3754758238
Short name T100
Test name
Test status
Simulation time 3455441879 ps
CPU time 2.9 seconds
Started Jul 19 04:54:41 PM PDT 24
Finished Jul 19 04:54:47 PM PDT 24
Peak memory 205260 kb
Host smart-69519a29-9e52-46bb-afa4-54a5aedb1efd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754758238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3754758238
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2914714254
Short name T305
Test name
Test status
Simulation time 7044628292 ps
CPU time 13.25 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:54:54 PM PDT 24
Peak memory 205256 kb
Host smart-64087961-827c-4e28-baa0-58c851bcbbcb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914714254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
914714254
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1493491887
Short name T319
Test name
Test status
Simulation time 161984376 ps
CPU time 1.04 seconds
Started Jul 19 04:54:39 PM PDT 24
Finished Jul 19 04:54:42 PM PDT 24
Peak memory 204948 kb
Host smart-86624219-4b88-4c76-9c77-e348cdfc42ac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493491887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.1493491887
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2072600373
Short name T401
Test name
Test status
Simulation time 5988157623 ps
CPU time 16.8 seconds
Started Jul 19 04:54:36 PM PDT 24
Finished Jul 19 04:54:54 PM PDT 24
Peak memory 205384 kb
Host smart-ad1cf406-55bd-4e53-b4ca-f77b3c77b7cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072600373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2072600373
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.292013892
Short name T366
Test name
Test status
Simulation time 625749407 ps
CPU time 1.19 seconds
Started Jul 19 04:54:39 PM PDT 24
Finished Jul 19 04:54:42 PM PDT 24
Peak memory 205024 kb
Host smart-f91cf1ce-b6ee-4478-9f19-6ba954b8f13f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292013892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.292013892
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2404239631
Short name T367
Test name
Test status
Simulation time 164679074 ps
CPU time 1.12 seconds
Started Jul 19 04:54:38 PM PDT 24
Finished Jul 19 04:54:41 PM PDT 24
Peak memory 205000 kb
Host smart-dfae82b9-03a0-4530-a03b-788d7be1860d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404239631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
404239631
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.482909521
Short name T351
Test name
Test status
Simulation time 229160788 ps
CPU time 0.72 seconds
Started Jul 19 04:54:46 PM PDT 24
Finished Jul 19 04:54:50 PM PDT 24
Peak memory 204988 kb
Host smart-c9fa9e55-2a60-4695-8bbd-d29e38222fde
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482909521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.482909521
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.225745123
Short name T355
Test name
Test status
Simulation time 118157350 ps
CPU time 0.8 seconds
Started Jul 19 04:54:51 PM PDT 24
Finished Jul 19 04:54:57 PM PDT 24
Peak memory 205000 kb
Host smart-97735383-ac1e-4fcf-ae45-0bfe5170f3b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225745123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.225745123
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3983439870
Short name T377
Test name
Test status
Simulation time 170933522 ps
CPU time 3.74 seconds
Started Jul 19 04:54:50 PM PDT 24
Finished Jul 19 04:55:00 PM PDT 24
Peak memory 205288 kb
Host smart-11c16114-409f-42c4-b135-b880336b310a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983439870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3983439870
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.546185671
Short name T125
Test name
Test status
Simulation time 33160774817 ps
CPU time 169.99 seconds
Started Jul 19 04:54:49 PM PDT 24
Finished Jul 19 04:57:45 PM PDT 24
Peak memory 221772 kb
Host smart-8b97a774-6498-469a-8a8e-1e8e9b80b8c8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546185671 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.546185671
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2301497327
Short name T371
Test name
Test status
Simulation time 131526898 ps
CPU time 2.64 seconds
Started Jul 19 04:54:47 PM PDT 24
Finished Jul 19 04:54:54 PM PDT 24
Peak memory 213644 kb
Host smart-21720d25-7252-46b4-b7b7-373f86988d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301497327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2301497327
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3863352599
Short name T159
Test name
Test status
Simulation time 2413404056 ps
CPU time 10.68 seconds
Started Jul 19 04:54:44 PM PDT 24
Finished Jul 19 04:54:57 PM PDT 24
Peak memory 213544 kb
Host smart-efe07e45-51c3-4847-8e76-9e62e952a7d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863352599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3863352599
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4093170
Short name T88
Test name
Test status
Simulation time 8602574139 ps
CPU time 80.87 seconds
Started Jul 19 04:54:50 PM PDT 24
Finished Jul 19 04:56:16 PM PDT 24
Peak memory 213644 kb
Host smart-1162a9f9-9815-4bd4-9008-2057ba9fe4b4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM
_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.rv_dm_csr_aliasing.4093170
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3922750835
Short name T114
Test name
Test status
Simulation time 7287085512 ps
CPU time 41.11 seconds
Started Jul 19 04:54:47 PM PDT 24
Finished Jul 19 04:55:31 PM PDT 24
Peak memory 213648 kb
Host smart-5a4923f7-5420-4a51-99bc-2765a14e2bfc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922750835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3922750835
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1108738895
Short name T118
Test name
Test status
Simulation time 220419837 ps
CPU time 1.55 seconds
Started Jul 19 04:54:50 PM PDT 24
Finished Jul 19 04:54:57 PM PDT 24
Peak memory 213568 kb
Host smart-c2297117-0cfb-4400-958b-eecae34845f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108738895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1108738895
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.616686130
Short name T96
Test name
Test status
Simulation time 4963288638 ps
CPU time 8.73 seconds
Started Jul 19 04:54:46 PM PDT 24
Finished Jul 19 04:54:58 PM PDT 24
Peak memory 221908 kb
Host smart-519420c5-44ef-428a-8e5d-d73af8a29737
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616686130 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.616686130
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1226972360
Short name T103
Test name
Test status
Simulation time 246721357 ps
CPU time 2.3 seconds
Started Jul 19 04:54:55 PM PDT 24
Finished Jul 19 04:55:01 PM PDT 24
Peak memory 213208 kb
Host smart-fca82b48-e34b-4149-9952-a292cd8eec89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226972360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1226972360
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4090845058
Short name T297
Test name
Test status
Simulation time 45987764692 ps
CPU time 28.39 seconds
Started Jul 19 04:54:47 PM PDT 24
Finished Jul 19 04:55:19 PM PDT 24
Peak memory 205236 kb
Host smart-b1edc7a3-0da8-4cf1-be84-788cde36f568
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090845058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.4090845058
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4236503635
Short name T345
Test name
Test status
Simulation time 44237099649 ps
CPU time 36.85 seconds
Started Jul 19 04:54:45 PM PDT 24
Finished Jul 19 04:55:25 PM PDT 24
Peak memory 205384 kb
Host smart-9d34d91a-d1b8-4c7f-9186-e8bd78f4016e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236503635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.4236503635
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1718856071
Short name T97
Test name
Test status
Simulation time 2438388597 ps
CPU time 8 seconds
Started Jul 19 04:54:49 PM PDT 24
Finished Jul 19 04:55:02 PM PDT 24
Peak memory 205548 kb
Host smart-70291d6b-8e79-4fbd-b1c8-b1c0a6781bb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718856071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1718856071
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1949914303
Short name T357
Test name
Test status
Simulation time 4891209013 ps
CPU time 14.5 seconds
Started Jul 19 04:54:48 PM PDT 24
Finished Jul 19 04:55:06 PM PDT 24
Peak memory 205256 kb
Host smart-feb819b6-0def-46a1-bab6-2dc8504be5dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949914303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
949914303
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1440278523
Short name T300
Test name
Test status
Simulation time 584962445 ps
CPU time 1.69 seconds
Started Jul 19 04:54:50 PM PDT 24
Finished Jul 19 04:54:57 PM PDT 24
Peak memory 204892 kb
Host smart-595c6586-8d3d-414b-aec6-5116dabc5b0a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440278523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1440278523
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3710406761
Short name T298
Test name
Test status
Simulation time 4477138139 ps
CPU time 5.2 seconds
Started Jul 19 04:54:44 PM PDT 24
Finished Jul 19 04:54:52 PM PDT 24
Peak memory 205332 kb
Host smart-79d61c6e-f27e-469c-bd90-95d5ca35865c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710406761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3710406761
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2596491809
Short name T331
Test name
Test status
Simulation time 814094242 ps
CPU time 2.85 seconds
Started Jul 19 04:54:53 PM PDT 24
Finished Jul 19 04:55:00 PM PDT 24
Peak memory 204980 kb
Host smart-e6ef5164-717a-4a14-b8bb-03a45245f5fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596491809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2596491809
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3975040224
Short name T349
Test name
Test status
Simulation time 79688445 ps
CPU time 0.91 seconds
Started Jul 19 04:54:47 PM PDT 24
Finished Jul 19 04:54:51 PM PDT 24
Peak memory 204972 kb
Host smart-94af90ed-88ca-459a-8332-4a8e590eac7d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975040224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
975040224
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3340971047
Short name T336
Test name
Test status
Simulation time 117869078 ps
CPU time 0.75 seconds
Started Jul 19 04:54:51 PM PDT 24
Finished Jul 19 04:54:57 PM PDT 24
Peak memory 204916 kb
Host smart-2870ddfc-4c3d-4774-8706-5405de200eda
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340971047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3340971047
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3446475351
Short name T398
Test name
Test status
Simulation time 154918932 ps
CPU time 0.85 seconds
Started Jul 19 04:54:55 PM PDT 24
Finished Jul 19 04:54:59 PM PDT 24
Peak memory 204924 kb
Host smart-202fca21-32ef-40ed-8067-2e5d497109c6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446475351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3446475351
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3857615204
Short name T120
Test name
Test status
Simulation time 1368857313 ps
CPU time 8.08 seconds
Started Jul 19 04:54:48 PM PDT 24
Finished Jul 19 04:55:01 PM PDT 24
Peak memory 205304 kb
Host smart-9d2a9106-2571-40a3-b7ce-72480884035f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857615204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3857615204
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2924927872
Short name T75
Test name
Test status
Simulation time 81387669327 ps
CPU time 856.32 seconds
Started Jul 19 04:54:45 PM PDT 24
Finished Jul 19 05:09:04 PM PDT 24
Peak memory 231984 kb
Host smart-242349bf-35e3-48ef-ab2f-fd488aa2cf0f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924927872 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2924927872
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.658628973
Short name T62
Test name
Test status
Simulation time 261898096 ps
CPU time 4.51 seconds
Started Jul 19 04:54:49 PM PDT 24
Finished Jul 19 04:54:59 PM PDT 24
Peak memory 213760 kb
Host smart-62dfd598-cf41-498e-8e77-d4c9f02fed92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658628973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.658628973
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1167558789
Short name T156
Test name
Test status
Simulation time 5913994551 ps
CPU time 28.66 seconds
Started Jul 19 04:54:49 PM PDT 24
Finished Jul 19 04:55:23 PM PDT 24
Peak memory 213752 kb
Host smart-73905d43-8cb7-4568-b433-34bb41349db8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167558789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1167558789
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3743315811
Short name T341
Test name
Test status
Simulation time 2228058811 ps
CPU time 67.7 seconds
Started Jul 19 04:54:47 PM PDT 24
Finished Jul 19 04:55:59 PM PDT 24
Peak memory 213504 kb
Host smart-20ca1fcc-3532-403c-a353-7269a0903c36
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743315811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3743315811
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1815070856
Short name T312
Test name
Test status
Simulation time 30469296072 ps
CPU time 79.19 seconds
Started Jul 19 04:54:45 PM PDT 24
Finished Jul 19 04:56:07 PM PDT 24
Peak memory 205400 kb
Host smart-db9e955b-3698-4d78-9b95-2e2f4edbf859
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815070856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1815070856
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2858271415
Short name T64
Test name
Test status
Simulation time 1290552499 ps
CPU time 2.74 seconds
Started Jul 19 04:54:49 PM PDT 24
Finished Jul 19 04:54:57 PM PDT 24
Peak memory 213568 kb
Host smart-b1f977de-3c3e-4fca-8e32-5ec722e3da20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858271415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2858271415
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.786993234
Short name T376
Test name
Test status
Simulation time 1300370063 ps
CPU time 4.25 seconds
Started Jul 19 04:54:49 PM PDT 24
Finished Jul 19 04:54:59 PM PDT 24
Peak memory 220380 kb
Host smart-265fe9d5-1f9d-4052-9746-6e70bd033c94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786993234 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.786993234
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1309381120
Short name T101
Test name
Test status
Simulation time 151416181 ps
CPU time 1.6 seconds
Started Jul 19 04:54:50 PM PDT 24
Finished Jul 19 04:54:57 PM PDT 24
Peak memory 213512 kb
Host smart-07b8b324-2407-49f2-89a7-89e8d549c4a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309381120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1309381120
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2969083880
Short name T437
Test name
Test status
Simulation time 83798896109 ps
CPU time 64.54 seconds
Started Jul 19 04:54:46 PM PDT 24
Finished Jul 19 04:55:53 PM PDT 24
Peak memory 205284 kb
Host smart-56b6cd03-475f-4ea5-af0a-c12688e4e355
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969083880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2969083880
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1155159334
Short name T323
Test name
Test status
Simulation time 17794239000 ps
CPU time 14.62 seconds
Started Jul 19 04:54:55 PM PDT 24
Finished Jul 19 04:55:13 PM PDT 24
Peak memory 205264 kb
Host smart-fe7fa10d-3c65-40b1-ad4a-9ef63b67ceb4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155159334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.1155159334
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1815261444
Short name T338
Test name
Test status
Simulation time 6418103373 ps
CPU time 16.91 seconds
Started Jul 19 04:54:47 PM PDT 24
Finished Jul 19 04:55:08 PM PDT 24
Peak memory 205260 kb
Host smart-1b11ef48-014c-4005-b2fd-79e47841fab4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815261444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
815261444
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2508572392
Short name T388
Test name
Test status
Simulation time 1856373668 ps
CPU time 2.03 seconds
Started Jul 19 04:54:49 PM PDT 24
Finished Jul 19 04:54:57 PM PDT 24
Peak memory 204944 kb
Host smart-b1d0399d-68e6-4631-a33c-24c692d155bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508572392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2508572392
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.560014675
Short name T430
Test name
Test status
Simulation time 17745026912 ps
CPU time 11.03 seconds
Started Jul 19 04:54:45 PM PDT 24
Finished Jul 19 04:54:59 PM PDT 24
Peak memory 205280 kb
Host smart-1a291d3c-42fc-4fe5-8b4d-6889e3fec434
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560014675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.560014675
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3088272004
Short name T309
Test name
Test status
Simulation time 911680016 ps
CPU time 1.72 seconds
Started Jul 19 04:54:48 PM PDT 24
Finished Jul 19 04:54:54 PM PDT 24
Peak memory 205004 kb
Host smart-ceb453f0-d347-4345-bff3-f5075facc3eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088272004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3088272004
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4063189613
Short name T369
Test name
Test status
Simulation time 440840598 ps
CPU time 1.5 seconds
Started Jul 19 04:54:45 PM PDT 24
Finished Jul 19 04:54:49 PM PDT 24
Peak memory 204924 kb
Host smart-89820a5d-bb23-45f2-a8e0-892a332160ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063189613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.4
063189613
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.935082008
Short name T405
Test name
Test status
Simulation time 53165232 ps
CPU time 0.85 seconds
Started Jul 19 04:54:46 PM PDT 24
Finished Jul 19 04:54:50 PM PDT 24
Peak memory 204996 kb
Host smart-8ecc87f6-08e6-43c2-bb0f-735a853abf78
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935082008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.935082008
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.195341050
Short name T316
Test name
Test status
Simulation time 105935854 ps
CPU time 0.67 seconds
Started Jul 19 04:54:47 PM PDT 24
Finished Jul 19 04:54:50 PM PDT 24
Peak memory 204916 kb
Host smart-22c51d69-f204-4a9d-823e-baefbdc0b42b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195341050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.195341050
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3551764433
Short name T370
Test name
Test status
Simulation time 257549168 ps
CPU time 4.47 seconds
Started Jul 19 04:54:45 PM PDT 24
Finished Jul 19 04:54:52 PM PDT 24
Peak memory 205408 kb
Host smart-bc249e66-9331-4a7b-8838-afeb92cfe172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551764433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3551764433
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2809526496
Short name T161
Test name
Test status
Simulation time 58130938613 ps
CPU time 494.65 seconds
Started Jul 19 04:54:49 PM PDT 24
Finished Jul 19 05:03:10 PM PDT 24
Peak memory 230156 kb
Host smart-292f3202-097c-4675-b076-7adcbc3dfe82
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809526496 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2809526496
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1826717082
Short name T438
Test name
Test status
Simulation time 287537980 ps
CPU time 4.19 seconds
Started Jul 19 04:54:49 PM PDT 24
Finished Jul 19 04:54:59 PM PDT 24
Peak memory 213888 kb
Host smart-b362c0bf-8106-4a2e-83e3-086e46100d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826717082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1826717082
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.472076713
Short name T95
Test name
Test status
Simulation time 1975648172 ps
CPU time 17.39 seconds
Started Jul 19 04:54:49 PM PDT 24
Finished Jul 19 04:55:11 PM PDT 24
Peak memory 213616 kb
Host smart-66dfdbaa-dd87-4edd-8a78-355a8c2f2ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472076713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.472076713
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.621904587
Short name T334
Test name
Test status
Simulation time 3157462962 ps
CPU time 5.73 seconds
Started Jul 19 04:54:51 PM PDT 24
Finished Jul 19 04:55:02 PM PDT 24
Peak memory 219588 kb
Host smart-2abb9217-005f-40fa-be8f-73675e0ad254
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621904587 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.621904587
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2143097091
Short name T112
Test name
Test status
Simulation time 266311440 ps
CPU time 1.67 seconds
Started Jul 19 04:54:55 PM PDT 24
Finished Jul 19 04:55:00 PM PDT 24
Peak memory 213248 kb
Host smart-062c98bb-d5ad-4e76-ac9d-744f3e2bd94c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143097091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2143097091
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4021071346
Short name T325
Test name
Test status
Simulation time 5067255115 ps
CPU time 2.49 seconds
Started Jul 19 04:54:45 PM PDT 24
Finished Jul 19 04:54:51 PM PDT 24
Peak memory 205296 kb
Host smart-e0b7fd24-757b-4634-af63-259d5f01424f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021071346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.4021071346
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.548526004
Short name T329
Test name
Test status
Simulation time 6749998989 ps
CPU time 5.61 seconds
Started Jul 19 04:54:51 PM PDT 24
Finished Jul 19 04:55:02 PM PDT 24
Peak memory 205264 kb
Host smart-c6722242-f22c-4e2a-9d43-f75283994eb7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548526004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.548526004
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.718595709
Short name T295
Test name
Test status
Simulation time 165449926 ps
CPU time 0.93 seconds
Started Jul 19 04:54:46 PM PDT 24
Finished Jul 19 04:54:50 PM PDT 24
Peak memory 205000 kb
Host smart-3cb77ee3-0810-4243-811b-d103f6803086
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718595709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.718595709
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3743227549
Short name T105
Test name
Test status
Simulation time 751589485 ps
CPU time 3.96 seconds
Started Jul 19 04:54:51 PM PDT 24
Finished Jul 19 04:55:00 PM PDT 24
Peak memory 205444 kb
Host smart-15bd7924-7a49-4c0e-a79d-7e714c0f8021
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743227549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3743227549
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3060995977
Short name T372
Test name
Test status
Simulation time 312868166 ps
CPU time 4.79 seconds
Started Jul 19 04:54:51 PM PDT 24
Finished Jul 19 04:55:01 PM PDT 24
Peak memory 213704 kb
Host smart-faa11617-3ac0-4c84-8831-cef32e95fbfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060995977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3060995977
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3472298852
Short name T126
Test name
Test status
Simulation time 4541261451 ps
CPU time 20.2 seconds
Started Jul 19 04:54:50 PM PDT 24
Finished Jul 19 04:55:16 PM PDT 24
Peak memory 213752 kb
Host smart-0af31d86-7ba2-4799-95e4-fc4afbf8bc91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472298852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3472298852
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3640162453
Short name T344
Test name
Test status
Simulation time 7327474774 ps
CPU time 7.46 seconds
Started Jul 19 04:54:50 PM PDT 24
Finished Jul 19 04:55:04 PM PDT 24
Peak memory 220380 kb
Host smart-936ceed2-61d6-4626-9ae7-6c2feb965faa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640162453 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3640162453
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3989504991
Short name T116
Test name
Test status
Simulation time 130557117 ps
CPU time 1.47 seconds
Started Jul 19 04:54:50 PM PDT 24
Finished Jul 19 04:54:57 PM PDT 24
Peak memory 213512 kb
Host smart-c07ed17a-a19d-4eec-b0d5-b523c35903ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989504991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3989504991
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3356586688
Short name T308
Test name
Test status
Simulation time 9365346482 ps
CPU time 13.72 seconds
Started Jul 19 04:54:46 PM PDT 24
Finished Jul 19 04:55:02 PM PDT 24
Peak memory 205360 kb
Host smart-5dc0f498-6cbe-46b7-87c5-2708821e0343
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356586688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.3356586688
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2769901534
Short name T397
Test name
Test status
Simulation time 4105937998 ps
CPU time 2.59 seconds
Started Jul 19 04:54:46 PM PDT 24
Finished Jul 19 04:54:52 PM PDT 24
Peak memory 205164 kb
Host smart-4c709dc7-3302-4c38-b3f6-8d188b1429c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769901534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
769901534
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4007530285
Short name T78
Test name
Test status
Simulation time 235663333 ps
CPU time 1.03 seconds
Started Jul 19 04:54:48 PM PDT 24
Finished Jul 19 04:54:54 PM PDT 24
Peak memory 204972 kb
Host smart-cd26f25c-3ca5-4335-bd8c-00d1d129dd1e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007530285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.4
007530285
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2257872095
Short name T420
Test name
Test status
Simulation time 1067682210 ps
CPU time 7.6 seconds
Started Jul 19 04:54:50 PM PDT 24
Finished Jul 19 04:55:03 PM PDT 24
Peak memory 205308 kb
Host smart-1a29c2d0-10f1-4830-bf66-afa7650c7940
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257872095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2257872095
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.4242672729
Short name T395
Test name
Test status
Simulation time 42720351700 ps
CPU time 146.22 seconds
Started Jul 19 04:54:47 PM PDT 24
Finished Jul 19 04:57:17 PM PDT 24
Peak memory 221896 kb
Host smart-13fd1f59-7aba-4d3d-8122-b5012f460045
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242672729 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.4242672729
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2969174302
Short name T81
Test name
Test status
Simulation time 161150844 ps
CPU time 5.21 seconds
Started Jul 19 04:54:49 PM PDT 24
Finished Jul 19 04:55:00 PM PDT 24
Peak memory 213864 kb
Host smart-cd3f0c20-7899-4370-8355-3aff1b2a4eed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969174302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2969174302
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2421478816
Short name T404
Test name
Test status
Simulation time 2930900488 ps
CPU time 11.24 seconds
Started Jul 19 04:54:50 PM PDT 24
Finished Jul 19 04:55:06 PM PDT 24
Peak memory 213644 kb
Host smart-4cce95fc-c7c6-49a5-bc1f-745fed0ba5a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421478816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2421478816
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1495831195
Short name T410
Test name
Test status
Simulation time 234869484 ps
CPU time 2.5 seconds
Started Jul 19 04:55:00 PM PDT 24
Finished Jul 19 04:55:06 PM PDT 24
Peak memory 219184 kb
Host smart-4d9e60a6-e845-4300-9003-f01df9f21b24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495831195 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1495831195
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.281013053
Short name T358
Test name
Test status
Simulation time 59302668 ps
CPU time 2.06 seconds
Started Jul 19 04:55:00 PM PDT 24
Finished Jul 19 04:55:06 PM PDT 24
Peak memory 213444 kb
Host smart-3511958c-7792-4e33-86f8-63dd573e16f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281013053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.281013053
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1533526280
Short name T431
Test name
Test status
Simulation time 16705117740 ps
CPU time 24.48 seconds
Started Jul 19 04:55:01 PM PDT 24
Finished Jul 19 04:55:29 PM PDT 24
Peak memory 205268 kb
Host smart-a191904f-92ae-43bc-bd0a-0d1aa9ed03c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533526280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.1533526280
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3934075149
Short name T314
Test name
Test status
Simulation time 903927257 ps
CPU time 1.81 seconds
Started Jul 19 04:55:00 PM PDT 24
Finished Jul 19 04:55:05 PM PDT 24
Peak memory 205144 kb
Host smart-b60810c9-123c-4e85-a77a-604dc44610f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934075149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
934075149
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1984394034
Short name T365
Test name
Test status
Simulation time 180623229 ps
CPU time 0.85 seconds
Started Jul 19 04:54:57 PM PDT 24
Finished Jul 19 04:55:02 PM PDT 24
Peak memory 204928 kb
Host smart-fdc08497-f3af-4cbb-af16-e6e570447248
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984394034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
984394034
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.601694273
Short name T426
Test name
Test status
Simulation time 7897810527 ps
CPU time 11.1 seconds
Started Jul 19 04:55:00 PM PDT 24
Finished Jul 19 04:55:15 PM PDT 24
Peak memory 205452 kb
Host smart-db9d7d81-f422-4a15-bf87-ae99e9e4c81b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601694273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.601694273
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2952281926
Short name T162
Test name
Test status
Simulation time 24546750390 ps
CPU time 74.05 seconds
Started Jul 19 04:54:59 PM PDT 24
Finished Jul 19 04:56:16 PM PDT 24
Peak memory 214548 kb
Host smart-c1026cc2-066f-42fa-81b0-86177b1f600e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952281926 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2952281926
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.538312182
Short name T303
Test name
Test status
Simulation time 166358662 ps
CPU time 2.5 seconds
Started Jul 19 04:54:57 PM PDT 24
Finished Jul 19 04:55:03 PM PDT 24
Peak memory 213632 kb
Host smart-2ee1950f-b3fe-4fd1-b5be-f61afa55379c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538312182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.538312182
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.867189168
Short name T346
Test name
Test status
Simulation time 872966048 ps
CPU time 10.83 seconds
Started Jul 19 04:54:57 PM PDT 24
Finished Jul 19 04:55:12 PM PDT 24
Peak memory 213644 kb
Host smart-9aec345e-6a3d-4cb0-a639-001443962aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867189168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.867189168
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.428372556
Short name T414
Test name
Test status
Simulation time 760154712 ps
CPU time 3.94 seconds
Started Jul 19 04:54:59 PM PDT 24
Finished Jul 19 04:55:07 PM PDT 24
Peak memory 218936 kb
Host smart-419b54f0-251e-48ed-8255-fb353a6728d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428372556 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.428372556
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3225467
Short name T102
Test name
Test status
Simulation time 291239705 ps
CPU time 1.58 seconds
Started Jul 19 04:54:59 PM PDT 24
Finished Jul 19 04:55:04 PM PDT 24
Peak memory 213424 kb
Host smart-b5feb08c-12bb-4942-b194-bb2977314a91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3225467
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2063946937
Short name T353
Test name
Test status
Simulation time 8512602244 ps
CPU time 21.35 seconds
Started Jul 19 04:54:58 PM PDT 24
Finished Jul 19 04:55:23 PM PDT 24
Peak memory 205312 kb
Host smart-8a492e80-3c26-432b-a023-1934d9cdbb2d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063946937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.2063946937
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1195449350
Short name T306
Test name
Test status
Simulation time 10143716287 ps
CPU time 31.03 seconds
Started Jul 19 04:55:00 PM PDT 24
Finished Jul 19 04:55:35 PM PDT 24
Peak memory 205228 kb
Host smart-0790b0a6-8da3-44a8-832f-b6ac676d75cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195449350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
195449350
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1184517660
Short name T396
Test name
Test status
Simulation time 251687760 ps
CPU time 1.32 seconds
Started Jul 19 04:55:01 PM PDT 24
Finished Jul 19 04:55:06 PM PDT 24
Peak memory 204904 kb
Host smart-da81c8ac-a7a1-4b55-91f3-35ad8ee34ed3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184517660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1
184517660
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1619559567
Short name T411
Test name
Test status
Simulation time 212146572 ps
CPU time 7.03 seconds
Started Jul 19 04:54:57 PM PDT 24
Finished Jul 19 04:55:08 PM PDT 24
Peak memory 205352 kb
Host smart-a1227d32-15d0-4b14-9dde-58613d6ddda6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619559567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1619559567
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2286989449
Short name T408
Test name
Test status
Simulation time 34623306793 ps
CPU time 222.98 seconds
Started Jul 19 04:54:59 PM PDT 24
Finished Jul 19 04:58:46 PM PDT 24
Peak memory 222000 kb
Host smart-cea1ab48-74fe-4576-b7c5-9466aa82575c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286989449 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.2286989449
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2371415322
Short name T347
Test name
Test status
Simulation time 212112344 ps
CPU time 3.93 seconds
Started Jul 19 04:55:01 PM PDT 24
Finished Jul 19 04:55:09 PM PDT 24
Peak memory 213544 kb
Host smart-cae50c49-3408-41ad-84fd-64028a77f3d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371415322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2371415322
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3575040834
Short name T434
Test name
Test status
Simulation time 1397691433 ps
CPU time 9.7 seconds
Started Jul 19 04:54:57 PM PDT 24
Finished Jul 19 04:55:10 PM PDT 24
Peak memory 213644 kb
Host smart-2ec5c08e-91a4-4d7e-8665-230d2eb3cb99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575040834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3575040834
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1778892880
Short name T390
Test name
Test status
Simulation time 1035691146 ps
CPU time 5.61 seconds
Started Jul 19 04:55:00 PM PDT 24
Finished Jul 19 04:55:09 PM PDT 24
Peak memory 221776 kb
Host smart-2f925e63-f41c-4d66-a184-7b9547ee6f09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778892880 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1778892880
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.786006273
Short name T104
Test name
Test status
Simulation time 719842590 ps
CPU time 1.83 seconds
Started Jul 19 04:54:57 PM PDT 24
Finished Jul 19 04:55:03 PM PDT 24
Peak memory 213588 kb
Host smart-94af63e2-5898-44a1-bdc2-ec1090af829f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786006273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.786006273
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2987762771
Short name T391
Test name
Test status
Simulation time 2324279763 ps
CPU time 6.86 seconds
Started Jul 19 04:54:58 PM PDT 24
Finished Jul 19 04:55:08 PM PDT 24
Peak memory 205252 kb
Host smart-6fd7f4e4-5777-444c-b812-525c6537da30
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987762771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2987762771
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4097074126
Short name T386
Test name
Test status
Simulation time 12462099752 ps
CPU time 16.74 seconds
Started Jul 19 04:54:59 PM PDT 24
Finished Jul 19 04:55:20 PM PDT 24
Peak memory 205224 kb
Host smart-52dd6fbe-5751-4960-8284-5db0bfefac6f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097074126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.4
097074126
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3162743543
Short name T313
Test name
Test status
Simulation time 191714605 ps
CPU time 0.8 seconds
Started Jul 19 04:54:58 PM PDT 24
Finished Jul 19 04:55:02 PM PDT 24
Peak memory 204912 kb
Host smart-564b2404-be44-4552-b3ce-c786cff2fd35
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162743543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
162743543
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2392601920
Short name T87
Test name
Test status
Simulation time 245781036 ps
CPU time 6.63 seconds
Started Jul 19 04:55:01 PM PDT 24
Finished Jul 19 04:55:11 PM PDT 24
Peak memory 205304 kb
Host smart-a3ef5402-d9f6-4b41-9499-b50ffc31cb96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392601920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2392601920
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1478667820
Short name T360
Test name
Test status
Simulation time 99632963 ps
CPU time 2.32 seconds
Started Jul 19 04:54:58 PM PDT 24
Finished Jul 19 04:55:04 PM PDT 24
Peak memory 213608 kb
Host smart-164b703d-7318-4a40-92fc-a6f666842921
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478667820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1478667820
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3997339701
Short name T158
Test name
Test status
Simulation time 1668283869 ps
CPU time 16.66 seconds
Started Jul 19 04:54:58 PM PDT 24
Finished Jul 19 04:55:18 PM PDT 24
Peak memory 213552 kb
Host smart-fc25b80e-20b3-437f-b67d-11264c1f21c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997339701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3997339701
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.321531044
Short name T246
Test name
Test status
Simulation time 248205460 ps
CPU time 0.73 seconds
Started Jul 19 04:58:43 PM PDT 24
Finished Jul 19 04:58:45 PM PDT 24
Peak memory 204944 kb
Host smart-91ffcdad-2c2c-4d64-98c0-6a52b5985f77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321531044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.321531044
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3970527653
Short name T204
Test name
Test status
Simulation time 14523695583 ps
CPU time 25.22 seconds
Started Jul 19 04:58:36 PM PDT 24
Finished Jul 19 04:59:03 PM PDT 24
Peak memory 221840 kb
Host smart-26d2c60d-de69-4cb1-aab0-300f624e2364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970527653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3970527653
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2824386439
Short name T24
Test name
Test status
Simulation time 768248524 ps
CPU time 2.61 seconds
Started Jul 19 04:58:36 PM PDT 24
Finished Jul 19 04:58:41 PM PDT 24
Peak memory 205012 kb
Host smart-025ed1a6-bbbf-4b11-a8d5-94293c119919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824386439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2824386439
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.879061870
Short name T276
Test name
Test status
Simulation time 112367201 ps
CPU time 0.9 seconds
Started Jul 19 04:58:35 PM PDT 24
Finished Jul 19 04:58:37 PM PDT 24
Peak memory 204988 kb
Host smart-2088dee3-94ef-4c7a-bcf3-2b7092d64944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879061870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.879061870
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2709512631
Short name T173
Test name
Test status
Simulation time 146896167 ps
CPU time 1.09 seconds
Started Jul 19 04:58:36 PM PDT 24
Finished Jul 19 04:58:39 PM PDT 24
Peak memory 204912 kb
Host smart-9012cd73-fe55-4900-a8fe-e0f66972433f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709512631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2709512631
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2340531511
Short name T248
Test name
Test status
Simulation time 2533485564 ps
CPU time 4.54 seconds
Started Jul 19 04:58:36 PM PDT 24
Finished Jul 19 04:58:42 PM PDT 24
Peak memory 205412 kb
Host smart-9881b6c2-f2bc-4577-9e96-c540df87ce30
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2340531511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2340531511
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2375695655
Short name T7
Test name
Test status
Simulation time 545187217 ps
CPU time 1.01 seconds
Started Jul 19 04:58:33 PM PDT 24
Finished Jul 19 04:58:35 PM PDT 24
Peak memory 204956 kb
Host smart-16b5965c-f9c9-41c7-9736-f7bd835e7760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375695655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2375695655
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2121223025
Short name T227
Test name
Test status
Simulation time 381679779 ps
CPU time 1.22 seconds
Started Jul 19 04:58:36 PM PDT 24
Finished Jul 19 04:58:39 PM PDT 24
Peak memory 204992 kb
Host smart-dde00f15-993b-46c2-b093-467bde60b954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121223025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2121223025
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3211937502
Short name T57
Test name
Test status
Simulation time 609020447 ps
CPU time 2.15 seconds
Started Jul 19 04:58:41 PM PDT 24
Finished Jul 19 04:58:44 PM PDT 24
Peak memory 204964 kb
Host smart-60e518e1-b223-4f17-ab7e-8b85baa2b956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211937502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3211937502
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2431512538
Short name T31
Test name
Test status
Simulation time 329319545 ps
CPU time 1.67 seconds
Started Jul 19 04:58:44 PM PDT 24
Finished Jul 19 04:58:47 PM PDT 24
Peak memory 204892 kb
Host smart-1d548c90-e316-4a9b-b2dd-b890b81173cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431512538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2431512538
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.270783198
Short name T51
Test name
Test status
Simulation time 436705787 ps
CPU time 0.93 seconds
Started Jul 19 04:58:42 PM PDT 24
Finished Jul 19 04:58:43 PM PDT 24
Peak memory 205012 kb
Host smart-1f0ec668-e44b-405f-a27a-b2f09583c04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270783198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.270783198
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.135974519
Short name T171
Test name
Test status
Simulation time 2278941964 ps
CPU time 2.16 seconds
Started Jul 19 04:58:35 PM PDT 24
Finished Jul 19 04:58:38 PM PDT 24
Peak memory 205072 kb
Host smart-11c97619-549e-4523-8a76-e0f67efeed95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135974519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.135974519
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.855384613
Short name T278
Test name
Test status
Simulation time 838329245 ps
CPU time 2.29 seconds
Started Jul 19 04:58:36 PM PDT 24
Finished Jul 19 04:58:39 PM PDT 24
Peak memory 213228 kb
Host smart-10fa4c3e-0a5e-4338-80ab-406d4f73d093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855384613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.855384613
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3849163114
Short name T10
Test name
Test status
Simulation time 77772445 ps
CPU time 0.82 seconds
Started Jul 19 04:58:43 PM PDT 24
Finished Jul 19 04:58:45 PM PDT 24
Peak memory 213248 kb
Host smart-c09de99b-28fe-4ae1-a261-a428e216bc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849163114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3849163114
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1049707681
Short name T55
Test name
Test status
Simulation time 2291650119 ps
CPU time 1.75 seconds
Started Jul 19 04:58:35 PM PDT 24
Finished Jul 19 04:58:38 PM PDT 24
Peak memory 213608 kb
Host smart-b3189ca8-556a-441b-a748-cfe4e1f3ef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049707681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1049707681
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1730554800
Short name T50
Test name
Test status
Simulation time 2460910769 ps
CPU time 8.29 seconds
Started Jul 19 04:58:45 PM PDT 24
Finished Jul 19 04:58:54 PM PDT 24
Peak memory 229364 kb
Host smart-45120825-f84c-4c41-ad97-4aaf276fe229
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730554800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1730554800
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.370187420
Short name T146
Test name
Test status
Simulation time 1741632835 ps
CPU time 3.21 seconds
Started Jul 19 04:58:35 PM PDT 24
Finished Jul 19 04:58:39 PM PDT 24
Peak memory 204940 kb
Host smart-1c0564af-3ad6-4671-b542-329335b573c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370187420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.370187420
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.676006770
Short name T168
Test name
Test status
Simulation time 3840621217 ps
CPU time 10.65 seconds
Started Jul 19 04:58:43 PM PDT 24
Finished Jul 19 04:58:55 PM PDT 24
Peak memory 213448 kb
Host smart-12a7ca1e-f65f-4b15-bf09-38bd993e77ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676006770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.676006770
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.676045668
Short name T74
Test name
Test status
Simulation time 3614189040 ps
CPU time 2.98 seconds
Started Jul 19 04:58:36 PM PDT 24
Finished Jul 19 04:58:40 PM PDT 24
Peak memory 205328 kb
Host smart-e7036f05-22ce-4cb8-adfd-ebc724753a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676045668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.676045668
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.550551544
Short name T5
Test name
Test status
Simulation time 310709296 ps
CPU time 1 seconds
Started Jul 19 04:59:05 PM PDT 24
Finished Jul 19 04:59:07 PM PDT 24
Peak memory 204992 kb
Host smart-65077a6b-3edb-4f89-8d43-35b009895b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550551544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.550551544
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.782870086
Short name T186
Test name
Test status
Simulation time 118004881 ps
CPU time 0.79 seconds
Started Jul 19 04:59:01 PM PDT 24
Finished Jul 19 04:59:03 PM PDT 24
Peak memory 204908 kb
Host smart-69e0b670-ab79-4196-9117-e4d3daf38ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782870086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.782870086
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.4036738001
Short name T194
Test name
Test status
Simulation time 2149961662 ps
CPU time 6.92 seconds
Started Jul 19 04:58:43 PM PDT 24
Finished Jul 19 04:58:52 PM PDT 24
Peak memory 213664 kb
Host smart-c9ecd9a5-b94f-403c-a293-a9b36e0d76a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036738001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.4036738001
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.976400172
Short name T222
Test name
Test status
Simulation time 5885684832 ps
CPU time 15.06 seconds
Started Jul 19 04:58:41 PM PDT 24
Finished Jul 19 04:58:57 PM PDT 24
Peak memory 213684 kb
Host smart-71821eee-2d2f-4ec2-92fa-c8e2f1b36256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976400172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.976400172
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3343146415
Short name T277
Test name
Test status
Simulation time 224752606 ps
CPU time 0.96 seconds
Started Jul 19 04:58:56 PM PDT 24
Finished Jul 19 04:58:59 PM PDT 24
Peak memory 204956 kb
Host smart-014bd158-2eeb-4912-ba4b-0e815a3c335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343146415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3343146415
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2983663411
Short name T23
Test name
Test status
Simulation time 2122125143 ps
CPU time 6.23 seconds
Started Jul 19 04:58:56 PM PDT 24
Finished Jul 19 04:59:04 PM PDT 24
Peak memory 204964 kb
Host smart-801e6427-729f-447c-8003-eb6160516a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983663411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2983663411
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.294600099
Short name T35
Test name
Test status
Simulation time 126511103 ps
CPU time 0.93 seconds
Started Jul 19 04:58:57 PM PDT 24
Finished Jul 19 04:58:59 PM PDT 24
Peak memory 204988 kb
Host smart-a4a2d096-2125-4d87-9916-a77eceef44c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294600099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.294600099
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2361263964
Short name T34
Test name
Test status
Simulation time 257057967 ps
CPU time 1.2 seconds
Started Jul 19 04:58:55 PM PDT 24
Finished Jul 19 04:58:58 PM PDT 24
Peak memory 205012 kb
Host smart-1fd52f4a-5574-4eea-ba07-3f598d3eff5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361263964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2361263964
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1727376354
Short name T124
Test name
Test status
Simulation time 165969653 ps
CPU time 0.89 seconds
Started Jul 19 04:58:55 PM PDT 24
Finished Jul 19 04:58:57 PM PDT 24
Peak memory 204992 kb
Host smart-2755ce10-2758-487e-bc62-5354c3b03817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727376354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1727376354
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.3629101347
Short name T9
Test name
Test status
Simulation time 91424193 ps
CPU time 0.87 seconds
Started Jul 19 04:59:03 PM PDT 24
Finished Jul 19 04:59:06 PM PDT 24
Peak memory 215420 kb
Host smart-92b2991e-bd83-4d28-9cf9-b7534d0f3937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629101347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3629101347
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3122953901
Short name T272
Test name
Test status
Simulation time 9050336718 ps
CPU time 26.64 seconds
Started Jul 19 04:58:41 PM PDT 24
Finished Jul 19 04:59:09 PM PDT 24
Peak memory 213648 kb
Host smart-b2bf70e3-fa60-4e94-b036-e464621fa34c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3122953901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3122953901
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.3535552084
Short name T53
Test name
Test status
Simulation time 151581453 ps
CPU time 0.81 seconds
Started Jul 19 04:59:03 PM PDT 24
Finished Jul 19 04:59:05 PM PDT 24
Peak memory 204984 kb
Host smart-86ac18d0-5a99-4344-ad7f-da76e0464d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535552084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3535552084
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3627610313
Short name T169
Test name
Test status
Simulation time 590580777 ps
CPU time 1.94 seconds
Started Jul 19 04:58:54 PM PDT 24
Finished Jul 19 04:58:57 PM PDT 24
Peak memory 204980 kb
Host smart-31fa1208-831c-4199-a43c-4f5cae05915e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627610313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3627610313
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3631019351
Short name T268
Test name
Test status
Simulation time 92269128 ps
CPU time 0.8 seconds
Started Jul 19 04:58:54 PM PDT 24
Finished Jul 19 04:58:56 PM PDT 24
Peak memory 205156 kb
Host smart-669184bb-594c-44bd-bbf1-74661392ec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631019351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3631019351
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3423870663
Short name T286
Test name
Test status
Simulation time 148108352 ps
CPU time 1.1 seconds
Started Jul 19 04:58:55 PM PDT 24
Finished Jul 19 04:58:57 PM PDT 24
Peak memory 205008 kb
Host smart-86d0b75d-d476-461f-a614-af77002d0d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423870663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3423870663
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1017198708
Short name T249
Test name
Test status
Simulation time 299027729 ps
CPU time 1.45 seconds
Started Jul 19 04:58:54 PM PDT 24
Finished Jul 19 04:58:57 PM PDT 24
Peak memory 204856 kb
Host smart-e14cbf1c-36d0-4064-a87a-2d9def487347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017198708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1017198708
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3403589192
Short name T216
Test name
Test status
Simulation time 715607659 ps
CPU time 2.39 seconds
Started Jul 19 04:58:55 PM PDT 24
Finished Jul 19 04:59:00 PM PDT 24
Peak memory 204988 kb
Host smart-7851ca05-eff6-4906-b2a8-c2ae4ebfcd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403589192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3403589192
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1964965013
Short name T281
Test name
Test status
Simulation time 125339805 ps
CPU time 0.86 seconds
Started Jul 19 04:58:57 PM PDT 24
Finished Jul 19 04:58:59 PM PDT 24
Peak memory 204952 kb
Host smart-915ce6a7-4ab8-46d0-85be-8295f8cc3993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964965013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1964965013
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.357766930
Short name T274
Test name
Test status
Simulation time 483309956 ps
CPU time 1.02 seconds
Started Jul 19 04:58:54 PM PDT 24
Finished Jul 19 04:58:56 PM PDT 24
Peak memory 204888 kb
Host smart-68520f07-8000-4872-b130-1e8bb8c22703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357766930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.357766930
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2430960228
Short name T172
Test name
Test status
Simulation time 2828764674 ps
CPU time 2.42 seconds
Started Jul 19 04:58:55 PM PDT 24
Finished Jul 19 04:59:00 PM PDT 24
Peak memory 205300 kb
Host smart-a7f27bcd-ec1c-4d96-9558-318c69694be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430960228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2430960228
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3440811358
Short name T280
Test name
Test status
Simulation time 152431992 ps
CPU time 1.06 seconds
Started Jul 19 04:58:53 PM PDT 24
Finished Jul 19 04:58:55 PM PDT 24
Peak memory 213168 kb
Host smart-2fcf065f-1564-4289-978c-c3783aacd0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440811358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3440811358
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.2899659097
Short name T22
Test name
Test status
Simulation time 1109440586 ps
CPU time 3.56 seconds
Started Jul 19 04:58:56 PM PDT 24
Finished Jul 19 04:59:01 PM PDT 24
Peak memory 204988 kb
Host smart-8a9e1044-11cb-4a46-87be-0f82632ed615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899659097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2899659097
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2887161511
Short name T42
Test name
Test status
Simulation time 706922367 ps
CPU time 1.2 seconds
Started Jul 19 04:59:03 PM PDT 24
Finished Jul 19 04:59:05 PM PDT 24
Peak memory 205020 kb
Host smart-89c1400c-43a9-49bd-812f-43e0ba6e4ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887161511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2887161511
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3857687571
Short name T72
Test name
Test status
Simulation time 4265714715 ps
CPU time 6.36 seconds
Started Jul 19 04:58:55 PM PDT 24
Finished Jul 19 04:59:03 PM PDT 24
Peak memory 205276 kb
Host smart-1a2d783d-713b-45aa-a398-d93b33422d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857687571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3857687571
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1274052378
Short name T256
Test name
Test status
Simulation time 5042569466 ps
CPU time 7.15 seconds
Started Jul 19 04:58:42 PM PDT 24
Finished Jul 19 04:58:51 PM PDT 24
Peak memory 205512 kb
Host smart-6bbcf28b-90e6-4962-aa75-e7c453bf33d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274052378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1274052378
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3665136942
Short name T219
Test name
Test status
Simulation time 3490645851 ps
CPU time 9.77 seconds
Started Jul 19 04:58:45 PM PDT 24
Finished Jul 19 04:58:56 PM PDT 24
Peak memory 204992 kb
Host smart-b879a0a8-e3c0-4734-85ba-4245c1fa6212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665136942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3665136942
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.1588595468
Short name T136
Test name
Test status
Simulation time 2238697661 ps
CPU time 1.77 seconds
Started Jul 19 04:59:03 PM PDT 24
Finished Jul 19 04:59:06 PM PDT 24
Peak memory 213440 kb
Host smart-f1465100-1da4-4d5c-b92f-6ef7cdaca85f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588595468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1588595468
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1353727633
Short name T192
Test name
Test status
Simulation time 76762441 ps
CPU time 0.83 seconds
Started Jul 19 04:59:26 PM PDT 24
Finished Jul 19 04:59:31 PM PDT 24
Peak memory 204964 kb
Host smart-96fea714-e4ae-4943-a979-dee2137f1eed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353727633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1353727633
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2423095033
Short name T231
Test name
Test status
Simulation time 29318406386 ps
CPU time 88.48 seconds
Started Jul 19 04:59:27 PM PDT 24
Finished Jul 19 05:01:00 PM PDT 24
Peak memory 218980 kb
Host smart-fa2a0d06-5e11-4d28-9603-acc90c093e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423095033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2423095033
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.709576461
Short name T242
Test name
Test status
Simulation time 2991081171 ps
CPU time 3.2 seconds
Started Jul 19 04:59:25 PM PDT 24
Finished Jul 19 04:59:33 PM PDT 24
Peak memory 205400 kb
Host smart-b299db82-f4a6-404d-8798-63479a720543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709576461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.709576461
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3984082838
Short name T197
Test name
Test status
Simulation time 908544110 ps
CPU time 1.65 seconds
Started Jul 19 04:59:29 PM PDT 24
Finished Jul 19 04:59:36 PM PDT 24
Peak memory 205352 kb
Host smart-2945aed2-0d5b-4da9-9c6c-fe24ed2b4996
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3984082838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3984082838
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.342055959
Short name T189
Test name
Test status
Simulation time 7982021672 ps
CPU time 22.47 seconds
Started Jul 19 04:59:27 PM PDT 24
Finished Jul 19 04:59:55 PM PDT 24
Peak memory 213544 kb
Host smart-d08bf3bb-430d-4634-9e05-faca45ec9165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342055959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.342055959
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1242689055
Short name T187
Test name
Test status
Simulation time 44230168 ps
CPU time 0.78 seconds
Started Jul 19 04:59:26 PM PDT 24
Finished Jul 19 04:59:31 PM PDT 24
Peak memory 204996 kb
Host smart-b30633fc-a993-4eda-8ec8-9567bedbab47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242689055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1242689055
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3378779253
Short name T188
Test name
Test status
Simulation time 9571863191 ps
CPU time 6.82 seconds
Started Jul 19 04:59:27 PM PDT 24
Finished Jul 19 04:59:38 PM PDT 24
Peak memory 216160 kb
Host smart-528fa11b-d18a-4aea-9467-887eeca887f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378779253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3378779253
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3300462300
Short name T76
Test name
Test status
Simulation time 2206406401 ps
CPU time 2.79 seconds
Started Jul 19 04:59:28 PM PDT 24
Finished Jul 19 04:59:36 PM PDT 24
Peak memory 205468 kb
Host smart-776180b3-e059-4923-82f8-64ec0566818f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300462300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3300462300
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3662937138
Short name T206
Test name
Test status
Simulation time 2564408310 ps
CPU time 4.6 seconds
Started Jul 19 04:59:26 PM PDT 24
Finished Jul 19 04:59:36 PM PDT 24
Peak memory 205364 kb
Host smart-5cc117d9-872c-46c9-b6e3-442cd260fc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662937138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3662937138
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1471461524
Short name T122
Test name
Test status
Simulation time 38587220 ps
CPU time 0.8 seconds
Started Jul 19 04:59:37 PM PDT 24
Finished Jul 19 04:59:41 PM PDT 24
Peak memory 204916 kb
Host smart-a150f88c-f51b-4591-84c5-aa4e5301030a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471461524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1471461524
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3150761660
Short name T215
Test name
Test status
Simulation time 817421309 ps
CPU time 1.23 seconds
Started Jul 19 04:59:34 PM PDT 24
Finished Jul 19 04:59:39 PM PDT 24
Peak memory 205272 kb
Host smart-23231e26-b546-4619-bc06-75736c3ac3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150761660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3150761660
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3821103641
Short name T39
Test name
Test status
Simulation time 7813945753 ps
CPU time 11.04 seconds
Started Jul 19 04:59:39 PM PDT 24
Finished Jul 19 04:59:52 PM PDT 24
Peak memory 213704 kb
Host smart-0dc79bbd-7b3a-472c-b593-73a9435c38b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821103641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3821103641
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1642920069
Short name T238
Test name
Test status
Simulation time 3264728339 ps
CPU time 6.35 seconds
Started Jul 19 04:59:36 PM PDT 24
Finished Jul 19 04:59:45 PM PDT 24
Peak memory 205388 kb
Host smart-7fe3d54a-df77-4933-9d40-7cd919d24d84
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642920069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1642920069
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.233144355
Short name T234
Test name
Test status
Simulation time 833025573 ps
CPU time 1.96 seconds
Started Jul 19 04:59:29 PM PDT 24
Finished Jul 19 04:59:36 PM PDT 24
Peak memory 205308 kb
Host smart-ec2dca85-f931-493e-bbd4-712a5e3a8b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233144355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.233144355
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1833664796
Short name T203
Test name
Test status
Simulation time 36787954 ps
CPU time 0.75 seconds
Started Jul 19 04:59:39 PM PDT 24
Finished Jul 19 04:59:41 PM PDT 24
Peak memory 204992 kb
Host smart-f4921be2-89aa-4cab-ac5a-d55fa079a405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833664796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1833664796
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2495821192
Short name T139
Test name
Test status
Simulation time 13051343697 ps
CPU time 11.24 seconds
Started Jul 19 04:59:33 PM PDT 24
Finished Jul 19 04:59:48 PM PDT 24
Peak memory 213564 kb
Host smart-dfaae46a-068a-4348-b56e-5de8539c5c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495821192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2495821192
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1642366885
Short name T210
Test name
Test status
Simulation time 5326654133 ps
CPU time 6.04 seconds
Started Jul 19 04:59:35 PM PDT 24
Finished Jul 19 04:59:44 PM PDT 24
Peak memory 213664 kb
Host smart-7f4d8ed1-bfd9-453b-a9eb-97f6bb345b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642366885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1642366885
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1987743088
Short name T228
Test name
Test status
Simulation time 2458672819 ps
CPU time 7.55 seconds
Started Jul 19 04:59:35 PM PDT 24
Finished Jul 19 04:59:45 PM PDT 24
Peak memory 213668 kb
Host smart-7257a1bb-826c-4c58-b053-7cd6dc26916c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1987743088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1987743088
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2387650165
Short name T240
Test name
Test status
Simulation time 1317605003 ps
CPU time 4.48 seconds
Started Jul 19 04:59:35 PM PDT 24
Finished Jul 19 04:59:42 PM PDT 24
Peak memory 205392 kb
Host smart-3127b2a0-adc5-408c-862d-c4d04f014c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387650165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2387650165
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.4071420480
Short name T13
Test name
Test status
Simulation time 3020548501 ps
CPU time 9.34 seconds
Started Jul 19 04:59:37 PM PDT 24
Finished Jul 19 04:59:49 PM PDT 24
Peak memory 205312 kb
Host smart-fb352bd9-b91a-452c-8c2e-c3639d726d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071420480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.4071420480
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2389895577
Short name T218
Test name
Test status
Simulation time 176846720 ps
CPU time 0.91 seconds
Started Jul 19 04:59:35 PM PDT 24
Finished Jul 19 04:59:39 PM PDT 24
Peak memory 204964 kb
Host smart-884e337d-b5df-4201-8813-406a8704d3cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389895577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2389895577
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.650692812
Short name T251
Test name
Test status
Simulation time 9377278324 ps
CPU time 10.99 seconds
Started Jul 19 04:59:37 PM PDT 24
Finished Jul 19 04:59:51 PM PDT 24
Peak memory 213704 kb
Host smart-9cf335d6-ef6a-4dea-bd4b-901d6fa3da5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650692812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.650692812
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4076411385
Short name T211
Test name
Test status
Simulation time 1557044345 ps
CPU time 2.49 seconds
Started Jul 19 04:59:34 PM PDT 24
Finished Jul 19 04:59:40 PM PDT 24
Peak memory 213512 kb
Host smart-3fbe527f-9498-4031-b209-72b1848e4c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076411385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4076411385
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.181974616
Short name T279
Test name
Test status
Simulation time 2737107992 ps
CPU time 3.89 seconds
Started Jul 19 04:59:39 PM PDT 24
Finished Jul 19 04:59:45 PM PDT 24
Peak memory 205384 kb
Host smart-55f61f94-a4d9-4880-8105-dd0660cdfa0e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181974616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.181974616
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1568382547
Short name T220
Test name
Test status
Simulation time 2453282977 ps
CPU time 7.75 seconds
Started Jul 19 04:59:36 PM PDT 24
Finished Jul 19 04:59:47 PM PDT 24
Peak memory 205588 kb
Host smart-c0706b79-4565-4579-8a1c-587a3b50dea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568382547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1568382547
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2584575164
Short name T284
Test name
Test status
Simulation time 110658446 ps
CPU time 0.73 seconds
Started Jul 19 04:59:40 PM PDT 24
Finished Jul 19 04:59:43 PM PDT 24
Peak memory 205000 kb
Host smart-10a62dd2-2260-4715-a108-008beed9f1fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584575164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2584575164
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3709082598
Short name T190
Test name
Test status
Simulation time 9357393900 ps
CPU time 15.79 seconds
Started Jul 19 04:59:35 PM PDT 24
Finished Jul 19 04:59:53 PM PDT 24
Peak memory 205432 kb
Host smart-0210c4d9-a564-4cae-838e-42c257f765c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709082598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3709082598
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3594808396
Short name T257
Test name
Test status
Simulation time 2016348382 ps
CPU time 2.43 seconds
Started Jul 19 04:59:36 PM PDT 24
Finished Jul 19 04:59:42 PM PDT 24
Peak memory 205272 kb
Host smart-163ec66c-e7df-4629-bb1b-f04ce5797efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594808396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3594808396
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.452498105
Short name T270
Test name
Test status
Simulation time 1448022282 ps
CPU time 3.12 seconds
Started Jul 19 04:59:36 PM PDT 24
Finished Jul 19 04:59:42 PM PDT 24
Peak memory 205284 kb
Host smart-acb820b6-614a-42e2-b4c9-5b43c1ef8d44
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=452498105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.452498105
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.4121681051
Short name T132
Test name
Test status
Simulation time 817466005 ps
CPU time 1.79 seconds
Started Jul 19 04:59:34 PM PDT 24
Finished Jul 19 04:59:39 PM PDT 24
Peak memory 205292 kb
Host smart-9977cf55-f399-4851-a664-910c74674df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121681051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.4121681051
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1011587175
Short name T17
Test name
Test status
Simulation time 3344778857 ps
CPU time 3.16 seconds
Started Jul 19 04:59:37 PM PDT 24
Finished Jul 19 04:59:43 PM PDT 24
Peak memory 205228 kb
Host smart-a91de174-845a-4dad-a293-cbd2a83bbf92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011587175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1011587175
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1564121593
Short name T199
Test name
Test status
Simulation time 29682583 ps
CPU time 0.73 seconds
Started Jul 19 04:59:34 PM PDT 24
Finished Jul 19 04:59:38 PM PDT 24
Peak memory 204964 kb
Host smart-e4278fc5-5041-4384-aceb-fda87d086bc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564121593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1564121593
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.4062348405
Short name T209
Test name
Test status
Simulation time 14282200931 ps
CPU time 17.62 seconds
Started Jul 19 04:59:35 PM PDT 24
Finished Jul 19 04:59:56 PM PDT 24
Peak memory 213716 kb
Host smart-db8f1b6e-78c6-4e78-84dc-d03d324913b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062348405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.4062348405
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1663759586
Short name T3
Test name
Test status
Simulation time 1828864365 ps
CPU time 1.56 seconds
Started Jul 19 04:59:35 PM PDT 24
Finished Jul 19 04:59:39 PM PDT 24
Peak memory 205332 kb
Host smart-5e243697-e702-4c86-aba2-f7c81e33a4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663759586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1663759586
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2239591516
Short name T69
Test name
Test status
Simulation time 1471533528 ps
CPU time 3.19 seconds
Started Jul 19 04:59:35 PM PDT 24
Finished Jul 19 04:59:41 PM PDT 24
Peak memory 205316 kb
Host smart-d784cdcb-5776-4be1-bdca-2fb5617a4f9e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2239591516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2239591516
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1097321352
Short name T237
Test name
Test status
Simulation time 2260660074 ps
CPU time 2.75 seconds
Started Jul 19 04:59:35 PM PDT 24
Finished Jul 19 04:59:41 PM PDT 24
Peak memory 205376 kb
Host smart-08885592-1f89-479d-b23f-780479257270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097321352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1097321352
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1879000037
Short name T45
Test name
Test status
Simulation time 182068527 ps
CPU time 0.74 seconds
Started Jul 19 04:59:44 PM PDT 24
Finished Jul 19 04:59:47 PM PDT 24
Peak memory 204984 kb
Host smart-27c948d7-04c2-4dda-98d1-4d7bb94df36b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879000037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1879000037
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1226800200
Short name T262
Test name
Test status
Simulation time 32230143799 ps
CPU time 49.64 seconds
Started Jul 19 04:59:46 PM PDT 24
Finished Jul 19 05:00:37 PM PDT 24
Peak memory 213728 kb
Host smart-81f43aac-4fa4-41a2-b7cb-e0825947a49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226800200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1226800200
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.507262406
Short name T141
Test name
Test status
Simulation time 3838596250 ps
CPU time 6.23 seconds
Started Jul 19 04:59:44 PM PDT 24
Finished Jul 19 04:59:52 PM PDT 24
Peak memory 205404 kb
Host smart-69f64e27-5d7d-49ed-9ab3-3d5e4692d21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507262406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.507262406
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.227219547
Short name T252
Test name
Test status
Simulation time 2907942793 ps
CPU time 4.82 seconds
Started Jul 19 04:59:45 PM PDT 24
Finished Jul 19 04:59:51 PM PDT 24
Peak memory 205432 kb
Host smart-9c49e567-4dcd-433f-94ab-246877ec3e4c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227219547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.227219547
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.622938924
Short name T265
Test name
Test status
Simulation time 3015815528 ps
CPU time 3.2 seconds
Started Jul 19 04:59:45 PM PDT 24
Finished Jul 19 04:59:50 PM PDT 24
Peak memory 205476 kb
Host smart-84d49538-2abf-4541-af4d-a233e572c293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622938924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.622938924
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.219305361
Short name T18
Test name
Test status
Simulation time 6735942063 ps
CPU time 20.9 seconds
Started Jul 19 04:59:47 PM PDT 24
Finished Jul 19 05:00:08 PM PDT 24
Peak memory 213492 kb
Host smart-f780e018-a8bf-499a-a583-0867ccebcfc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219305361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.219305361
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.4154142319
Short name T239
Test name
Test status
Simulation time 81699502 ps
CPU time 0.92 seconds
Started Jul 19 04:59:44 PM PDT 24
Finished Jul 19 04:59:47 PM PDT 24
Peak memory 205004 kb
Host smart-5fc150bf-36eb-49a6-b8f9-dcbef1ad15d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154142319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.4154142319
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3211510347
Short name T67
Test name
Test status
Simulation time 6187548581 ps
CPU time 18.08 seconds
Started Jul 19 04:59:44 PM PDT 24
Finished Jul 19 05:00:03 PM PDT 24
Peak memory 213752 kb
Host smart-c253da5f-4a23-4966-9f0e-8f6b867121bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211510347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3211510347
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1003978947
Short name T273
Test name
Test status
Simulation time 1863333557 ps
CPU time 3.69 seconds
Started Jul 19 04:59:44 PM PDT 24
Finished Jul 19 04:59:49 PM PDT 24
Peak memory 213516 kb
Host smart-a746ffc7-7330-438e-bf27-b416b9fe7070
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003978947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1003978947
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3316488008
Short name T149
Test name
Test status
Simulation time 765773423 ps
CPU time 1.67 seconds
Started Jul 19 04:59:45 PM PDT 24
Finished Jul 19 04:59:49 PM PDT 24
Peak memory 205336 kb
Host smart-1aea6ebc-0506-420c-99aa-c059d78588a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316488008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3316488008
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3211768835
Short name T254
Test name
Test status
Simulation time 103750116 ps
CPU time 0.8 seconds
Started Jul 19 04:59:43 PM PDT 24
Finished Jul 19 04:59:44 PM PDT 24
Peak memory 204984 kb
Host smart-fb30f17d-1e7b-4516-9de1-4a1da27f1c3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211768835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3211768835
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3108968826
Short name T224
Test name
Test status
Simulation time 4301086156 ps
CPU time 5.32 seconds
Started Jul 19 04:59:44 PM PDT 24
Finished Jul 19 04:59:51 PM PDT 24
Peak memory 213660 kb
Host smart-77ec0890-de54-44c0-9e09-be6fade66c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108968826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3108968826
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.375273995
Short name T134
Test name
Test status
Simulation time 4969151467 ps
CPU time 14.32 seconds
Started Jul 19 04:59:45 PM PDT 24
Finished Jul 19 05:00:01 PM PDT 24
Peak memory 213768 kb
Host smart-f10e80cf-c7e7-4627-a841-25c4d365930a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375273995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.375273995
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.783660796
Short name T148
Test name
Test status
Simulation time 959957333 ps
CPU time 1.23 seconds
Started Jul 19 04:59:44 PM PDT 24
Finished Jul 19 04:59:48 PM PDT 24
Peak memory 213456 kb
Host smart-a653c062-544d-4780-a4df-b33834e6148c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=783660796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.783660796
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.1042116291
Short name T243
Test name
Test status
Simulation time 4004055800 ps
CPU time 4.31 seconds
Started Jul 19 04:59:44 PM PDT 24
Finished Jul 19 04:59:50 PM PDT 24
Peak memory 213620 kb
Host smart-356bf046-dd80-438c-ae74-8651802a7590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042116291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1042116291
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.1285506980
Short name T19
Test name
Test status
Simulation time 1242889638 ps
CPU time 2.72 seconds
Started Jul 19 04:59:44 PM PDT 24
Finished Jul 19 04:59:49 PM PDT 24
Peak memory 205188 kb
Host smart-7ba1d112-bfab-49ba-af2a-f57a567c987e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285506980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1285506980
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2968414803
Short name T177
Test name
Test status
Simulation time 45382652 ps
CPU time 0.77 seconds
Started Jul 19 04:59:02 PM PDT 24
Finished Jul 19 04:59:04 PM PDT 24
Peak memory 204980 kb
Host smart-4bb93a90-4434-4706-aa22-44a582fd7202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968414803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2968414803
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3864552928
Short name T258
Test name
Test status
Simulation time 27333221301 ps
CPU time 15.25 seconds
Started Jul 19 04:59:04 PM PDT 24
Finished Jul 19 04:59:20 PM PDT 24
Peak memory 213720 kb
Host smart-6e0838a5-1b9a-4a89-9d05-fb8060e31c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864552928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3864552928
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.433084982
Short name T230
Test name
Test status
Simulation time 7597088824 ps
CPU time 11.86 seconds
Started Jul 19 04:59:05 PM PDT 24
Finished Jul 19 04:59:18 PM PDT 24
Peak memory 213616 kb
Host smart-e64f97a7-95a3-4cef-a35b-3c01ca7ef306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433084982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.433084982
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2106207562
Short name T250
Test name
Test status
Simulation time 12650869208 ps
CPU time 19.18 seconds
Started Jul 19 04:59:03 PM PDT 24
Finished Jul 19 04:59:24 PM PDT 24
Peak memory 213608 kb
Host smart-31b60bbb-1b2a-46d6-ad41-1aa9fb761dd2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2106207562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2106207562
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.637783133
Short name T221
Test name
Test status
Simulation time 245545018 ps
CPU time 1.04 seconds
Started Jul 19 04:59:01 PM PDT 24
Finished Jul 19 04:59:03 PM PDT 24
Peak memory 204984 kb
Host smart-b63348e1-5796-4366-a209-f08f5615821f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637783133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.637783133
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3241593219
Short name T267
Test name
Test status
Simulation time 617947189 ps
CPU time 1.73 seconds
Started Jul 19 04:59:04 PM PDT 24
Finished Jul 19 04:59:07 PM PDT 24
Peak memory 205124 kb
Host smart-b88fc9f6-abfe-4473-8789-d7dfc0195799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241593219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3241593219
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.962559657
Short name T49
Test name
Test status
Simulation time 760022104 ps
CPU time 1.98 seconds
Started Jul 19 04:59:02 PM PDT 24
Finished Jul 19 04:59:04 PM PDT 24
Peak memory 229472 kb
Host smart-a101ddc6-610f-4ebc-87b5-1d9613b694e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962559657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.962559657
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.3691262615
Short name T11
Test name
Test status
Simulation time 7132790933 ps
CPU time 21.19 seconds
Started Jul 19 04:59:03 PM PDT 24
Finished Jul 19 04:59:26 PM PDT 24
Peak memory 205316 kb
Host smart-e706e96a-f85b-4e88-ab1b-8387f79feb5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691262615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3691262615
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3332160809
Short name T2
Test name
Test status
Simulation time 43159915 ps
CPU time 0.74 seconds
Started Jul 19 04:59:46 PM PDT 24
Finished Jul 19 04:59:48 PM PDT 24
Peak memory 204992 kb
Host smart-54f8cdf3-9441-412a-bd6a-d42ee9b7488b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332160809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3332160809
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2112768453
Short name T179
Test name
Test status
Simulation time 38992684 ps
CPU time 0.77 seconds
Started Jul 19 04:59:53 PM PDT 24
Finished Jul 19 04:59:55 PM PDT 24
Peak memory 204912 kb
Host smart-0f11156b-778b-4621-bd8a-1a78d7ebac8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112768453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2112768453
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1692746728
Short name T225
Test name
Test status
Simulation time 40386485 ps
CPU time 0.78 seconds
Started Jul 19 04:59:52 PM PDT 24
Finished Jul 19 04:59:54 PM PDT 24
Peak memory 204992 kb
Host smart-4b2c6f1d-98c0-4dfc-bd37-7a3cde9c6c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692746728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1692746728
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2879166356
Short name T232
Test name
Test status
Simulation time 106742869 ps
CPU time 0.74 seconds
Started Jul 19 04:59:53 PM PDT 24
Finished Jul 19 04:59:56 PM PDT 24
Peak memory 204964 kb
Host smart-4d32972b-7a5b-451b-8204-b6955c6e4ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879166356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2879166356
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.1737985085
Short name T135
Test name
Test status
Simulation time 5386255998 ps
CPU time 8.95 seconds
Started Jul 19 04:59:51 PM PDT 24
Finished Jul 19 05:00:01 PM PDT 24
Peak memory 213516 kb
Host smart-d9721c1a-9f29-484a-b8d9-12b604cbf519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737985085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1737985085
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2272106738
Short name T208
Test name
Test status
Simulation time 50063249 ps
CPU time 0.75 seconds
Started Jul 19 04:59:53 PM PDT 24
Finished Jul 19 04:59:55 PM PDT 24
Peak memory 204984 kb
Host smart-bdaefed6-ebdb-42a3-bb7a-c7d2d048626d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272106738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2272106738
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.4101060073
Short name T235
Test name
Test status
Simulation time 88196602 ps
CPU time 0.72 seconds
Started Jul 19 04:59:52 PM PDT 24
Finished Jul 19 04:59:54 PM PDT 24
Peak memory 204936 kb
Host smart-433363e7-8d4b-4dbc-af3e-5b47b31bb129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101060073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.4101060073
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1407046882
Short name T271
Test name
Test status
Simulation time 73758202 ps
CPU time 0.76 seconds
Started Jul 19 04:59:51 PM PDT 24
Finished Jul 19 04:59:52 PM PDT 24
Peak memory 205016 kb
Host smart-188f004b-d0b1-4fad-b7f1-21121619f57a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407046882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1407046882
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.325033926
Short name T27
Test name
Test status
Simulation time 5937255851 ps
CPU time 10.44 seconds
Started Jul 19 04:59:54 PM PDT 24
Finished Jul 19 05:00:07 PM PDT 24
Peak memory 213508 kb
Host smart-b0a0640c-1087-49b4-aa56-9abb601ac0da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325033926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.325033926
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3675958276
Short name T223
Test name
Test status
Simulation time 56362184 ps
CPU time 0.71 seconds
Started Jul 19 04:59:55 PM PDT 24
Finished Jul 19 04:59:58 PM PDT 24
Peak memory 204992 kb
Host smart-f5237f0d-3d03-431f-8a15-9d058b80110d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675958276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3675958276
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.3516688297
Short name T8
Test name
Test status
Simulation time 8334671014 ps
CPU time 23.73 seconds
Started Jul 19 04:59:53 PM PDT 24
Finished Jul 19 05:00:18 PM PDT 24
Peak memory 213448 kb
Host smart-010249dd-8eb5-44bd-a2e0-b8ab81642f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516688297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3516688297
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1252138111
Short name T244
Test name
Test status
Simulation time 110209844 ps
CPU time 0.93 seconds
Started Jul 19 04:59:53 PM PDT 24
Finished Jul 19 04:59:56 PM PDT 24
Peak memory 204972 kb
Host smart-978bd099-913c-47d4-b938-4878410688fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252138111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1252138111
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1776148492
Short name T15
Test name
Test status
Simulation time 3930971330 ps
CPU time 11.56 seconds
Started Jul 19 04:59:52 PM PDT 24
Finished Jul 19 05:00:05 PM PDT 24
Peak memory 205120 kb
Host smart-8584be9a-e02b-44a4-95a3-eb1b4d40a509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776148492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1776148492
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.385456663
Short name T71
Test name
Test status
Simulation time 47249206 ps
CPU time 0.77 seconds
Started Jul 19 04:59:52 PM PDT 24
Finished Jul 19 04:59:55 PM PDT 24
Peak memory 204960 kb
Host smart-90c2ef52-bdab-4769-a245-f823142b7fcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385456663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.385456663
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.741652480
Short name T167
Test name
Test status
Simulation time 11417855093 ps
CPU time 8.9 seconds
Started Jul 19 04:59:52 PM PDT 24
Finished Jul 19 05:00:02 PM PDT 24
Peak memory 213580 kb
Host smart-5d7b914f-be9e-4a0f-b3bb-d26c6dcadf41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741652480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.741652480
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.936208925
Short name T184
Test name
Test status
Simulation time 118519108 ps
CPU time 0.79 seconds
Started Jul 19 04:59:11 PM PDT 24
Finished Jul 19 04:59:13 PM PDT 24
Peak memory 204964 kb
Host smart-e01cbfbc-d235-4d32-8d19-ad8ab0d18462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936208925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.936208925
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3726550367
Short name T144
Test name
Test status
Simulation time 79620762536 ps
CPU time 123.8 seconds
Started Jul 19 04:59:13 PM PDT 24
Finished Jul 19 05:01:18 PM PDT 24
Peak memory 216088 kb
Host smart-2825f81d-75f0-468c-a621-c257ca707ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726550367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3726550367
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2098936859
Short name T178
Test name
Test status
Simulation time 11134047883 ps
CPU time 31.18 seconds
Started Jul 19 04:59:10 PM PDT 24
Finished Jul 19 04:59:43 PM PDT 24
Peak memory 213656 kb
Host smart-6f1ada96-5390-449b-8834-5642b2101c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098936859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2098936859
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1065701470
Short name T205
Test name
Test status
Simulation time 6789634798 ps
CPU time 18.72 seconds
Started Jul 19 04:59:12 PM PDT 24
Finished Jul 19 04:59:32 PM PDT 24
Peak memory 205528 kb
Host smart-d967058b-6406-4f1e-addb-1e8e17442bb0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1065701470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1065701470
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.270724828
Short name T32
Test name
Test status
Simulation time 234213510 ps
CPU time 0.8 seconds
Started Jul 19 04:59:12 PM PDT 24
Finished Jul 19 04:59:14 PM PDT 24
Peak memory 204980 kb
Host smart-ac7b6c50-1bb0-44fd-830a-fb4ddbd7fd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270724828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.270724828
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2079231183
Short name T142
Test name
Test status
Simulation time 3857118318 ps
CPU time 11.61 seconds
Started Jul 19 04:59:02 PM PDT 24
Finished Jul 19 04:59:15 PM PDT 24
Peak memory 205268 kb
Host smart-b98620e9-7695-435d-99ce-7da78b683ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079231183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2079231183
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1126546187
Short name T65
Test name
Test status
Simulation time 490434598 ps
CPU time 2.3 seconds
Started Jul 19 04:59:13 PM PDT 24
Finished Jul 19 04:59:16 PM PDT 24
Peak memory 229692 kb
Host smart-a462caf0-7315-4f3a-aec9-cdadb7f4fcd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126546187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1126546187
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.2183388903
Short name T25
Test name
Test status
Simulation time 10552010466 ps
CPU time 31.08 seconds
Started Jul 19 04:59:11 PM PDT 24
Finished Jul 19 04:59:44 PM PDT 24
Peak memory 205228 kb
Host smart-609b1102-a8e7-4d63-94dd-07c08b0f52fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183388903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2183388903
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2500102133
Short name T68
Test name
Test status
Simulation time 46626087 ps
CPU time 0.8 seconds
Started Jul 19 04:59:54 PM PDT 24
Finished Jul 19 04:59:57 PM PDT 24
Peak memory 205016 kb
Host smart-53818d82-b4f8-49e9-8358-ee79d8e142d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500102133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2500102133
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2786532806
Short name T236
Test name
Test status
Simulation time 124290026 ps
CPU time 0.84 seconds
Started Jul 19 04:59:55 PM PDT 24
Finished Jul 19 04:59:58 PM PDT 24
Peak memory 204992 kb
Host smart-7d63c41b-5336-4018-93d9-80936ee9f10c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786532806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2786532806
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1236777321
Short name T130
Test name
Test status
Simulation time 1681165478 ps
CPU time 3.58 seconds
Started Jul 19 04:59:52 PM PDT 24
Finished Jul 19 04:59:56 PM PDT 24
Peak memory 213348 kb
Host smart-5a03daa1-9fb8-4c61-a0c3-50510d94cb72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236777321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1236777321
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1682102855
Short name T260
Test name
Test status
Simulation time 100879377 ps
CPU time 0.88 seconds
Started Jul 19 04:59:52 PM PDT 24
Finished Jul 19 04:59:55 PM PDT 24
Peak memory 205000 kb
Host smart-96a1ada0-15f6-4c6f-96f3-c20f34ec6e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682102855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1682102855
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.2409132452
Short name T164
Test name
Test status
Simulation time 4355982909 ps
CPU time 8.41 seconds
Started Jul 19 04:59:54 PM PDT 24
Finished Jul 19 05:00:05 PM PDT 24
Peak memory 205300 kb
Host smart-1d99ad8e-d4c9-40c6-a720-aa55f40c0d48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409132452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.2409132452
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3642677162
Short name T183
Test name
Test status
Simulation time 49317952 ps
CPU time 0.77 seconds
Started Jul 19 04:59:54 PM PDT 24
Finished Jul 19 04:59:58 PM PDT 24
Peak memory 204892 kb
Host smart-be33efc4-ab1d-4089-938a-2f4fafeab1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642677162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3642677162
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1803666881
Short name T70
Test name
Test status
Simulation time 78917155 ps
CPU time 0.74 seconds
Started Jul 19 04:59:52 PM PDT 24
Finished Jul 19 04:59:54 PM PDT 24
Peak memory 204936 kb
Host smart-70c8d415-5a0f-4dc0-97f8-62db7caca70d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803666881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1803666881
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3256429047
Short name T191
Test name
Test status
Simulation time 181331159 ps
CPU time 0.83 seconds
Started Jul 19 04:59:52 PM PDT 24
Finished Jul 19 04:59:55 PM PDT 24
Peak memory 204996 kb
Host smart-fec51ded-5500-44ab-b77d-97c174c287aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256429047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3256429047
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2291832581
Short name T207
Test name
Test status
Simulation time 7845693854 ps
CPU time 20.54 seconds
Started Jul 19 04:59:53 PM PDT 24
Finished Jul 19 05:00:16 PM PDT 24
Peak memory 214604 kb
Host smart-0690f36f-bfd8-428f-b363-f1a1754d8dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291832581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2291832581
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.823594061
Short name T202
Test name
Test status
Simulation time 66927067 ps
CPU time 0.75 seconds
Started Jul 19 05:00:04 PM PDT 24
Finished Jul 19 05:00:07 PM PDT 24
Peak memory 204952 kb
Host smart-f6fc7551-926c-4251-8a2c-5a556cb6fd79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823594061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.823594061
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2710970023
Short name T175
Test name
Test status
Simulation time 53251595 ps
CPU time 0.83 seconds
Started Jul 19 05:00:00 PM PDT 24
Finished Jul 19 05:00:05 PM PDT 24
Peak memory 204964 kb
Host smart-c8b83736-537c-49ca-af55-fbb2be3e0af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710970023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2710970023
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.2962498236
Short name T138
Test name
Test status
Simulation time 6324267020 ps
CPU time 8.22 seconds
Started Jul 19 04:59:59 PM PDT 24
Finished Jul 19 05:00:13 PM PDT 24
Peak memory 213552 kb
Host smart-58e8e10f-a290-4ee4-99b0-1315fa49bc58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962498236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2962498236
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2193228971
Short name T200
Test name
Test status
Simulation time 121656276 ps
CPU time 0.89 seconds
Started Jul 19 05:00:01 PM PDT 24
Finished Jul 19 05:00:06 PM PDT 24
Peak memory 204880 kb
Host smart-462d3c5c-0a8a-4b92-9f00-beb35f876948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193228971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2193228971
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2749485476
Short name T269
Test name
Test status
Simulation time 136103411 ps
CPU time 0.88 seconds
Started Jul 19 05:00:00 PM PDT 24
Finished Jul 19 05:00:06 PM PDT 24
Peak memory 204972 kb
Host smart-84eaa11e-b7c7-4f74-8532-61d2f1a2b5a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749485476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2749485476
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.1299257872
Short name T145
Test name
Test status
Simulation time 3766486778 ps
CPU time 3.44 seconds
Started Jul 19 05:00:01 PM PDT 24
Finished Jul 19 05:00:08 PM PDT 24
Peak memory 205264 kb
Host smart-99cd832b-007c-4e00-86ac-7d1b02b1e322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299257872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1299257872
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3310677853
Short name T226
Test name
Test status
Simulation time 111056246 ps
CPU time 0.75 seconds
Started Jul 19 04:59:21 PM PDT 24
Finished Jul 19 04:59:26 PM PDT 24
Peak memory 204948 kb
Host smart-28c28313-1ac7-4e35-aac5-69f9cf65e4fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310677853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3310677853
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3764023411
Short name T174
Test name
Test status
Simulation time 57656973547 ps
CPU time 175.06 seconds
Started Jul 19 04:59:20 PM PDT 24
Finished Jul 19 05:02:19 PM PDT 24
Peak memory 214616 kb
Host smart-65910c48-94c3-428e-86db-5e1a2eb9d33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764023411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3764023411
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3330025653
Short name T201
Test name
Test status
Simulation time 2103252962 ps
CPU time 6.7 seconds
Started Jul 19 04:59:21 PM PDT 24
Finished Jul 19 04:59:32 PM PDT 24
Peak memory 205436 kb
Host smart-2be2abd0-67b2-4c55-8067-b57f7c2fdefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330025653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3330025653
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.4137421704
Short name T82
Test name
Test status
Simulation time 1067030026 ps
CPU time 1.25 seconds
Started Jul 19 04:59:20 PM PDT 24
Finished Jul 19 04:59:26 PM PDT 24
Peak memory 205276 kb
Host smart-349e1d9b-3e92-415c-8013-f33449869eca
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137421704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.4137421704
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.4273441075
Short name T282
Test name
Test status
Simulation time 403889064 ps
CPU time 1.85 seconds
Started Jul 19 04:59:19 PM PDT 24
Finished Jul 19 04:59:26 PM PDT 24
Peak memory 204984 kb
Host smart-d14ed420-04e6-4569-ac13-ae3297e8f6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273441075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.4273441075
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2713043063
Short name T255
Test name
Test status
Simulation time 1439800612 ps
CPU time 2.02 seconds
Started Jul 19 04:59:19 PM PDT 24
Finished Jul 19 04:59:24 PM PDT 24
Peak memory 205332 kb
Host smart-48931f1c-97c6-4c10-a319-ebc78ceb7ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713043063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2713043063
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1624067840
Short name T48
Test name
Test status
Simulation time 1136348930 ps
CPU time 1.88 seconds
Started Jul 19 04:59:21 PM PDT 24
Finished Jul 19 04:59:27 PM PDT 24
Peak memory 229592 kb
Host smart-14b07255-bbce-4eae-8fc0-54171749a529
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624067840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1624067840
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.1942370496
Short name T163
Test name
Test status
Simulation time 11295652635 ps
CPU time 16.18 seconds
Started Jul 19 04:59:18 PM PDT 24
Finished Jul 19 04:59:37 PM PDT 24
Peak memory 213440 kb
Host smart-b8f4afdd-8027-426e-8383-835030f6eaa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942370496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1942370496
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2229467537
Short name T264
Test name
Test status
Simulation time 38656783 ps
CPU time 0.77 seconds
Started Jul 19 05:00:00 PM PDT 24
Finished Jul 19 05:00:05 PM PDT 24
Peak memory 204980 kb
Host smart-55b655e6-d551-4606-880a-f02f03bb1168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229467537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2229467537
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.1573388376
Short name T133
Test name
Test status
Simulation time 9601113337 ps
CPU time 16.27 seconds
Started Jul 19 04:59:59 PM PDT 24
Finished Jul 19 05:00:21 PM PDT 24
Peak memory 213676 kb
Host smart-217fadc7-40ba-46ac-a1f0-8a33d02a40b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573388376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1573388376
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1123185357
Short name T185
Test name
Test status
Simulation time 116949778 ps
CPU time 0.95 seconds
Started Jul 19 05:00:00 PM PDT 24
Finished Jul 19 05:00:06 PM PDT 24
Peak memory 204936 kb
Host smart-3cf79226-f753-42da-a57d-2c4e78347612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123185357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1123185357
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.339464841
Short name T233
Test name
Test status
Simulation time 88387718 ps
CPU time 0.82 seconds
Started Jul 19 04:59:59 PM PDT 24
Finished Jul 19 05:00:05 PM PDT 24
Peak memory 204996 kb
Host smart-ab190200-2b12-403d-bc04-b7dbc6166971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339464841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.339464841
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.1332798041
Short name T170
Test name
Test status
Simulation time 6975435993 ps
CPU time 9.79 seconds
Started Jul 19 04:59:57 PM PDT 24
Finished Jul 19 05:00:12 PM PDT 24
Peak memory 213504 kb
Host smart-ea5ba925-a352-45f7-9bac-c0e0ed6e088e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332798041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1332798041
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.2570030519
Short name T14
Test name
Test status
Simulation time 2311321915 ps
CPU time 2.9 seconds
Started Jul 19 05:00:00 PM PDT 24
Finished Jul 19 05:00:08 PM PDT 24
Peak memory 205264 kb
Host smart-ffdb2f09-99aa-40ce-bc3d-8a65aadb339c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570030519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2570030519
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2833981229
Short name T259
Test name
Test status
Simulation time 54763508 ps
CPU time 0.7 seconds
Started Jul 19 05:00:09 PM PDT 24
Finished Jul 19 05:00:13 PM PDT 24
Peak memory 204940 kb
Host smart-d8c23329-ec17-4fea-b78c-21382103077f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833981229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2833981229
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.417848857
Short name T193
Test name
Test status
Simulation time 66176227 ps
CPU time 0.71 seconds
Started Jul 19 05:00:07 PM PDT 24
Finished Jul 19 05:00:10 PM PDT 24
Peak memory 204972 kb
Host smart-c2cc25bb-0bc4-451d-81d3-6c96885622d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417848857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.417848857
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.4061601775
Short name T47
Test name
Test status
Simulation time 130004845 ps
CPU time 0.8 seconds
Started Jul 19 05:00:09 PM PDT 24
Finished Jul 19 05:00:13 PM PDT 24
Peak memory 204992 kb
Host smart-dcb2ce4e-22de-45c5-89a8-72fdb23370e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061601775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.4061601775
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2942737803
Short name T247
Test name
Test status
Simulation time 66481444 ps
CPU time 0.81 seconds
Started Jul 19 05:00:08 PM PDT 24
Finished Jul 19 05:00:11 PM PDT 24
Peak memory 204976 kb
Host smart-4981f544-1f8b-4c6c-a365-fbc9e7536142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942737803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2942737803
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.2774248098
Short name T166
Test name
Test status
Simulation time 5723889035 ps
CPU time 2.38 seconds
Started Jul 19 05:00:10 PM PDT 24
Finished Jul 19 05:00:15 PM PDT 24
Peak memory 213512 kb
Host smart-950588b3-df20-4b06-8c34-ebc0fae764f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774248098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2774248098
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.924884508
Short name T195
Test name
Test status
Simulation time 49590030 ps
CPU time 0.81 seconds
Started Jul 19 05:00:08 PM PDT 24
Finished Jul 19 05:00:11 PM PDT 24
Peak memory 205164 kb
Host smart-139ef25f-98ec-40bf-9746-66ca5bc9e1a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924884508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.924884508
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.4117241175
Short name T165
Test name
Test status
Simulation time 9864125532 ps
CPU time 28.13 seconds
Started Jul 19 05:00:16 PM PDT 24
Finished Jul 19 05:00:46 PM PDT 24
Peak memory 213524 kb
Host smart-ed027684-7575-4660-8b1b-ddc63a1938c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117241175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.4117241175
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1817738539
Short name T241
Test name
Test status
Simulation time 114786046 ps
CPU time 0.72 seconds
Started Jul 19 05:00:08 PM PDT 24
Finished Jul 19 05:00:12 PM PDT 24
Peak memory 204940 kb
Host smart-6842c4de-dc75-4617-8c95-07d4aed3997b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817738539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1817738539
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3849231028
Short name T214
Test name
Test status
Simulation time 49120714 ps
CPU time 0.71 seconds
Started Jul 19 04:59:19 PM PDT 24
Finished Jul 19 04:59:23 PM PDT 24
Peak memory 205016 kb
Host smart-e736bc68-447a-4d38-8190-559632ff1974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849231028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3849231028
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2201201137
Short name T54
Test name
Test status
Simulation time 1528117993 ps
CPU time 3 seconds
Started Jul 19 04:59:18 PM PDT 24
Finished Jul 19 04:59:24 PM PDT 24
Peak memory 213528 kb
Host smart-3e10b309-8ad5-4c20-9d66-20cf60a4141a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201201137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2201201137
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3853484499
Short name T16
Test name
Test status
Simulation time 10184828611 ps
CPU time 11.09 seconds
Started Jul 19 04:59:20 PM PDT 24
Finished Jul 19 04:59:35 PM PDT 24
Peak memory 213664 kb
Host smart-e15ec333-9c4a-43ed-8704-c9076c13e113
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3853484499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3853484499
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1061872182
Short name T263
Test name
Test status
Simulation time 2921912666 ps
CPU time 2.8 seconds
Started Jul 19 04:59:19 PM PDT 24
Finished Jul 19 04:59:27 PM PDT 24
Peak memory 213592 kb
Host smart-a3689f7f-5309-40e3-9490-f79f0f5312b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061872182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1061872182
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.2019537969
Short name T36
Test name
Test status
Simulation time 5784294534 ps
CPU time 12.41 seconds
Started Jul 19 04:59:23 PM PDT 24
Finished Jul 19 04:59:40 PM PDT 24
Peak memory 213592 kb
Host smart-bb437953-e5a7-4532-b949-e89e8146fb89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019537969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2019537969
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.776952559
Short name T182
Test name
Test status
Simulation time 151586510 ps
CPU time 1.07 seconds
Started Jul 19 04:59:22 PM PDT 24
Finished Jul 19 04:59:28 PM PDT 24
Peak memory 205016 kb
Host smart-c10aacc7-7e05-42cb-b062-4ecd6b6592f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776952559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.776952559
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3586918550
Short name T198
Test name
Test status
Simulation time 11578902101 ps
CPU time 16.99 seconds
Started Jul 19 04:59:19 PM PDT 24
Finished Jul 19 04:59:41 PM PDT 24
Peak memory 213772 kb
Host smart-4d037211-19bc-4360-ac56-7b63689d8ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586918550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3586918550
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1816159144
Short name T137
Test name
Test status
Simulation time 13522266199 ps
CPU time 21.43 seconds
Started Jul 19 04:59:21 PM PDT 24
Finished Jul 19 04:59:47 PM PDT 24
Peak memory 213592 kb
Host smart-36b96514-727b-44b2-b04b-ccb8702f071f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816159144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1816159144
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2740225241
Short name T140
Test name
Test status
Simulation time 1073267784 ps
CPU time 2.93 seconds
Started Jul 19 04:59:18 PM PDT 24
Finished Jul 19 04:59:24 PM PDT 24
Peak memory 205360 kb
Host smart-eb632e14-ca58-46db-8241-4f04f61e6e16
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740225241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2740225241
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3739654378
Short name T213
Test name
Test status
Simulation time 2261130775 ps
CPU time 2.93 seconds
Started Jul 19 04:59:18 PM PDT 24
Finished Jul 19 04:59:23 PM PDT 24
Peak memory 213580 kb
Host smart-dbcc9c88-8cdb-493b-8766-ab608388d43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739654378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3739654378
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1656923022
Short name T181
Test name
Test status
Simulation time 27849790 ps
CPU time 0.77 seconds
Started Jul 19 04:59:29 PM PDT 24
Finished Jul 19 04:59:35 PM PDT 24
Peak memory 204980 kb
Host smart-9d2e1a89-9596-44a1-ad6f-33f7cf40e075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656923022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1656923022
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1102372146
Short name T212
Test name
Test status
Simulation time 37446261669 ps
CPU time 64.42 seconds
Started Jul 19 04:59:23 PM PDT 24
Finished Jul 19 05:00:32 PM PDT 24
Peak memory 213660 kb
Host smart-1cafed30-7cdb-4b92-b318-15cb2ec6c917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102372146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1102372146
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3083947861
Short name T285
Test name
Test status
Simulation time 1435965802 ps
CPU time 4.79 seconds
Started Jul 19 04:59:21 PM PDT 24
Finished Jul 19 04:59:31 PM PDT 24
Peak memory 205336 kb
Host smart-ca463931-afa6-4a0f-a845-29fa2f03223a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083947861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3083947861
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3984071897
Short name T253
Test name
Test status
Simulation time 2122695978 ps
CPU time 3.68 seconds
Started Jul 19 04:59:21 PM PDT 24
Finished Jul 19 04:59:29 PM PDT 24
Peak memory 213496 kb
Host smart-bdf8d8d2-2013-4ca5-bd67-f7c34d5fc0a6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3984071897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3984071897
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.4143173684
Short name T266
Test name
Test status
Simulation time 2827478052 ps
CPU time 4.9 seconds
Started Jul 19 04:59:20 PM PDT 24
Finished Jul 19 04:59:30 PM PDT 24
Peak memory 213648 kb
Host smart-2b5f6173-a160-4398-be44-4e3af6171045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143173684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.4143173684
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.604813427
Short name T143
Test name
Test status
Simulation time 4397332433 ps
CPU time 6.3 seconds
Started Jul 19 04:59:27 PM PDT 24
Finished Jul 19 04:59:38 PM PDT 24
Peak memory 214936 kb
Host smart-1c9579c9-4e8b-4873-820b-5bccb2347e5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604813427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.604813427
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3303218141
Short name T229
Test name
Test status
Simulation time 135169102 ps
CPU time 0.8 seconds
Started Jul 19 04:59:27 PM PDT 24
Finished Jul 19 04:59:33 PM PDT 24
Peak memory 204988 kb
Host smart-60b8d9b6-658b-46c9-b2b6-20d69d42554b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303218141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3303218141
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3976764421
Short name T152
Test name
Test status
Simulation time 15225055253 ps
CPU time 14.06 seconds
Started Jul 19 04:59:27 PM PDT 24
Finished Jul 19 04:59:46 PM PDT 24
Peak memory 221900 kb
Host smart-f6373fb8-1230-4b51-9f73-c9db068c5c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976764421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3976764421
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.4045472515
Short name T261
Test name
Test status
Simulation time 6518906324 ps
CPU time 12.82 seconds
Started Jul 19 04:59:27 PM PDT 24
Finished Jul 19 04:59:45 PM PDT 24
Peak memory 213628 kb
Host smart-e9133d52-ca02-4c76-a847-b01db86e7685
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4045472515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.4045472515
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1897281921
Short name T245
Test name
Test status
Simulation time 2332243758 ps
CPU time 3.98 seconds
Started Jul 19 04:59:29 PM PDT 24
Finished Jul 19 04:59:38 PM PDT 24
Peak memory 205420 kb
Host smart-08383062-c39e-4867-b588-b39c9920b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897281921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1897281921
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.1076302215
Short name T176
Test name
Test status
Simulation time 3620040811 ps
CPU time 7.21 seconds
Started Jul 19 04:59:30 PM PDT 24
Finished Jul 19 04:59:42 PM PDT 24
Peak memory 205320 kb
Host smart-a4060c99-4dc0-4e98-98e7-e9af73d09975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076302215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.1076302215
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.4095767959
Short name T180
Test name
Test status
Simulation time 45259847 ps
CPU time 0.75 seconds
Started Jul 19 04:59:27 PM PDT 24
Finished Jul 19 04:59:33 PM PDT 24
Peak memory 204932 kb
Host smart-105a6dbc-2920-41a6-b637-676e51ad645b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095767959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.4095767959
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3160854774
Short name T196
Test name
Test status
Simulation time 3963133350 ps
CPU time 2.78 seconds
Started Jul 19 04:59:26 PM PDT 24
Finished Jul 19 04:59:34 PM PDT 24
Peak memory 213540 kb
Host smart-bb23f1ea-dfe0-4c7b-a723-599aed1342b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160854774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3160854774
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.586576647
Short name T44
Test name
Test status
Simulation time 3242187349 ps
CPU time 5.97 seconds
Started Jul 19 04:59:28 PM PDT 24
Finished Jul 19 04:59:39 PM PDT 24
Peak memory 205400 kb
Host smart-f0a057ca-19c0-4a89-96bf-b11135c6621a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586576647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.586576647
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.902386965
Short name T217
Test name
Test status
Simulation time 2397650176 ps
CPU time 3.85 seconds
Started Jul 19 04:59:28 PM PDT 24
Finished Jul 19 04:59:36 PM PDT 24
Peak memory 205424 kb
Host smart-c982ed0e-22ac-47de-9fab-515534d91744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902386965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.902386965
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.1047667444
Short name T283
Test name
Test status
Simulation time 2420409931 ps
CPU time 4.41 seconds
Started Jul 19 04:59:30 PM PDT 24
Finished Jul 19 04:59:39 PM PDT 24
Peak memory 205232 kb
Host smart-1ea47438-912e-4809-ba60-9a947a842fd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047667444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1047667444
Directory /workspace/9.rv_dm_stress_all/latest
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