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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.48 95.57 81.38 89.91 77.50 86.33 98.53 55.12


Total test records in report: 438
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T88 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.409358989 Jul 20 05:55:25 PM PDT 24 Jul 20 05:55:28 PM PDT 24 275865523 ps
T294 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2316130010 Jul 20 05:55:17 PM PDT 24 Jul 20 05:56:15 PM PDT 24 63370437535 ps
T119 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3195683571 Jul 20 05:55:06 PM PDT 24 Jul 20 05:55:18 PM PDT 24 3758750949 ps
T295 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4210932921 Jul 20 05:55:05 PM PDT 24 Jul 20 05:55:08 PM PDT 24 83103250 ps
T93 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.152164547 Jul 20 05:55:08 PM PDT 24 Jul 20 05:55:13 PM PDT 24 4502403778 ps
T89 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2381239065 Jul 20 05:55:17 PM PDT 24 Jul 20 05:55:20 PM PDT 24 132022373 ps
T296 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1110681559 Jul 20 05:55:01 PM PDT 24 Jul 20 05:55:49 PM PDT 24 18366924903 ps
T76 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1513168303 Jul 20 05:55:32 PM PDT 24 Jul 20 05:55:37 PM PDT 24 121083109 ps
T90 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.721183477 Jul 20 05:55:07 PM PDT 24 Jul 20 05:55:14 PM PDT 24 626103754 ps
T91 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2845574546 Jul 20 05:55:26 PM PDT 24 Jul 20 05:55:31 PM PDT 24 306721105 ps
T97 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.726356867 Jul 20 05:55:20 PM PDT 24 Jul 20 05:55:25 PM PDT 24 332333089 ps
T98 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2828393572 Jul 20 05:55:23 PM PDT 24 Jul 20 05:55:31 PM PDT 24 615332351 ps
T297 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2814582537 Jul 20 05:55:29 PM PDT 24 Jul 20 05:55:32 PM PDT 24 621018754 ps
T99 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.888786191 Jul 20 05:55:22 PM PDT 24 Jul 20 05:55:27 PM PDT 24 505412284 ps
T100 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1551950629 Jul 20 05:55:02 PM PDT 24 Jul 20 05:56:23 PM PDT 24 4513586164 ps
T298 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1153997481 Jul 20 05:55:28 PM PDT 24 Jul 20 05:55:33 PM PDT 24 208283031 ps
T299 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1086303202 Jul 20 05:55:15 PM PDT 24 Jul 20 05:55:26 PM PDT 24 6611895854 ps
T114 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2540723988 Jul 20 05:55:05 PM PDT 24 Jul 20 05:56:18 PM PDT 24 20498424094 ps
T300 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1789104341 Jul 20 05:55:13 PM PDT 24 Jul 20 05:57:29 PM PDT 24 47687800599 ps
T301 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1093058919 Jul 20 05:55:15 PM PDT 24 Jul 20 05:55:19 PM PDT 24 235027160 ps
T302 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.273604411 Jul 20 05:55:05 PM PDT 24 Jul 20 05:55:14 PM PDT 24 7737485815 ps
T303 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2349310976 Jul 20 05:55:25 PM PDT 24 Jul 20 05:55:29 PM PDT 24 65150073 ps
T304 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.147073794 Jul 20 05:55:09 PM PDT 24 Jul 20 05:55:12 PM PDT 24 778536015 ps
T305 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2465583096 Jul 20 05:55:04 PM PDT 24 Jul 20 05:55:15 PM PDT 24 7172445512 ps
T306 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2347950096 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:36 PM PDT 24 157083557 ps
T307 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2189776297 Jul 20 05:54:57 PM PDT 24 Jul 20 05:55:00 PM PDT 24 162859367 ps
T308 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3120218764 Jul 20 05:55:23 PM PDT 24 Jul 20 05:55:28 PM PDT 24 9500336812 ps
T309 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3027405398 Jul 20 05:55:16 PM PDT 24 Jul 20 05:55:18 PM PDT 24 134719071 ps
T310 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1348282280 Jul 20 05:55:15 PM PDT 24 Jul 20 05:55:18 PM PDT 24 398140033 ps
T115 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.947225223 Jul 20 05:54:56 PM PDT 24 Jul 20 05:55:00 PM PDT 24 414147772 ps
T101 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3401906755 Jul 20 05:55:25 PM PDT 24 Jul 20 05:55:34 PM PDT 24 1178453446 ps
T311 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1594252986 Jul 20 05:54:58 PM PDT 24 Jul 20 05:55:00 PM PDT 24 220707668 ps
T312 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2019737010 Jul 20 05:55:04 PM PDT 24 Jul 20 05:55:06 PM PDT 24 34459400 ps
T105 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.749256574 Jul 20 05:55:16 PM PDT 24 Jul 20 05:55:20 PM PDT 24 1773441115 ps
T102 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1991900394 Jul 20 05:55:12 PM PDT 24 Jul 20 05:55:15 PM PDT 24 240150418 ps
T313 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2738513832 Jul 20 05:55:30 PM PDT 24 Jul 20 05:55:35 PM PDT 24 969526335 ps
T314 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1402477340 Jul 20 05:55:07 PM PDT 24 Jul 20 05:55:09 PM PDT 24 131675722 ps
T56 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.4250784806 Jul 20 05:55:27 PM PDT 24 Jul 20 05:55:47 PM PDT 24 55385130892 ps
T315 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3052677323 Jul 20 05:55:24 PM PDT 24 Jul 20 05:55:28 PM PDT 24 889735340 ps
T316 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3499206400 Jul 20 05:55:17 PM PDT 24 Jul 20 05:56:12 PM PDT 24 18463532795 ps
T317 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3400823415 Jul 20 05:55:27 PM PDT 24 Jul 20 05:55:44 PM PDT 24 17263457324 ps
T318 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3941311774 Jul 20 05:55:06 PM PDT 24 Jul 20 05:55:09 PM PDT 24 50351080 ps
T103 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1311365705 Jul 20 05:55:14 PM PDT 24 Jul 20 05:55:19 PM PDT 24 389240449 ps
T112 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4143200009 Jul 20 05:55:17 PM PDT 24 Jul 20 05:55:26 PM PDT 24 873190687 ps
T319 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4143423283 Jul 20 05:55:18 PM PDT 24 Jul 20 05:55:23 PM PDT 24 705332185 ps
T104 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3951442307 Jul 20 05:55:06 PM PDT 24 Jul 20 05:55:10 PM PDT 24 183311414 ps
T116 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1881150694 Jul 20 05:55:03 PM PDT 24 Jul 20 05:55:27 PM PDT 24 8032106066 ps
T320 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2586904795 Jul 20 05:55:22 PM PDT 24 Jul 20 05:55:29 PM PDT 24 248982371 ps
T321 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.822994143 Jul 20 05:54:57 PM PDT 24 Jul 20 05:54:59 PM PDT 24 42702638 ps
T322 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2515991006 Jul 20 05:55:29 PM PDT 24 Jul 20 05:55:37 PM PDT 24 4773113139 ps
T323 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3541783160 Jul 20 05:55:17 PM PDT 24 Jul 20 05:55:21 PM PDT 24 1753009980 ps
T324 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2224296582 Jul 20 05:54:57 PM PDT 24 Jul 20 05:55:01 PM PDT 24 2530866647 ps
T109 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.556828032 Jul 20 05:55:27 PM PDT 24 Jul 20 05:56:03 PM PDT 24 10287789718 ps
T325 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1263960068 Jul 20 05:55:01 PM PDT 24 Jul 20 05:55:04 PM PDT 24 283712004 ps
T94 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3565586028 Jul 20 05:54:59 PM PDT 24 Jul 20 05:55:12 PM PDT 24 4176454813 ps
T326 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1183503569 Jul 20 05:55:26 PM PDT 24 Jul 20 05:55:31 PM PDT 24 2984067437 ps
T327 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1082940707 Jul 20 05:55:27 PM PDT 24 Jul 20 05:55:34 PM PDT 24 1416651746 ps
T328 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.784375646 Jul 20 05:55:04 PM PDT 24 Jul 20 05:55:09 PM PDT 24 1483756239 ps
T106 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1979492690 Jul 20 05:54:57 PM PDT 24 Jul 20 05:56:13 PM PDT 24 7954244610 ps
T329 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3046080657 Jul 20 05:54:59 PM PDT 24 Jul 20 05:55:06 PM PDT 24 4958470126 ps
T147 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1361136043 Jul 20 05:55:30 PM PDT 24 Jul 20 05:55:44 PM PDT 24 1645037329 ps
T330 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3534046539 Jul 20 05:55:01 PM PDT 24 Jul 20 05:55:26 PM PDT 24 7499616561 ps
T331 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1961219819 Jul 20 05:55:38 PM PDT 24 Jul 20 05:55:51 PM PDT 24 2533559111 ps
T149 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3582258356 Jul 20 05:55:07 PM PDT 24 Jul 20 05:55:22 PM PDT 24 4398245616 ps
T332 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.641839939 Jul 20 05:55:18 PM PDT 24 Jul 20 05:55:21 PM PDT 24 245822662 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4127640419 Jul 20 05:55:08 PM PDT 24 Jul 20 05:55:12 PM PDT 24 283236014 ps
T334 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.137374685 Jul 20 05:55:20 PM PDT 24 Jul 20 05:55:23 PM PDT 24 1205543610 ps
T335 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2340988569 Jul 20 05:55:07 PM PDT 24 Jul 20 05:55:12 PM PDT 24 1114777134 ps
T336 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1300700103 Jul 20 05:55:23 PM PDT 24 Jul 20 05:55:26 PM PDT 24 189009177 ps
T150 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2326489094 Jul 20 05:55:37 PM PDT 24 Jul 20 05:55:56 PM PDT 24 2950785980 ps
T337 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3888380708 Jul 20 05:55:27 PM PDT 24 Jul 20 05:55:32 PM PDT 24 4034142513 ps
T157 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4033916008 Jul 20 05:55:05 PM PDT 24 Jul 20 05:55:30 PM PDT 24 2979147618 ps
T338 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2389174956 Jul 20 05:55:00 PM PDT 24 Jul 20 05:55:08 PM PDT 24 150576536 ps
T339 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.507847772 Jul 20 05:55:17 PM PDT 24 Jul 20 05:55:22 PM PDT 24 1173539633 ps
T340 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1438690947 Jul 20 05:55:28 PM PDT 24 Jul 20 05:55:31 PM PDT 24 149410296 ps
T341 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.941089143 Jul 20 05:55:33 PM PDT 24 Jul 20 05:55:42 PM PDT 24 2843333950 ps
T342 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2307251965 Jul 20 05:55:15 PM PDT 24 Jul 20 05:55:17 PM PDT 24 92391692 ps
T343 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1337323524 Jul 20 05:55:22 PM PDT 24 Jul 20 05:55:27 PM PDT 24 1975069094 ps
T107 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2014273878 Jul 20 05:55:07 PM PDT 24 Jul 20 05:55:11 PM PDT 24 139895096 ps
T344 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1721122416 Jul 20 05:55:15 PM PDT 24 Jul 20 05:55:26 PM PDT 24 5469222206 ps
T345 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.542269855 Jul 20 05:55:26 PM PDT 24 Jul 20 05:55:42 PM PDT 24 2585352030 ps
T346 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2251432968 Jul 20 05:55:25 PM PDT 24 Jul 20 05:55:31 PM PDT 24 743685012 ps
T347 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.342872901 Jul 20 05:55:26 PM PDT 24 Jul 20 05:55:34 PM PDT 24 4536549136 ps
T348 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2368889389 Jul 20 05:55:32 PM PDT 24 Jul 20 05:55:36 PM PDT 24 290620071 ps
T155 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.649532796 Jul 20 05:55:23 PM PDT 24 Jul 20 05:55:47 PM PDT 24 3628811658 ps
T349 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1684669068 Jul 20 05:55:15 PM PDT 24 Jul 20 05:55:18 PM PDT 24 2473302749 ps
T350 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1441084218 Jul 20 05:55:07 PM PDT 24 Jul 20 06:04:58 PM PDT 24 220818669809 ps
T117 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2168157962 Jul 20 05:55:14 PM PDT 24 Jul 20 05:55:20 PM PDT 24 1315939803 ps
T108 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2549972437 Jul 20 05:55:26 PM PDT 24 Jul 20 05:55:31 PM PDT 24 420070035 ps
T351 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3234223020 Jul 20 05:55:27 PM PDT 24 Jul 20 05:55:45 PM PDT 24 26846497891 ps
T352 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3871513294 Jul 20 05:55:36 PM PDT 24 Jul 20 05:55:44 PM PDT 24 245707127 ps
T353 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.811761582 Jul 20 05:55:04 PM PDT 24 Jul 20 05:55:08 PM PDT 24 849161418 ps
T354 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.996923638 Jul 20 05:55:30 PM PDT 24 Jul 20 05:55:34 PM PDT 24 106952364 ps
T355 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2676864183 Jul 20 05:55:32 PM PDT 24 Jul 20 05:55:38 PM PDT 24 666312166 ps
T356 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3387113911 Jul 20 05:55:37 PM PDT 24 Jul 20 05:55:42 PM PDT 24 197033545 ps
T357 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.410685560 Jul 20 05:55:04 PM PDT 24 Jul 20 05:55:08 PM PDT 24 187502785 ps
T358 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2773973401 Jul 20 05:55:04 PM PDT 24 Jul 20 05:55:06 PM PDT 24 402464382 ps
T359 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2526362655 Jul 20 05:55:28 PM PDT 24 Jul 20 05:55:34 PM PDT 24 184758332 ps
T360 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2474023651 Jul 20 05:55:20 PM PDT 24 Jul 20 05:55:27 PM PDT 24 8132384420 ps
T111 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1198467820 Jul 20 05:55:19 PM PDT 24 Jul 20 05:55:22 PM PDT 24 64458360 ps
T361 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2666112380 Jul 20 05:55:08 PM PDT 24 Jul 20 05:55:23 PM PDT 24 172424362 ps
T362 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1905088495 Jul 20 05:55:11 PM PDT 24 Jul 20 05:55:13 PM PDT 24 435167881 ps
T363 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2079175298 Jul 20 05:55:35 PM PDT 24 Jul 20 05:55:42 PM PDT 24 339123546 ps
T364 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2235938121 Jul 20 05:55:32 PM PDT 24 Jul 20 05:55:38 PM PDT 24 578559474 ps
T365 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.771327397 Jul 20 05:55:30 PM PDT 24 Jul 20 05:56:42 PM PDT 24 27565030665 ps
T366 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3143639214 Jul 20 05:55:35 PM PDT 24 Jul 20 05:55:42 PM PDT 24 188455609 ps
T367 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2964693911 Jul 20 05:55:08 PM PDT 24 Jul 20 05:55:20 PM PDT 24 5613924188 ps
T368 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3174797271 Jul 20 05:55:37 PM PDT 24 Jul 20 05:55:43 PM PDT 24 139477178 ps
T369 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3141783879 Jul 20 05:55:06 PM PDT 24 Jul 20 05:55:08 PM PDT 24 61222006 ps
T95 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4262940912 Jul 20 05:55:09 PM PDT 24 Jul 20 05:55:16 PM PDT 24 7488196953 ps
T370 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1976130524 Jul 20 05:55:04 PM PDT 24 Jul 20 05:55:06 PM PDT 24 72490093 ps
T371 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2084068235 Jul 20 05:55:07 PM PDT 24 Jul 20 05:55:12 PM PDT 24 181372110 ps
T153 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.923044187 Jul 20 05:55:32 PM PDT 24 Jul 20 05:55:45 PM PDT 24 1100075249 ps
T372 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1514113845 Jul 20 05:55:06 PM PDT 24 Jul 20 05:55:13 PM PDT 24 335184904 ps
T373 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2185584898 Jul 20 05:55:06 PM PDT 24 Jul 20 05:56:23 PM PDT 24 52306803656 ps
T374 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3461678161 Jul 20 05:55:15 PM PDT 24 Jul 20 05:55:16 PM PDT 24 39643394 ps
T375 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3925189420 Jul 20 05:55:25 PM PDT 24 Jul 20 05:55:34 PM PDT 24 2280955804 ps
T376 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1276589327 Jul 20 05:55:11 PM PDT 24 Jul 20 05:55:13 PM PDT 24 420041609 ps
T377 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1289855660 Jul 20 05:55:22 PM PDT 24 Jul 20 05:55:26 PM PDT 24 321887485 ps
T378 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1157169897 Jul 20 05:55:05 PM PDT 24 Jul 20 05:55:09 PM PDT 24 332296400 ps
T379 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2938848855 Jul 20 05:55:08 PM PDT 24 Jul 20 05:57:30 PM PDT 24 55932404663 ps
T148 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2789044551 Jul 20 05:55:11 PM PDT 24 Jul 20 05:55:34 PM PDT 24 6318863996 ps
T380 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1654072942 Jul 20 05:55:30 PM PDT 24 Jul 20 05:55:42 PM PDT 24 1795522176 ps
T381 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2403626824 Jul 20 05:55:04 PM PDT 24 Jul 20 06:04:18 PM PDT 24 238151023779 ps
T154 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3582205798 Jul 20 05:55:15 PM PDT 24 Jul 20 05:55:28 PM PDT 24 1995659249 ps
T382 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1176148887 Jul 20 05:55:04 PM PDT 24 Jul 20 05:55:34 PM PDT 24 2542367230 ps
T383 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.4130544206 Jul 20 05:55:17 PM PDT 24 Jul 20 05:55:23 PM PDT 24 91274034 ps
T384 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.4001082575 Jul 20 05:55:16 PM PDT 24 Jul 20 05:55:22 PM PDT 24 339734677 ps
T385 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3102443534 Jul 20 05:55:05 PM PDT 24 Jul 20 05:55:11 PM PDT 24 2180685360 ps
T386 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3231800886 Jul 20 05:55:34 PM PDT 24 Jul 20 05:55:39 PM PDT 24 81457897 ps
T387 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1181018246 Jul 20 05:55:29 PM PDT 24 Jul 20 05:55:34 PM PDT 24 80706396 ps
T96 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.863036686 Jul 20 05:55:01 PM PDT 24 Jul 20 05:55:07 PM PDT 24 4632758566 ps
T388 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2238431061 Jul 20 05:55:03 PM PDT 24 Jul 20 05:56:33 PM PDT 24 190072099912 ps
T389 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3557182358 Jul 20 05:55:01 PM PDT 24 Jul 20 05:56:17 PM PDT 24 14981368583 ps
T390 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1407281730 Jul 20 05:55:39 PM PDT 24 Jul 20 05:55:47 PM PDT 24 2518306983 ps
T391 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2560675150 Jul 20 05:55:16 PM PDT 24 Jul 20 05:55:24 PM PDT 24 781770374 ps
T392 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2664726355 Jul 20 05:55:23 PM PDT 24 Jul 20 05:55:31 PM PDT 24 4001714379 ps
T110 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1526206308 Jul 20 05:55:34 PM PDT 24 Jul 20 05:55:39 PM PDT 24 142891308 ps
T393 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3465542998 Jul 20 05:55:17 PM PDT 24 Jul 20 05:56:47 PM PDT 24 108016012832 ps
T156 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1523892641 Jul 20 05:55:16 PM PDT 24 Jul 20 05:55:35 PM PDT 24 4083401630 ps
T394 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.125561558 Jul 20 05:55:25 PM PDT 24 Jul 20 05:55:27 PM PDT 24 764434699 ps
T395 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.826430807 Jul 20 05:55:29 PM PDT 24 Jul 20 05:55:35 PM PDT 24 98731583 ps
T396 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3575451735 Jul 20 05:55:14 PM PDT 24 Jul 20 05:55:47 PM PDT 24 43119309698 ps
T397 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1710625970 Jul 20 05:55:09 PM PDT 24 Jul 20 05:55:44 PM PDT 24 4348780531 ps
T398 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.36337160 Jul 20 05:55:06 PM PDT 24 Jul 20 05:55:55 PM PDT 24 18487950150 ps
T151 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.946100202 Jul 20 05:55:27 PM PDT 24 Jul 20 05:55:46 PM PDT 24 1196574329 ps
T399 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3628538456 Jul 20 05:55:28 PM PDT 24 Jul 20 05:55:32 PM PDT 24 180281443 ps
T400 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1528222062 Jul 20 05:55:17 PM PDT 24 Jul 20 05:55:20 PM PDT 24 185936500 ps
T401 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.189112675 Jul 20 05:55:08 PM PDT 24 Jul 20 05:55:12 PM PDT 24 108863170 ps
T402 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4135928768 Jul 20 05:55:25 PM PDT 24 Jul 20 05:55:30 PM PDT 24 971260279 ps
T403 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.327930386 Jul 20 05:55:30 PM PDT 24 Jul 20 05:55:34 PM PDT 24 49429280 ps
T404 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.231371640 Jul 20 05:55:22 PM PDT 24 Jul 20 05:56:39 PM PDT 24 25559753304 ps
T405 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4141888336 Jul 20 05:55:18 PM PDT 24 Jul 20 05:55:22 PM PDT 24 298322618 ps
T406 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4000905167 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:36 PM PDT 24 1176284209 ps
T158 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1894277333 Jul 20 05:55:28 PM PDT 24 Jul 20 05:55:44 PM PDT 24 2781837565 ps
T407 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3654355517 Jul 20 05:54:57 PM PDT 24 Jul 20 05:55:14 PM PDT 24 2971101258 ps
T408 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1975808240 Jul 20 05:55:23 PM PDT 24 Jul 20 05:55:30 PM PDT 24 1176526320 ps
T409 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2873327884 Jul 20 05:55:21 PM PDT 24 Jul 20 05:55:32 PM PDT 24 28248011556 ps
T410 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.725183431 Jul 20 05:55:40 PM PDT 24 Jul 20 05:55:46 PM PDT 24 150810337 ps
T411 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1998126358 Jul 20 05:55:36 PM PDT 24 Jul 20 05:56:09 PM PDT 24 14173599976 ps
T412 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.462876054 Jul 20 05:55:08 PM PDT 24 Jul 20 05:55:18 PM PDT 24 9898474951 ps
T413 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.4164490269 Jul 20 05:55:12 PM PDT 24 Jul 20 05:55:16 PM PDT 24 1499636651 ps
T414 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.4127470381 Jul 20 05:55:35 PM PDT 24 Jul 20 05:55:39 PM PDT 24 38785146 ps
T415 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1090741908 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:42 PM PDT 24 3500623528 ps
T416 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3792347748 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:35 PM PDT 24 1222650349 ps
T417 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.950196641 Jul 20 05:55:00 PM PDT 24 Jul 20 05:58:35 PM PDT 24 58487715750 ps
T418 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2028847480 Jul 20 05:55:05 PM PDT 24 Jul 20 05:55:08 PM PDT 24 357524262 ps
T419 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.439487108 Jul 20 05:55:37 PM PDT 24 Jul 20 05:55:41 PM PDT 24 267176728 ps
T420 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.441166460 Jul 20 05:55:20 PM PDT 24 Jul 20 05:55:35 PM PDT 24 6423103027 ps
T421 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.4220416373 Jul 20 05:55:29 PM PDT 24 Jul 20 05:57:11 PM PDT 24 37421085870 ps
T422 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3406690010 Jul 20 05:55:31 PM PDT 24 Jul 20 05:56:52 PM PDT 24 5636063847 ps
T423 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3526628460 Jul 20 05:55:04 PM PDT 24 Jul 20 05:55:33 PM PDT 24 2381964001 ps
T424 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3689809740 Jul 20 05:55:19 PM PDT 24 Jul 20 05:55:26 PM PDT 24 4620012365 ps
T425 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1835980503 Jul 20 05:55:32 PM PDT 24 Jul 20 05:55:39 PM PDT 24 112677169 ps
T426 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3247036583 Jul 20 05:55:33 PM PDT 24 Jul 20 05:55:42 PM PDT 24 1095451679 ps
T427 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.664274181 Jul 20 05:55:08 PM PDT 24 Jul 20 05:56:21 PM PDT 24 76282652015 ps
T428 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1563184676 Jul 20 05:55:22 PM PDT 24 Jul 20 05:55:27 PM PDT 24 3008349394 ps
T152 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1077258063 Jul 20 05:55:15 PM PDT 24 Jul 20 05:55:41 PM PDT 24 4142278435 ps
T429 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.393439629 Jul 20 05:55:37 PM PDT 24 Jul 20 05:55:42 PM PDT 24 1854913066 ps
T430 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3908082555 Jul 20 05:55:38 PM PDT 24 Jul 20 05:55:53 PM PDT 24 4956313703 ps
T431 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3979957058 Jul 20 05:55:10 PM PDT 24 Jul 20 05:55:12 PM PDT 24 363130331 ps
T432 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3931680260 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:36 PM PDT 24 2018673935 ps
T433 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3072089576 Jul 20 05:55:18 PM PDT 24 Jul 20 05:55:21 PM PDT 24 234669838 ps
T434 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.4271819406 Jul 20 05:55:37 PM PDT 24 Jul 20 05:55:42 PM PDT 24 199543164 ps
T435 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2746967758 Jul 20 05:55:23 PM PDT 24 Jul 20 05:55:41 PM PDT 24 5949856549 ps
T436 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2083915158 Jul 20 05:55:32 PM PDT 24 Jul 20 05:56:01 PM PDT 24 15186630170 ps
T437 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3044555806 Jul 20 05:55:22 PM PDT 24 Jul 20 05:55:27 PM PDT 24 305608106 ps
T438 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2741852026 Jul 20 05:55:26 PM PDT 24 Jul 20 05:55:32 PM PDT 24 398273587 ps

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2794414046
Short name T16
Test name
Test status
Simulation time 4860880783 ps
CPU time 3.52 seconds
Started Jul 20 06:47:47 PM PDT 24
Finished Jul 20 06:47:53 PM PDT 24
Peak memory 205424 kb
Host smart-68608d75-cb5e-4b29-91ba-59dadd7412a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794414046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2794414046
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.3186639354
Short name T18
Test name
Test status
Simulation time 11171449747 ps
CPU time 35.01 seconds
Started Jul 20 06:48:10 PM PDT 24
Finished Jul 20 06:48:47 PM PDT 24
Peak memory 213424 kb
Host smart-cd565f3c-e408-45e0-8f04-81a1a4ca6a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186639354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3186639354
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3797275698
Short name T71
Test name
Test status
Simulation time 90754674502 ps
CPU time 207.2 seconds
Started Jul 20 05:55:27 PM PDT 24
Finished Jul 20 05:58:56 PM PDT 24
Peak memory 224308 kb
Host smart-5acb673e-1e23-43c8-98f1-b3a7b564a6ba
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797275698 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3797275698
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.3358090133
Short name T10
Test name
Test status
Simulation time 6513332785 ps
CPU time 6.14 seconds
Started Jul 20 06:48:01 PM PDT 24
Finished Jul 20 06:48:09 PM PDT 24
Peak memory 213508 kb
Host smart-6e86b43b-d982-4c7b-964e-51b1036e89ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358090133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3358090133
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.243912112
Short name T61
Test name
Test status
Simulation time 8677850237 ps
CPU time 20.76 seconds
Started Jul 20 05:55:18 PM PDT 24
Finished Jul 20 05:55:41 PM PDT 24
Peak memory 213748 kb
Host smart-7d883d79-4dad-4442-96e2-1e81ae135799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243912112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.243912112
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.411189909
Short name T32
Test name
Test status
Simulation time 46528413860 ps
CPU time 67.45 seconds
Started Jul 20 06:47:23 PM PDT 24
Finished Jul 20 06:48:32 PM PDT 24
Peak memory 213748 kb
Host smart-cbca037b-bc12-4f7e-870c-5dbeb41844e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411189909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.411189909
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.4139902360
Short name T50
Test name
Test status
Simulation time 147517988 ps
CPU time 0.96 seconds
Started Jul 20 06:47:53 PM PDT 24
Finished Jul 20 06:47:55 PM PDT 24
Peak memory 204908 kb
Host smart-f843b966-f367-4a10-8e23-9969c4a2b927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139902360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.4139902360
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.47667763
Short name T46
Test name
Test status
Simulation time 165768234 ps
CPU time 0.86 seconds
Started Jul 20 06:47:27 PM PDT 24
Finished Jul 20 06:47:28 PM PDT 24
Peak memory 215488 kb
Host smart-7066d87d-5512-41a7-ace4-3f73d07a735c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47667763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.47667763
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2669155550
Short name T23
Test name
Test status
Simulation time 451390236 ps
CPU time 1.34 seconds
Started Jul 20 06:47:22 PM PDT 24
Finished Jul 20 06:47:24 PM PDT 24
Peak memory 205004 kb
Host smart-1396e9c7-2c24-4b2a-8d1b-fb5787a59c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669155550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2669155550
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.1523705480
Short name T22
Test name
Test status
Simulation time 8704484320 ps
CPU time 12.36 seconds
Started Jul 20 06:48:07 PM PDT 24
Finished Jul 20 06:48:21 PM PDT 24
Peak memory 213640 kb
Host smart-d41885db-0078-468f-b551-5a081b8e0dfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523705480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1523705480
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1551950629
Short name T100
Test name
Test status
Simulation time 4513586164 ps
CPU time 79.78 seconds
Started Jul 20 05:55:02 PM PDT 24
Finished Jul 20 05:56:23 PM PDT 24
Peak memory 205500 kb
Host smart-9654d84d-b96d-475b-9b9e-98ba6f86c2ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551950629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1551950629
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2781050954
Short name T70
Test name
Test status
Simulation time 1455888043 ps
CPU time 4.67 seconds
Started Jul 20 06:47:28 PM PDT 24
Finished Jul 20 06:47:35 PM PDT 24
Peak memory 205164 kb
Host smart-6ec7dd57-8c61-4718-bd8a-95ffb273e8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781050954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2781050954
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.774940377
Short name T73
Test name
Test status
Simulation time 26218841697 ps
CPU time 70.64 seconds
Started Jul 20 05:55:23 PM PDT 24
Finished Jul 20 05:56:35 PM PDT 24
Peak memory 221900 kb
Host smart-17a84e2a-c1c5-4f19-8284-b8782f3c38d3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774940377 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.774940377
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.328707208
Short name T52
Test name
Test status
Simulation time 228574755 ps
CPU time 1.84 seconds
Started Jul 20 06:47:28 PM PDT 24
Finished Jul 20 06:47:32 PM PDT 24
Peak memory 229696 kb
Host smart-9694ea46-2c63-407e-9469-cd900f9664ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328707208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.328707208
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.94910767
Short name T21
Test name
Test status
Simulation time 5638907475 ps
CPU time 8.91 seconds
Started Jul 20 06:48:08 PM PDT 24
Finished Jul 20 06:48:19 PM PDT 24
Peak memory 213576 kb
Host smart-1e6d7197-5351-4f16-aad7-cf8ddbad1aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94910767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.94910767
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.346371644
Short name T41
Test name
Test status
Simulation time 172672056 ps
CPU time 0.79 seconds
Started Jul 20 06:47:21 PM PDT 24
Finished Jul 20 06:47:22 PM PDT 24
Peak memory 205020 kb
Host smart-fff23688-b911-48c8-a499-5ee3dbb39681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346371644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.346371644
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3248901645
Short name T142
Test name
Test status
Simulation time 3803800596 ps
CPU time 7.18 seconds
Started Jul 20 06:47:49 PM PDT 24
Finished Jul 20 06:47:57 PM PDT 24
Peak memory 213704 kb
Host smart-fa09fe71-52bf-492f-9175-2336963a35eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248901645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3248901645
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1740531180
Short name T38
Test name
Test status
Simulation time 58361261 ps
CPU time 0.84 seconds
Started Jul 20 06:47:21 PM PDT 24
Finished Jul 20 06:47:23 PM PDT 24
Peak memory 213316 kb
Host smart-793415f8-b5e0-4d3b-9a70-4fa6cc588643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740531180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1740531180
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.4250784806
Short name T56
Test name
Test status
Simulation time 55385130892 ps
CPU time 17.85 seconds
Started Jul 20 05:55:27 PM PDT 24
Finished Jul 20 05:55:47 PM PDT 24
Peak memory 221912 kb
Host smart-31a75f60-e1ff-4d16-871d-8573ea11f237
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250784806 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.4250784806
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.391415330
Short name T86
Test name
Test status
Simulation time 360115324 ps
CPU time 3.51 seconds
Started Jul 20 05:55:26 PM PDT 24
Finished Jul 20 05:55:32 PM PDT 24
Peak memory 204992 kb
Host smart-441098ad-a595-4956-a14d-65c7b8f9ed6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391415330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.391415330
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3885142199
Short name T26
Test name
Test status
Simulation time 16024942313 ps
CPU time 8.59 seconds
Started Jul 20 06:47:46 PM PDT 24
Finished Jul 20 06:47:56 PM PDT 24
Peak memory 213444 kb
Host smart-0c501867-44e5-4488-8246-23f7f06c55b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885142199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3885142199
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1881150694
Short name T116
Test name
Test status
Simulation time 8032106066 ps
CPU time 22.23 seconds
Started Jul 20 05:55:03 PM PDT 24
Finished Jul 20 05:55:27 PM PDT 24
Peak memory 213720 kb
Host smart-354d71cc-1725-4636-a05d-58eb4aaae6d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881150694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1881150694
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.657415742
Short name T25
Test name
Test status
Simulation time 1209013516 ps
CPU time 1.59 seconds
Started Jul 20 06:47:22 PM PDT 24
Finished Jul 20 06:47:25 PM PDT 24
Peak memory 205256 kb
Host smart-b2418d48-1fb5-4f0e-b9dc-1153aba9c942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657415742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.657415742
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.3363457092
Short name T44
Test name
Test status
Simulation time 326910721 ps
CPU time 1.22 seconds
Started Jul 20 06:47:22 PM PDT 24
Finished Jul 20 06:47:25 PM PDT 24
Peak memory 204996 kb
Host smart-ab7386ac-b993-42fb-80e9-d5d9c388fcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363457092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.3363457092
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3394363192
Short name T239
Test name
Test status
Simulation time 42854389780 ps
CPU time 112.51 seconds
Started Jul 20 06:47:39 PM PDT 24
Finished Jul 20 06:49:33 PM PDT 24
Peak memory 213636 kb
Host smart-fae85883-bce7-4ff6-aa48-9826b9efd3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394363192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3394363192
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.3556322432
Short name T30
Test name
Test status
Simulation time 295553988 ps
CPU time 0.85 seconds
Started Jul 20 06:47:27 PM PDT 24
Finished Jul 20 06:47:29 PM PDT 24
Peak memory 204996 kb
Host smart-0fc09f91-812b-4e4e-b462-db2217475877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556322432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3556322432
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.779376278
Short name T35
Test name
Test status
Simulation time 270750367 ps
CPU time 0.99 seconds
Started Jul 20 06:47:30 PM PDT 24
Finished Jul 20 06:47:33 PM PDT 24
Peak memory 205024 kb
Host smart-1cc0479f-b1e8-46d7-8d51-3c9a7fda348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779376278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.779376278
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.923044187
Short name T153
Test name
Test status
Simulation time 1100075249 ps
CPU time 9.17 seconds
Started Jul 20 05:55:32 PM PDT 24
Finished Jul 20 05:55:45 PM PDT 24
Peak memory 213740 kb
Host smart-e805ca16-72ca-483f-b678-f51eeb2cd768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923044187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.923044187
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2999501602
Short name T12
Test name
Test status
Simulation time 4454111276 ps
CPU time 4.83 seconds
Started Jul 20 06:48:01 PM PDT 24
Finished Jul 20 06:48:08 PM PDT 24
Peak memory 205308 kb
Host smart-26346b48-85f5-4b7f-ac5b-958e3c139be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999501602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2999501602
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2189776297
Short name T307
Test name
Test status
Simulation time 162859367 ps
CPU time 0.93 seconds
Started Jul 20 05:54:57 PM PDT 24
Finished Jul 20 05:55:00 PM PDT 24
Peak memory 204984 kb
Host smart-b856c56a-8db9-43a7-966d-518ee1ca5aef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189776297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2189776297
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.2235586455
Short name T43
Test name
Test status
Simulation time 3841776583 ps
CPU time 2.02 seconds
Started Jul 20 06:48:00 PM PDT 24
Finished Jul 20 06:48:05 PM PDT 24
Peak memory 213480 kb
Host smart-8c3f3a98-d4ad-423f-bfe8-97f60c9fb4bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235586455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2235586455
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.863036686
Short name T96
Test name
Test status
Simulation time 4632758566 ps
CPU time 4.73 seconds
Started Jul 20 05:55:01 PM PDT 24
Finished Jul 20 05:55:07 PM PDT 24
Peak memory 205424 kb
Host smart-83697f00-8dee-4d24-b1a6-e544c85a32f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863036686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.863036686
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3195683571
Short name T119
Test name
Test status
Simulation time 3758750949 ps
CPU time 10.41 seconds
Started Jul 20 05:55:06 PM PDT 24
Finished Jul 20 05:55:18 PM PDT 24
Peak memory 213600 kb
Host smart-610c3df1-da80-4748-bc3a-7e693784aa52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195683571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3195683571
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.946100202
Short name T151
Test name
Test status
Simulation time 1196574329 ps
CPU time 17.09 seconds
Started Jul 20 05:55:27 PM PDT 24
Finished Jul 20 05:55:46 PM PDT 24
Peak memory 213636 kb
Host smart-41c02eec-110f-452f-845c-113fabd03a1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946100202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.946100202
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2789044551
Short name T148
Test name
Test status
Simulation time 6318863996 ps
CPU time 21.54 seconds
Started Jul 20 05:55:11 PM PDT 24
Finished Jul 20 05:55:34 PM PDT 24
Peak memory 213768 kb
Host smart-934366da-789e-460d-9e7b-9e5a82584b9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789044551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2789044551
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1462964562
Short name T143
Test name
Test status
Simulation time 923417419 ps
CPU time 1.43 seconds
Started Jul 20 06:47:22 PM PDT 24
Finished Jul 20 06:47:25 PM PDT 24
Peak memory 204972 kb
Host smart-9f07930c-b5ca-473e-99c5-a4cf9d56fab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462964562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1462964562
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3805886084
Short name T120
Test name
Test status
Simulation time 17340075495 ps
CPU time 49.72 seconds
Started Jul 20 06:47:45 PM PDT 24
Finished Jul 20 06:48:36 PM PDT 24
Peak memory 217564 kb
Host smart-7c30fe08-f986-4a4e-8ee8-b612d4620ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805886084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3805886084
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2835901757
Short name T124
Test name
Test status
Simulation time 5772420069 ps
CPU time 2.59 seconds
Started Jul 20 06:47:52 PM PDT 24
Finished Jul 20 06:47:56 PM PDT 24
Peak memory 205348 kb
Host smart-7110a4cd-81fe-48a8-a792-0b2a29112352
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835901757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2835901757
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.1433731417
Short name T130
Test name
Test status
Simulation time 4255806514 ps
CPU time 3.59 seconds
Started Jul 20 06:48:00 PM PDT 24
Finished Jul 20 06:48:06 PM PDT 24
Peak memory 213416 kb
Host smart-e2fbf1de-0860-43a5-96ad-03d86d02f846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433731417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1433731417
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.291838260
Short name T5
Test name
Test status
Simulation time 6089844501 ps
CPU time 4.27 seconds
Started Jul 20 06:48:07 PM PDT 24
Finished Jul 20 06:48:12 PM PDT 24
Peak memory 213508 kb
Host smart-82972d5d-2c24-4ebb-91bd-e34129ac448b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291838260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.291838260
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1526206308
Short name T110
Test name
Test status
Simulation time 142891308 ps
CPU time 1.58 seconds
Started Jul 20 05:55:34 PM PDT 24
Finished Jul 20 05:55:39 PM PDT 24
Peak memory 213512 kb
Host smart-ddc3b1f4-7e8a-4ad7-91af-fb5000263ca4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526206308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1526206308
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1627946333
Short name T217
Test name
Test status
Simulation time 121944153 ps
CPU time 0.97 seconds
Started Jul 20 06:47:21 PM PDT 24
Finished Jul 20 06:47:22 PM PDT 24
Peak memory 205028 kb
Host smart-14371e23-3031-4160-9e3f-60cac76e4e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627946333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1627946333
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3557182358
Short name T389
Test name
Test status
Simulation time 14981368583 ps
CPU time 74.8 seconds
Started Jul 20 05:55:01 PM PDT 24
Finished Jul 20 05:56:17 PM PDT 24
Peak memory 205364 kb
Host smart-922c7dfb-53ce-451e-a497-53298a412f10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557182358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3557182358
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1049362234
Short name T83
Test name
Test status
Simulation time 160807613 ps
CPU time 1.51 seconds
Started Jul 20 05:54:56 PM PDT 24
Finished Jul 20 05:54:58 PM PDT 24
Peak memory 213544 kb
Host smart-98644c49-b10b-4956-9150-711ce17d10d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049362234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1049362234
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.921200663
Short name T78
Test name
Test status
Simulation time 3962004014 ps
CPU time 5.26 seconds
Started Jul 20 05:54:57 PM PDT 24
Finished Jul 20 05:55:03 PM PDT 24
Peak memory 219820 kb
Host smart-ff986a87-8524-420f-89f1-e065c692d569
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921200663 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.921200663
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3626961010
Short name T85
Test name
Test status
Simulation time 225581940 ps
CPU time 1.62 seconds
Started Jul 20 05:54:57 PM PDT 24
Finished Jul 20 05:55:00 PM PDT 24
Peak memory 213536 kb
Host smart-ac804367-f98a-4c7f-b1cc-ed2a825ef00f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626961010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3626961010
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3575451735
Short name T396
Test name
Test status
Simulation time 43119309698 ps
CPU time 32.29 seconds
Started Jul 20 05:55:14 PM PDT 24
Finished Jul 20 05:55:47 PM PDT 24
Peak memory 205260 kb
Host smart-21d7f47a-23f5-4511-b9d5-9d40ad6310f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575451735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3575451735
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3534046539
Short name T330
Test name
Test status
Simulation time 7499616561 ps
CPU time 24.01 seconds
Started Jul 20 05:55:01 PM PDT 24
Finished Jul 20 05:55:26 PM PDT 24
Peak memory 205392 kb
Host smart-286a94c3-3a80-41ea-b9bc-443f70cc2296
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534046539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.3534046539
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2224296582
Short name T324
Test name
Test status
Simulation time 2530866647 ps
CPU time 3 seconds
Started Jul 20 05:54:57 PM PDT 24
Finished Jul 20 05:55:01 PM PDT 24
Peak memory 205300 kb
Host smart-933c22ea-fb0d-4028-8ec1-9923f715c222
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224296582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
224296582
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2465583096
Short name T305
Test name
Test status
Simulation time 7172445512 ps
CPU time 9.93 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 05:55:15 PM PDT 24
Peak memory 205368 kb
Host smart-5d4d2596-a51e-402a-b5f5-5ccc9d857d3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465583096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2465583096
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1905088495
Short name T362
Test name
Test status
Simulation time 435167881 ps
CPU time 0.82 seconds
Started Jul 20 05:55:11 PM PDT 24
Finished Jul 20 05:55:13 PM PDT 24
Peak memory 205000 kb
Host smart-b955cfa9-5d60-41a0-a131-a635c60c7646
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905088495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1905088495
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2389174956
Short name T338
Test name
Test status
Simulation time 150576536 ps
CPU time 1.02 seconds
Started Jul 20 05:55:00 PM PDT 24
Finished Jul 20 05:55:08 PM PDT 24
Peak memory 205000 kb
Host smart-3ae78d78-515b-422e-b4c9-6abc9b485d07
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389174956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
389174956
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.822994143
Short name T321
Test name
Test status
Simulation time 42702638 ps
CPU time 0.77 seconds
Started Jul 20 05:54:57 PM PDT 24
Finished Jul 20 05:54:59 PM PDT 24
Peak memory 205028 kb
Host smart-39d09183-08cb-4d32-a87d-1a163ac0a245
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822994143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.822994143
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1976130524
Short name T370
Test name
Test status
Simulation time 72490093 ps
CPU time 0.73 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 05:55:06 PM PDT 24
Peak memory 204980 kb
Host smart-74454a2a-0ee9-4d50-8b90-13a39d639831
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976130524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1976130524
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1311365705
Short name T103
Test name
Test status
Simulation time 389240449 ps
CPU time 4.59 seconds
Started Jul 20 05:55:14 PM PDT 24
Finished Jul 20 05:55:19 PM PDT 24
Peak memory 205348 kb
Host smart-0cdd0b8e-0e81-4020-a74e-5a193beee47d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311365705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1311365705
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.950196641
Short name T417
Test name
Test status
Simulation time 58487715750 ps
CPU time 214.56 seconds
Started Jul 20 05:55:00 PM PDT 24
Finished Jul 20 05:58:35 PM PDT 24
Peak memory 225184 kb
Host smart-c2720485-5aed-45ad-8cc7-1b2670414a4f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950196641 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.950196641
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.947225223
Short name T115
Test name
Test status
Simulation time 414147772 ps
CPU time 2.77 seconds
Started Jul 20 05:54:56 PM PDT 24
Finished Jul 20 05:55:00 PM PDT 24
Peak memory 213748 kb
Host smart-e9d8908e-470b-4415-8869-a46665fd0dc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947225223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.947225223
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3654355517
Short name T407
Test name
Test status
Simulation time 2971101258 ps
CPU time 15.89 seconds
Started Jul 20 05:54:57 PM PDT 24
Finished Jul 20 05:55:14 PM PDT 24
Peak memory 213676 kb
Host smart-0e7a4fad-c5c9-438b-b860-2556e4d6e049
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654355517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3654355517
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1979492690
Short name T106
Test name
Test status
Simulation time 7954244610 ps
CPU time 75.03 seconds
Started Jul 20 05:54:57 PM PDT 24
Finished Jul 20 05:56:13 PM PDT 24
Peak memory 213844 kb
Host smart-8b59b5e1-678d-4ceb-af52-f7ec1ba0cb41
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979492690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1979492690
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.556828032
Short name T109
Test name
Test status
Simulation time 10287789718 ps
CPU time 33.76 seconds
Started Jul 20 05:55:27 PM PDT 24
Finished Jul 20 05:56:03 PM PDT 24
Peak memory 205352 kb
Host smart-e31bc581-14ad-479a-b5b4-98c0c1039f9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556828032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.556828032
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3951442307
Short name T104
Test name
Test status
Simulation time 183311414 ps
CPU time 1.83 seconds
Started Jul 20 05:55:06 PM PDT 24
Finished Jul 20 05:55:10 PM PDT 24
Peak memory 213552 kb
Host smart-a3d1efb9-5005-403b-ae96-9f224aa07f23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951442307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3951442307
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.410685560
Short name T357
Test name
Test status
Simulation time 187502785 ps
CPU time 2.44 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 05:55:08 PM PDT 24
Peak memory 217352 kb
Host smart-150c8c47-0f33-4c32-b64c-e5dc5d112209
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410685560 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.410685560
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4127640419
Short name T333
Test name
Test status
Simulation time 283236014 ps
CPU time 2.54 seconds
Started Jul 20 05:55:08 PM PDT 24
Finished Jul 20 05:55:12 PM PDT 24
Peak memory 213552 kb
Host smart-dbde809f-2844-4d07-9970-f2dea771b000
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127640419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.4127640419
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3652956151
Short name T291
Test name
Test status
Simulation time 69152889682 ps
CPU time 69.98 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 05:56:16 PM PDT 24
Peak memory 205308 kb
Host smart-34eafb2c-5a23-40fc-a297-7bd228d3431e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652956151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3652956151
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1110681559
Short name T296
Test name
Test status
Simulation time 18366924903 ps
CPU time 46.04 seconds
Started Jul 20 05:55:01 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 205324 kb
Host smart-ec7701b7-3e58-4511-b5d9-9271ad5edbf8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110681559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1110681559
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3565586028
Short name T94
Test name
Test status
Simulation time 4176454813 ps
CPU time 12.68 seconds
Started Jul 20 05:54:59 PM PDT 24
Finished Jul 20 05:55:12 PM PDT 24
Peak memory 205340 kb
Host smart-34f9533a-63f3-4ee1-9dde-785728468a3f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565586028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3565586028
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3586471544
Short name T289
Test name
Test status
Simulation time 15460510758 ps
CPU time 39.87 seconds
Started Jul 20 05:54:57 PM PDT 24
Finished Jul 20 05:55:38 PM PDT 24
Peak memory 205276 kb
Host smart-b6b15fbe-394e-47fa-9570-aff0edf50a6c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586471544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
586471544
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1594252986
Short name T311
Test name
Test status
Simulation time 220707668 ps
CPU time 0.83 seconds
Started Jul 20 05:54:58 PM PDT 24
Finished Jul 20 05:55:00 PM PDT 24
Peak memory 205004 kb
Host smart-6f7176ad-3e8a-49df-8c3e-9ce6bd6866d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594252986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1594252986
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3046080657
Short name T329
Test name
Test status
Simulation time 4958470126 ps
CPU time 5.04 seconds
Started Jul 20 05:54:59 PM PDT 24
Finished Jul 20 05:55:06 PM PDT 24
Peak memory 205320 kb
Host smart-907c6beb-e16d-41d5-8c35-b485460649aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046080657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3046080657
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1276589327
Short name T376
Test name
Test status
Simulation time 420041609 ps
CPU time 1.53 seconds
Started Jul 20 05:55:11 PM PDT 24
Finished Jul 20 05:55:13 PM PDT 24
Peak memory 205000 kb
Host smart-f9a7b546-4519-4fd2-89b4-c072052c73fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276589327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1276589327
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1263960068
Short name T325
Test name
Test status
Simulation time 283712004 ps
CPU time 1.02 seconds
Started Jul 20 05:55:01 PM PDT 24
Finished Jul 20 05:55:04 PM PDT 24
Peak memory 205000 kb
Host smart-8d449adf-d0c8-400a-ab56-470f6272c8b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263960068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
263960068
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3941311774
Short name T318
Test name
Test status
Simulation time 50351080 ps
CPU time 0.8 seconds
Started Jul 20 05:55:06 PM PDT 24
Finished Jul 20 05:55:09 PM PDT 24
Peak memory 205024 kb
Host smart-0406a929-6b42-4f0b-9336-abda88b6c6c0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941311774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3941311774
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2019737010
Short name T312
Test name
Test status
Simulation time 34459400 ps
CPU time 0.75 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 05:55:06 PM PDT 24
Peak memory 204980 kb
Host smart-93f03b93-6538-4b77-82f4-26a9afbbf6c5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019737010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2019737010
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.721183477
Short name T90
Test name
Test status
Simulation time 626103754 ps
CPU time 4.35 seconds
Started Jul 20 05:55:07 PM PDT 24
Finished Jul 20 05:55:14 PM PDT 24
Peak memory 205172 kb
Host smart-b80f72da-2d9d-4990-82c3-bbf8042b3380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721183477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.721183477
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.664274181
Short name T427
Test name
Test status
Simulation time 76282652015 ps
CPU time 71.06 seconds
Started Jul 20 05:55:08 PM PDT 24
Finished Jul 20 05:56:21 PM PDT 24
Peak memory 221976 kb
Host smart-1abb655a-80e0-42c2-a593-79db78959a27
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664274181 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.664274181
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1472934501
Short name T82
Test name
Test status
Simulation time 58944044 ps
CPU time 2.74 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 05:55:09 PM PDT 24
Peak memory 213648 kb
Host smart-733a77ed-edff-4697-956e-6e1dcbaf53c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472934501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1472934501
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4033916008
Short name T157
Test name
Test status
Simulation time 2979147618 ps
CPU time 22.87 seconds
Started Jul 20 05:55:05 PM PDT 24
Finished Jul 20 05:55:30 PM PDT 24
Peak memory 213624 kb
Host smart-c7eb01d2-d339-4405-879a-28d8468d3b2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033916008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.4033916008
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.4147587945
Short name T79
Test name
Test status
Simulation time 4225133534 ps
CPU time 6.39 seconds
Started Jul 20 05:55:23 PM PDT 24
Finished Jul 20 05:55:31 PM PDT 24
Peak memory 213712 kb
Host smart-4799e448-bcd5-41d0-998d-7be230cf9073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147587945 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.4147587945
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.749256574
Short name T105
Test name
Test status
Simulation time 1773441115 ps
CPU time 2.62 seconds
Started Jul 20 05:55:16 PM PDT 24
Finished Jul 20 05:55:20 PM PDT 24
Peak memory 213500 kb
Host smart-72490cbc-f9bd-4f65-8a36-f9084bf1cfad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749256574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.749256574
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.4220416373
Short name T421
Test name
Test status
Simulation time 37421085870 ps
CPU time 100.41 seconds
Started Jul 20 05:55:29 PM PDT 24
Finished Jul 20 05:57:11 PM PDT 24
Peak memory 205300 kb
Host smart-7c43a421-db70-4856-b9e6-653a660fd709
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220416373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.4220416373
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3541783160
Short name T323
Test name
Test status
Simulation time 1753009980 ps
CPU time 2.12 seconds
Started Jul 20 05:55:17 PM PDT 24
Finished Jul 20 05:55:21 PM PDT 24
Peak memory 204560 kb
Host smart-4058224c-4906-441e-9a0c-4e5ecfe0f9f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541783160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3541783160
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.641839939
Short name T332
Test name
Test status
Simulation time 245822662 ps
CPU time 0.91 seconds
Started Jul 20 05:55:18 PM PDT 24
Finished Jul 20 05:55:21 PM PDT 24
Peak memory 204932 kb
Host smart-7bced656-e141-45e8-a249-7126ed5188ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641839939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.641839939
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2560675150
Short name T391
Test name
Test status
Simulation time 781770374 ps
CPU time 7.69 seconds
Started Jul 20 05:55:16 PM PDT 24
Finished Jul 20 05:55:24 PM PDT 24
Peak memory 205304 kb
Host smart-aabcc169-3e27-49e2-99a3-46d3d788f584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560675150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2560675150
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2888473282
Short name T62
Test name
Test status
Simulation time 104973270 ps
CPU time 4.09 seconds
Started Jul 20 05:55:16 PM PDT 24
Finished Jul 20 05:55:21 PM PDT 24
Peak memory 213636 kb
Host smart-04ccdbf3-1c1f-470c-9fb0-6dc7b103967e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888473282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2888473282
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2676864183
Short name T355
Test name
Test status
Simulation time 666312166 ps
CPU time 2.25 seconds
Started Jul 20 05:55:32 PM PDT 24
Finished Jul 20 05:55:38 PM PDT 24
Peak memory 214852 kb
Host smart-13e3adec-7d60-4317-a923-b82972a0567c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676864183 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2676864183
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.409358989
Short name T88
Test name
Test status
Simulation time 275865523 ps
CPU time 2.2 seconds
Started Jul 20 05:55:25 PM PDT 24
Finished Jul 20 05:55:28 PM PDT 24
Peak memory 213548 kb
Host smart-85612727-8906-4aff-8a2e-4868979bb2b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409358989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.409358989
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3465542998
Short name T393
Test name
Test status
Simulation time 108016012832 ps
CPU time 88 seconds
Started Jul 20 05:55:17 PM PDT 24
Finished Jul 20 05:56:47 PM PDT 24
Peak memory 205300 kb
Host smart-1a90689a-56d1-4d43-8cf1-d4fc125769b3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465542998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3465542998
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3888380708
Short name T337
Test name
Test status
Simulation time 4034142513 ps
CPU time 3.41 seconds
Started Jul 20 05:55:27 PM PDT 24
Finished Jul 20 05:55:32 PM PDT 24
Peak memory 205240 kb
Host smart-2a8978e9-d7ad-4cee-8f00-73b943d442e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888380708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3888380708
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1438690947
Short name T340
Test name
Test status
Simulation time 149410296 ps
CPU time 1.08 seconds
Started Jul 20 05:55:28 PM PDT 24
Finished Jul 20 05:55:31 PM PDT 24
Peak memory 205004 kb
Host smart-43ffcdc3-9ba7-475f-8fdc-841d6c6670d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438690947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1438690947
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.726356867
Short name T97
Test name
Test status
Simulation time 332333089 ps
CPU time 3.7 seconds
Started Jul 20 05:55:20 PM PDT 24
Finished Jul 20 05:55:25 PM PDT 24
Peak memory 205440 kb
Host smart-4b5f033d-e351-45be-acf4-73a839eb9ab9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726356867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.726356867
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2526362655
Short name T359
Test name
Test status
Simulation time 184758332 ps
CPU time 4.56 seconds
Started Jul 20 05:55:28 PM PDT 24
Finished Jul 20 05:55:34 PM PDT 24
Peak memory 213700 kb
Host smart-cf4e4c2a-a03e-4145-87ba-47b5541cd9e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526362655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2526362655
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1361136043
Short name T147
Test name
Test status
Simulation time 1645037329 ps
CPU time 11.21 seconds
Started Jul 20 05:55:30 PM PDT 24
Finished Jul 20 05:55:44 PM PDT 24
Peak memory 213644 kb
Host smart-6b2f7498-0fd2-4f63-b727-67012392c735
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361136043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
361136043
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1153997481
Short name T298
Test name
Test status
Simulation time 208283031 ps
CPU time 2.92 seconds
Started Jul 20 05:55:28 PM PDT 24
Finished Jul 20 05:55:33 PM PDT 24
Peak memory 217492 kb
Host smart-db9d80e3-5c78-481e-851a-cbcb6dba1939
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153997481 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1153997481
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.439487108
Short name T419
Test name
Test status
Simulation time 267176728 ps
CPU time 1.69 seconds
Started Jul 20 05:55:37 PM PDT 24
Finished Jul 20 05:55:41 PM PDT 24
Peak memory 213548 kb
Host smart-898c33ea-075f-4093-8328-b64477cf7fe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439487108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.439487108
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2873327884
Short name T409
Test name
Test status
Simulation time 28248011556 ps
CPU time 10.18 seconds
Started Jul 20 05:55:21 PM PDT 24
Finished Jul 20 05:55:32 PM PDT 24
Peak memory 205376 kb
Host smart-087e8207-2b45-4d19-b50f-cb66c17b0dee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873327884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2873327884
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.441166460
Short name T420
Test name
Test status
Simulation time 6423103027 ps
CPU time 13.33 seconds
Started Jul 20 05:55:20 PM PDT 24
Finished Jul 20 05:55:35 PM PDT 24
Peak memory 205376 kb
Host smart-dbc85be8-f69b-45c2-bed2-aab17eaf5e89
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441166460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.441166460
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3027405398
Short name T309
Test name
Test status
Simulation time 134719071 ps
CPU time 0.78 seconds
Started Jul 20 05:55:16 PM PDT 24
Finished Jul 20 05:55:18 PM PDT 24
Peak memory 204980 kb
Host smart-17837494-5293-4cd9-b37e-b57fce3758ac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027405398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3027405398
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.888786191
Short name T99
Test name
Test status
Simulation time 505412284 ps
CPU time 4.27 seconds
Started Jul 20 05:55:22 PM PDT 24
Finished Jul 20 05:55:27 PM PDT 24
Peak memory 205348 kb
Host smart-9bde23c7-39a4-4d8d-8bc1-99f358cad7a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888786191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.888786191
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3174797271
Short name T368
Test name
Test status
Simulation time 139477178 ps
CPU time 3.15 seconds
Started Jul 20 05:55:37 PM PDT 24
Finished Jul 20 05:55:43 PM PDT 24
Peak memory 213652 kb
Host smart-136bd746-025a-4583-8a71-469191b5ac31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174797271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3174797271
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1961219819
Short name T331
Test name
Test status
Simulation time 2533559111 ps
CPU time 10.34 seconds
Started Jul 20 05:55:38 PM PDT 24
Finished Jul 20 05:55:51 PM PDT 24
Peak memory 213672 kb
Host smart-25b9c5bb-2740-4ae7-995c-1ee723250b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961219819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
961219819
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2664726355
Short name T392
Test name
Test status
Simulation time 4001714379 ps
CPU time 6.08 seconds
Started Jul 20 05:55:23 PM PDT 24
Finished Jul 20 05:55:31 PM PDT 24
Peak memory 221704 kb
Host smart-6995b0b9-a9d4-4fe4-909a-95bdbc673848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664726355 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2664726355
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2347950096
Short name T306
Test name
Test status
Simulation time 157083557 ps
CPU time 2.14 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:36 PM PDT 24
Peak memory 213460 kb
Host smart-60c77af9-457f-45d4-bd15-b8e1c49dcb6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347950096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2347950096
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3234223020
Short name T351
Test name
Test status
Simulation time 26846497891 ps
CPU time 15.77 seconds
Started Jul 20 05:55:27 PM PDT 24
Finished Jul 20 05:55:45 PM PDT 24
Peak memory 205372 kb
Host smart-9c08dc7e-3099-4286-8bac-ad905297f8ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234223020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.3234223020
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3689809740
Short name T424
Test name
Test status
Simulation time 4620012365 ps
CPU time 4.51 seconds
Started Jul 20 05:55:19 PM PDT 24
Finished Jul 20 05:55:26 PM PDT 24
Peak memory 205260 kb
Host smart-3db523c3-67f3-4fef-b4dc-ee020b530371
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689809740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3689809740
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3052677323
Short name T315
Test name
Test status
Simulation time 889735340 ps
CPU time 3.1 seconds
Started Jul 20 05:55:24 PM PDT 24
Finished Jul 20 05:55:28 PM PDT 24
Peak memory 204968 kb
Host smart-a23c7cef-2b2c-4928-b30a-d4cd97c45a03
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052677323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3052677323
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3247036583
Short name T426
Test name
Test status
Simulation time 1095451679 ps
CPU time 4.63 seconds
Started Jul 20 05:55:33 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 205412 kb
Host smart-592b079a-088d-48f7-9860-7f93fc8d786e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247036583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3247036583
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3871513294
Short name T352
Test name
Test status
Simulation time 245707127 ps
CPU time 4.54 seconds
Started Jul 20 05:55:36 PM PDT 24
Finished Jul 20 05:55:44 PM PDT 24
Peak memory 213588 kb
Host smart-053ccc41-9439-4a25-afbe-7f665323776d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871513294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3871513294
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1090741908
Short name T415
Test name
Test status
Simulation time 3500623528 ps
CPU time 7.84 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 220564 kb
Host smart-f857493d-82f7-4856-bda6-f6da1279545d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090741908 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1090741908
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1835980503
Short name T425
Test name
Test status
Simulation time 112677169 ps
CPU time 2.58 seconds
Started Jul 20 05:55:32 PM PDT 24
Finished Jul 20 05:55:39 PM PDT 24
Peak memory 213556 kb
Host smart-dd2b89d7-fbd6-4ab4-a324-d771fb19df5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835980503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1835980503
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3400823415
Short name T317
Test name
Test status
Simulation time 17263457324 ps
CPU time 15.6 seconds
Started Jul 20 05:55:27 PM PDT 24
Finished Jul 20 05:55:44 PM PDT 24
Peak memory 205376 kb
Host smart-bd746e6d-3625-4b9c-9c70-0a78bec9c5ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400823415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.3400823415
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.202524741
Short name T288
Test name
Test status
Simulation time 5919907651 ps
CPU time 3.46 seconds
Started Jul 20 05:55:23 PM PDT 24
Finished Jul 20 05:55:28 PM PDT 24
Peak memory 205312 kb
Host smart-3746eff6-cad5-4c91-96ff-b7d2c3ab97bf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202524741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.202524741
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2368889389
Short name T348
Test name
Test status
Simulation time 290620071 ps
CPU time 0.82 seconds
Started Jul 20 05:55:32 PM PDT 24
Finished Jul 20 05:55:36 PM PDT 24
Peak memory 204976 kb
Host smart-6338b557-6ec1-4eaa-a7c5-16c780978777
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368889389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2368889389
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2996439258
Short name T87
Test name
Test status
Simulation time 347761904 ps
CPU time 3.75 seconds
Started Jul 20 05:55:36 PM PDT 24
Finished Jul 20 05:55:43 PM PDT 24
Peak memory 205364 kb
Host smart-d312bfd0-d074-4d60-8810-9c875f270ea9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996439258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2996439258
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.725183431
Short name T410
Test name
Test status
Simulation time 150810337 ps
CPU time 2.43 seconds
Started Jul 20 05:55:40 PM PDT 24
Finished Jul 20 05:55:46 PM PDT 24
Peak memory 213652 kb
Host smart-4beeeec6-2c90-4f8c-9f42-73539fd3401f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725183431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.725183431
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1654072942
Short name T380
Test name
Test status
Simulation time 1795522176 ps
CPU time 8.94 seconds
Started Jul 20 05:55:30 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 213572 kb
Host smart-f8db51ab-cfb7-4fbf-860a-7a5fd4f4d8ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654072942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
654072942
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3925189420
Short name T375
Test name
Test status
Simulation time 2280955804 ps
CPU time 7.34 seconds
Started Jul 20 05:55:25 PM PDT 24
Finished Jul 20 05:55:34 PM PDT 24
Peak memory 219724 kb
Host smart-02e176e3-f99d-44ef-94ec-7287201e259a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925189420 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3925189420
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3231800886
Short name T386
Test name
Test status
Simulation time 81457897 ps
CPU time 1.59 seconds
Started Jul 20 05:55:34 PM PDT 24
Finished Jul 20 05:55:39 PM PDT 24
Peak memory 213720 kb
Host smart-da1dfaaf-f0db-4c89-96b5-8c99aea1fe61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231800886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3231800886
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.231371640
Short name T404
Test name
Test status
Simulation time 25559753304 ps
CPU time 75.49 seconds
Started Jul 20 05:55:22 PM PDT 24
Finished Jul 20 05:56:39 PM PDT 24
Peak memory 205488 kb
Host smart-3c85a8ec-66df-497f-a99c-411f4f055987
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231371640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rv_dm_jtag_dmi_csr_bit_bash.231371640
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3908082555
Short name T430
Test name
Test status
Simulation time 4956313703 ps
CPU time 13.33 seconds
Started Jul 20 05:55:38 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 205388 kb
Host smart-7866f525-6f91-4c9b-91f1-c5cedf6310fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908082555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3908082555
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1300700103
Short name T336
Test name
Test status
Simulation time 189009177 ps
CPU time 1.17 seconds
Started Jul 20 05:55:23 PM PDT 24
Finished Jul 20 05:55:26 PM PDT 24
Peak memory 205012 kb
Host smart-b4b6eaf5-43d0-4598-9ab8-7cac3895d2cc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300700103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1300700103
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3143639214
Short name T366
Test name
Test status
Simulation time 188455609 ps
CPU time 3.54 seconds
Started Jul 20 05:55:35 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 205288 kb
Host smart-09a54655-3dc4-409d-9da6-9402e41265fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143639214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3143639214
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1975808240
Short name T408
Test name
Test status
Simulation time 1176526320 ps
CPU time 5.68 seconds
Started Jul 20 05:55:23 PM PDT 24
Finished Jul 20 05:55:30 PM PDT 24
Peak memory 213668 kb
Host smart-f7cd1c36-ee51-48bc-8019-4bdf7de9d896
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975808240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1975808240
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2251432968
Short name T346
Test name
Test status
Simulation time 743685012 ps
CPU time 3.89 seconds
Started Jul 20 05:55:25 PM PDT 24
Finished Jul 20 05:55:31 PM PDT 24
Peak memory 218368 kb
Host smart-2a9f5b2a-8ff0-415d-b746-c508394b551e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251432968 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2251432968
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2746967758
Short name T435
Test name
Test status
Simulation time 5949856549 ps
CPU time 16.64 seconds
Started Jul 20 05:55:23 PM PDT 24
Finished Jul 20 05:55:41 PM PDT 24
Peak memory 205384 kb
Host smart-b864ca8d-11b4-426e-a5e2-b9bfc5e21a76
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746967758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.2746967758
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1337323524
Short name T343
Test name
Test status
Simulation time 1975069094 ps
CPU time 3.39 seconds
Started Jul 20 05:55:22 PM PDT 24
Finished Jul 20 05:55:27 PM PDT 24
Peak memory 205156 kb
Host smart-2950ae30-b570-47fb-b6dc-ed1ba9d8f623
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337323524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1337323524
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.996923638
Short name T354
Test name
Test status
Simulation time 106952364 ps
CPU time 0.94 seconds
Started Jul 20 05:55:30 PM PDT 24
Finished Jul 20 05:55:34 PM PDT 24
Peak memory 205000 kb
Host smart-eb972e02-4c92-4108-aae2-2557a2b2e47f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996923638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.996923638
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1082940707
Short name T327
Test name
Test status
Simulation time 1416651746 ps
CPU time 4.24 seconds
Started Jul 20 05:55:27 PM PDT 24
Finished Jul 20 05:55:34 PM PDT 24
Peak memory 205412 kb
Host smart-d2991e09-c092-4328-a3f9-16107d82a96b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082940707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1082940707
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3044555806
Short name T437
Test name
Test status
Simulation time 305608106 ps
CPU time 3.52 seconds
Started Jul 20 05:55:22 PM PDT 24
Finished Jul 20 05:55:27 PM PDT 24
Peak memory 213696 kb
Host smart-1be8c1d1-b0db-4929-af54-c09142fde617
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044555806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3044555806
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.542269855
Short name T345
Test name
Test status
Simulation time 2585352030 ps
CPU time 13.9 seconds
Started Jul 20 05:55:26 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 213176 kb
Host smart-21466e21-2b33-4151-95fb-ce726c3b2f1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542269855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.542269855
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1563184676
Short name T428
Test name
Test status
Simulation time 3008349394 ps
CPU time 3.59 seconds
Started Jul 20 05:55:22 PM PDT 24
Finished Jul 20 05:55:27 PM PDT 24
Peak memory 213760 kb
Host smart-9dda7d9c-1409-45ee-9bca-d0a14bacfee4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563184676 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1563184676
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.327930386
Short name T403
Test name
Test status
Simulation time 49429280 ps
CPU time 2.13 seconds
Started Jul 20 05:55:30 PM PDT 24
Finished Jul 20 05:55:34 PM PDT 24
Peak memory 213600 kb
Host smart-788cc828-c181-4426-80ec-fb3ba68724ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327930386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.327930386
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1407281730
Short name T390
Test name
Test status
Simulation time 2518306983 ps
CPU time 4.75 seconds
Started Jul 20 05:55:39 PM PDT 24
Finished Jul 20 05:55:47 PM PDT 24
Peak memory 205308 kb
Host smart-bec857bf-256e-45de-9dd3-5620d51121e7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407281730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.1407281730
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.393439629
Short name T429
Test name
Test status
Simulation time 1854913066 ps
CPU time 2.59 seconds
Started Jul 20 05:55:37 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 205240 kb
Host smart-d89c0423-25f4-4767-be66-bb6729365d6a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393439629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.393439629
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2863284579
Short name T74
Test name
Test status
Simulation time 232480642 ps
CPU time 0.87 seconds
Started Jul 20 05:55:23 PM PDT 24
Finished Jul 20 05:55:25 PM PDT 24
Peak memory 204976 kb
Host smart-d6f1d242-7a2f-4475-9aab-d6f2906bba7e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863284579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2863284579
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2586904795
Short name T320
Test name
Test status
Simulation time 248982371 ps
CPU time 4.84 seconds
Started Jul 20 05:55:22 PM PDT 24
Finished Jul 20 05:55:29 PM PDT 24
Peak memory 213692 kb
Host smart-3b4cd143-aeeb-463a-aeb4-882b614fe09b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586904795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2586904795
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1894277333
Short name T158
Test name
Test status
Simulation time 2781837565 ps
CPU time 14.18 seconds
Started Jul 20 05:55:28 PM PDT 24
Finished Jul 20 05:55:44 PM PDT 24
Peak memory 213696 kb
Host smart-cb730da5-5b31-47e1-88c3-1ad7bba298dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894277333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
894277333
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2474023651
Short name T360
Test name
Test status
Simulation time 8132384420 ps
CPU time 5.64 seconds
Started Jul 20 05:55:20 PM PDT 24
Finished Jul 20 05:55:27 PM PDT 24
Peak memory 220440 kb
Host smart-dfb25ccf-e9ff-4477-a280-a24d0a6b3bc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474023651 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2474023651
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.125561558
Short name T394
Test name
Test status
Simulation time 764434699 ps
CPU time 1.75 seconds
Started Jul 20 05:55:25 PM PDT 24
Finished Jul 20 05:55:27 PM PDT 24
Peak memory 213524 kb
Host smart-78eab6ea-097a-4f59-9833-e6406f059b3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125561558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.125561558
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.941089143
Short name T341
Test name
Test status
Simulation time 2843333950 ps
CPU time 5.15 seconds
Started Jul 20 05:55:33 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 205268 kb
Host smart-27376dff-4527-4905-b56c-bb348080b34d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941089143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rv_dm_jtag_dmi_csr_bit_bash.941089143
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2083915158
Short name T436
Test name
Test status
Simulation time 15186630170 ps
CPU time 24.68 seconds
Started Jul 20 05:55:32 PM PDT 24
Finished Jul 20 05:56:01 PM PDT 24
Peak memory 205296 kb
Host smart-27bd3192-d977-4695-b6e8-17af81eebe72
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083915158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2083915158
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3792347748
Short name T416
Test name
Test status
Simulation time 1222650349 ps
CPU time 1.18 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:35 PM PDT 24
Peak memory 204896 kb
Host smart-48fe7a08-c69e-42be-bf14-8d602a468a6e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792347748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3792347748
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2828393572
Short name T98
Test name
Test status
Simulation time 615332351 ps
CPU time 6.86 seconds
Started Jul 20 05:55:23 PM PDT 24
Finished Jul 20 05:55:31 PM PDT 24
Peak memory 205360 kb
Host smart-549e5118-a2ca-47be-b391-b4ebdb2b81ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828393572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2828393572
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.4271819406
Short name T434
Test name
Test status
Simulation time 199543164 ps
CPU time 2.46 seconds
Started Jul 20 05:55:37 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 213712 kb
Host smart-d592ee42-ae5e-4a6a-89c4-a252467e3a97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271819406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.4271819406
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2326489094
Short name T150
Test name
Test status
Simulation time 2950785980 ps
CPU time 16.49 seconds
Started Jul 20 05:55:37 PM PDT 24
Finished Jul 20 05:55:56 PM PDT 24
Peak memory 213632 kb
Host smart-c659e0e6-1e68-449f-b3ff-3c5d93244917
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326489094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
326489094
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.472171535
Short name T81
Test name
Test status
Simulation time 3739435376 ps
CPU time 6.22 seconds
Started Jul 20 05:55:23 PM PDT 24
Finished Jul 20 05:55:31 PM PDT 24
Peak memory 221396 kb
Host smart-8e62273b-591b-4af9-96aa-1413a93c485f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472171535 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.472171535
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3734949692
Short name T84
Test name
Test status
Simulation time 219738236 ps
CPU time 1.56 seconds
Started Jul 20 05:55:22 PM PDT 24
Finished Jul 20 05:55:25 PM PDT 24
Peak memory 213444 kb
Host smart-53f678ac-d3a6-4991-b3d5-9defe90811d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734949692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3734949692
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3120218764
Short name T308
Test name
Test status
Simulation time 9500336812 ps
CPU time 3.09 seconds
Started Jul 20 05:55:23 PM PDT 24
Finished Jul 20 05:55:28 PM PDT 24
Peak memory 205296 kb
Host smart-ab927c24-675b-4f36-8af5-2e0eb73faa9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120218764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.3120218764
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4000905167
Short name T406
Test name
Test status
Simulation time 1176284209 ps
CPU time 1.88 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:36 PM PDT 24
Peak memory 205196 kb
Host smart-1589c9b9-a92c-4435-bf7d-84d3a8a96c4b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000905167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
4000905167
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1513168303
Short name T76
Test name
Test status
Simulation time 121083109 ps
CPU time 1.01 seconds
Started Jul 20 05:55:32 PM PDT 24
Finished Jul 20 05:55:37 PM PDT 24
Peak memory 204988 kb
Host smart-f2993f0e-1a79-4c49-bfcf-3f2c47ae063c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513168303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1513168303
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4135928768
Short name T402
Test name
Test status
Simulation time 971260279 ps
CPU time 4.06 seconds
Started Jul 20 05:55:25 PM PDT 24
Finished Jul 20 05:55:30 PM PDT 24
Peak memory 205320 kb
Host smart-35e4d32e-de39-4b1b-bbec-d9d25931f23f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135928768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.4135928768
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3387113911
Short name T356
Test name
Test status
Simulation time 197033545 ps
CPU time 2.83 seconds
Started Jul 20 05:55:37 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 213620 kb
Host smart-2625afa5-7fa0-49a5-b4aa-38b6b45bd81b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387113911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3387113911
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.649532796
Short name T155
Test name
Test status
Simulation time 3628811658 ps
CPU time 23.05 seconds
Started Jul 20 05:55:23 PM PDT 24
Finished Jul 20 05:55:47 PM PDT 24
Peak memory 213644 kb
Host smart-6538dfcd-d068-4bc0-abbe-9ae61bd8fbdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649532796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.649532796
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3526628460
Short name T423
Test name
Test status
Simulation time 2381964001 ps
CPU time 27.23 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 05:55:33 PM PDT 24
Peak memory 205464 kb
Host smart-ccf54465-e27f-4ac0-926e-cfcb55c6db5b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526628460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3526628460
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2540723988
Short name T114
Test name
Test status
Simulation time 20498424094 ps
CPU time 70.89 seconds
Started Jul 20 05:55:05 PM PDT 24
Finished Jul 20 05:56:18 PM PDT 24
Peak memory 205452 kb
Host smart-cfcacbc0-dec4-4026-a0a5-f15709f803c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540723988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2540723988
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.189112675
Short name T401
Test name
Test status
Simulation time 108863170 ps
CPU time 2.4 seconds
Started Jul 20 05:55:08 PM PDT 24
Finished Jul 20 05:55:12 PM PDT 24
Peak memory 213584 kb
Host smart-28eafeb1-9e28-45bc-af6d-91e84463864a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189112675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.189112675
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.784375646
Short name T328
Test name
Test status
Simulation time 1483756239 ps
CPU time 4.14 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 05:55:09 PM PDT 24
Peak memory 221712 kb
Host smart-df78adc1-2016-4e91-af3e-db0e6d31664f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784375646 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.784375646
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2014273878
Short name T107
Test name
Test status
Simulation time 139895096 ps
CPU time 2.25 seconds
Started Jul 20 05:55:07 PM PDT 24
Finished Jul 20 05:55:11 PM PDT 24
Peak memory 213296 kb
Host smart-6bbce42c-85a6-475a-9249-39aefc754c34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014273878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2014273878
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1441084218
Short name T350
Test name
Test status
Simulation time 220818669809 ps
CPU time 588.75 seconds
Started Jul 20 05:55:07 PM PDT 24
Finished Jul 20 06:04:58 PM PDT 24
Peak memory 210944 kb
Host smart-05f7a2a0-98f8-4167-9450-72488cda74e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441084218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1441084218
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2938848855
Short name T379
Test name
Test status
Simulation time 55932404663 ps
CPU time 140.64 seconds
Started Jul 20 05:55:08 PM PDT 24
Finished Jul 20 05:57:30 PM PDT 24
Peak memory 205216 kb
Host smart-ebabbe41-390a-466c-bd6c-097afbbc9983
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938848855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.2938848855
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4262940912
Short name T95
Test name
Test status
Simulation time 7488196953 ps
CPU time 5.41 seconds
Started Jul 20 05:55:09 PM PDT 24
Finished Jul 20 05:55:16 PM PDT 24
Peak memory 205420 kb
Host smart-dea41767-1f01-4e95-8762-58cd502483c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262940912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.4262940912
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3102443534
Short name T385
Test name
Test status
Simulation time 2180685360 ps
CPU time 3.97 seconds
Started Jul 20 05:55:05 PM PDT 24
Finished Jul 20 05:55:11 PM PDT 24
Peak memory 205240 kb
Host smart-92ac4ee6-a570-4808-a0df-8cadfc14421b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102443534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
102443534
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2773973401
Short name T358
Test name
Test status
Simulation time 402464382 ps
CPU time 1.01 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 05:55:06 PM PDT 24
Peak memory 204936 kb
Host smart-885a966f-6ae8-428d-8b1b-3ed62e2afd85
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773973401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2773973401
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.36337160
Short name T398
Test name
Test status
Simulation time 18487950150 ps
CPU time 47.17 seconds
Started Jul 20 05:55:06 PM PDT 24
Finished Jul 20 05:55:55 PM PDT 24
Peak memory 205312 kb
Host smart-8950c83d-3e6d-41a1-bd94-2eca34cd601d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36337160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_
bit_bash.36337160
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3979957058
Short name T431
Test name
Test status
Simulation time 363130331 ps
CPU time 1.67 seconds
Started Jul 20 05:55:10 PM PDT 24
Finished Jul 20 05:55:12 PM PDT 24
Peak memory 205040 kb
Host smart-460e362a-ca02-4c14-a9c9-417ee39852ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979957058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3979957058
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2814582537
Short name T297
Test name
Test status
Simulation time 621018754 ps
CPU time 2.42 seconds
Started Jul 20 05:55:29 PM PDT 24
Finished Jul 20 05:55:32 PM PDT 24
Peak memory 204976 kb
Host smart-ba311ed9-2bb2-46c9-8fca-763a95b7abe0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814582537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
814582537
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1088395606
Short name T286
Test name
Test status
Simulation time 140968241 ps
CPU time 0.99 seconds
Started Jul 20 05:55:09 PM PDT 24
Finished Jul 20 05:55:11 PM PDT 24
Peak memory 205004 kb
Host smart-56b384a0-3c57-4ecb-a171-401917817438
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088395606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1088395606
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4210932921
Short name T295
Test name
Test status
Simulation time 83103250 ps
CPU time 0.72 seconds
Started Jul 20 05:55:05 PM PDT 24
Finished Jul 20 05:55:08 PM PDT 24
Peak memory 204976 kb
Host smart-1b2933d0-ce64-4b9c-be97-ff323cc685cc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210932921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.4210932921
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1514113845
Short name T372
Test name
Test status
Simulation time 335184904 ps
CPU time 4.75 seconds
Started Jul 20 05:55:06 PM PDT 24
Finished Jul 20 05:55:13 PM PDT 24
Peak memory 205336 kb
Host smart-0395b7d9-9925-43c4-939c-278d234ffd13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514113845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1514113845
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3232631485
Short name T72
Test name
Test status
Simulation time 19574853716 ps
CPU time 34.3 seconds
Started Jul 20 05:55:05 PM PDT 24
Finished Jul 20 05:55:41 PM PDT 24
Peak memory 213712 kb
Host smart-459310db-0ca8-4aed-a7ec-23a2523ae972
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232631485 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3232631485
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3628538456
Short name T399
Test name
Test status
Simulation time 180281443 ps
CPU time 2.11 seconds
Started Jul 20 05:55:28 PM PDT 24
Finished Jul 20 05:55:32 PM PDT 24
Peak memory 213628 kb
Host smart-eef2bb63-67a4-4e27-8de9-793c7f39432a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628538456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3628538456
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1710625970
Short name T397
Test name
Test status
Simulation time 4348780531 ps
CPU time 34.17 seconds
Started Jul 20 05:55:09 PM PDT 24
Finished Jul 20 05:55:44 PM PDT 24
Peak memory 205476 kb
Host smart-6bb82b90-11f0-4d03-b447-f29f83aa1f2c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710625970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1710625970
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1998126358
Short name T411
Test name
Test status
Simulation time 14173599976 ps
CPU time 30.02 seconds
Started Jul 20 05:55:36 PM PDT 24
Finished Jul 20 05:56:09 PM PDT 24
Peak memory 213672 kb
Host smart-2cecd13c-3441-4eba-a858-7b63abb0dea7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998126358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1998126358
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1991900394
Short name T102
Test name
Test status
Simulation time 240150418 ps
CPU time 2.51 seconds
Started Jul 20 05:55:12 PM PDT 24
Finished Jul 20 05:55:15 PM PDT 24
Peak memory 213556 kb
Host smart-6c983ddd-69c7-4e7b-a689-5148da2bb615
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991900394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1991900394
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1812129474
Short name T80
Test name
Test status
Simulation time 128811385 ps
CPU time 2.46 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 05:55:08 PM PDT 24
Peak memory 217868 kb
Host smart-c0f24e3b-be73-4e43-a065-d9e842c2cc2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812129474 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1812129474
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2549972437
Short name T108
Test name
Test status
Simulation time 420070035 ps
CPU time 2.47 seconds
Started Jul 20 05:55:26 PM PDT 24
Finished Jul 20 05:55:31 PM PDT 24
Peak memory 213472 kb
Host smart-52b9b705-c658-4ea0-bfb1-4a95524b6c2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549972437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2549972437
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2403626824
Short name T381
Test name
Test status
Simulation time 238151023779 ps
CPU time 551.45 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 06:04:18 PM PDT 24
Peak memory 212404 kb
Host smart-5df1e653-c5e2-4d7b-810e-d5347820d5d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403626824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2403626824
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2185584898
Short name T373
Test name
Test status
Simulation time 52306803656 ps
CPU time 74.8 seconds
Started Jul 20 05:55:06 PM PDT 24
Finished Jul 20 05:56:23 PM PDT 24
Peak memory 205320 kb
Host smart-e4794703-4c34-4555-9602-ab8470bbc316
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185584898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.2185584898
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.152164547
Short name T93
Test name
Test status
Simulation time 4502403778 ps
CPU time 3.44 seconds
Started Jul 20 05:55:08 PM PDT 24
Finished Jul 20 05:55:13 PM PDT 24
Peak memory 205364 kb
Host smart-294147b7-8474-4fdf-b043-489d678107a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152164547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.152164547
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2738513832
Short name T313
Test name
Test status
Simulation time 969526335 ps
CPU time 1.54 seconds
Started Jul 20 05:55:30 PM PDT 24
Finished Jul 20 05:55:35 PM PDT 24
Peak memory 205092 kb
Host smart-fef9c404-974f-462a-bf2c-bb97e0fd5968
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738513832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
738513832
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.945751458
Short name T75
Test name
Test status
Simulation time 1173718268 ps
CPU time 1.69 seconds
Started Jul 20 05:55:07 PM PDT 24
Finished Jul 20 05:55:10 PM PDT 24
Peak memory 205020 kb
Host smart-b5c4c4ae-80e7-44da-b2f8-b71df6ff2457
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945751458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.945751458
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.273604411
Short name T302
Test name
Test status
Simulation time 7737485815 ps
CPU time 7.08 seconds
Started Jul 20 05:55:05 PM PDT 24
Finished Jul 20 05:55:14 PM PDT 24
Peak memory 205316 kb
Host smart-f3ce7d00-aa85-449a-b703-27895924e54d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273604411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.273604411
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2028847480
Short name T418
Test name
Test status
Simulation time 357524262 ps
CPU time 0.92 seconds
Started Jul 20 05:55:05 PM PDT 24
Finished Jul 20 05:55:08 PM PDT 24
Peak memory 205052 kb
Host smart-f87f5347-255f-4c46-baf8-a6c79f863f0c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028847480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2028847480
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1157169897
Short name T378
Test name
Test status
Simulation time 332296400 ps
CPU time 1.68 seconds
Started Jul 20 05:55:05 PM PDT 24
Finished Jul 20 05:55:09 PM PDT 24
Peak memory 204944 kb
Host smart-c0f50888-8919-4c6e-8be4-ba4c9b902472
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157169897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
157169897
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3461678161
Short name T374
Test name
Test status
Simulation time 39643394 ps
CPU time 0.7 seconds
Started Jul 20 05:55:15 PM PDT 24
Finished Jul 20 05:55:16 PM PDT 24
Peak memory 204908 kb
Host smart-14d2a500-7282-4706-b528-77abcac0c713
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461678161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3461678161
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3141783879
Short name T369
Test name
Test status
Simulation time 61222006 ps
CPU time 0.7 seconds
Started Jul 20 05:55:06 PM PDT 24
Finished Jul 20 05:55:08 PM PDT 24
Peak memory 204936 kb
Host smart-6249899f-7770-4a8d-ba0e-9bf21705af75
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141783879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3141783879
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.826430807
Short name T395
Test name
Test status
Simulation time 98731583 ps
CPU time 3.5 seconds
Started Jul 20 05:55:29 PM PDT 24
Finished Jul 20 05:55:35 PM PDT 24
Peak memory 205412 kb
Host smart-6431cca7-d50d-482b-8d9e-05b2f903310e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826430807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.826430807
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2296046464
Short name T159
Test name
Test status
Simulation time 64788576637 ps
CPU time 81.07 seconds
Started Jul 20 05:55:06 PM PDT 24
Finished Jul 20 05:56:29 PM PDT 24
Peak memory 224936 kb
Host smart-4bedc6ef-da23-40b9-95bf-51eccfa24568
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296046464 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2296046464
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2666112380
Short name T361
Test name
Test status
Simulation time 172424362 ps
CPU time 3.1 seconds
Started Jul 20 05:55:08 PM PDT 24
Finished Jul 20 05:55:23 PM PDT 24
Peak memory 213648 kb
Host smart-0b8b2342-efe0-44d2-87f1-814c81a98152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666112380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2666112380
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3582258356
Short name T149
Test name
Test status
Simulation time 4398245616 ps
CPU time 13.62 seconds
Started Jul 20 05:55:07 PM PDT 24
Finished Jul 20 05:55:22 PM PDT 24
Peak memory 213752 kb
Host smart-02ddfe5a-943d-4a28-8a3e-c19cbc50f396
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582258356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3582258356
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3406690010
Short name T422
Test name
Test status
Simulation time 5636063847 ps
CPU time 77.19 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:56:52 PM PDT 24
Peak memory 219072 kb
Host smart-f38dc72b-32c4-4366-b6a5-83a2898a4ad6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406690010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3406690010
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1176148887
Short name T382
Test name
Test status
Simulation time 2542367230 ps
CPU time 27.7 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 05:55:34 PM PDT 24
Peak memory 205464 kb
Host smart-66a4b721-453a-4158-b5b4-a861e0484370
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176148887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1176148887
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2845574546
Short name T91
Test name
Test status
Simulation time 306721105 ps
CPU time 2.87 seconds
Started Jul 20 05:55:26 PM PDT 24
Finished Jul 20 05:55:31 PM PDT 24
Peak memory 213556 kb
Host smart-e9e9982b-8ebe-4130-97f6-c4d337e7c284
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845574546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2845574546
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.4084271512
Short name T60
Test name
Test status
Simulation time 1239814686 ps
CPU time 3 seconds
Started Jul 20 05:55:28 PM PDT 24
Finished Jul 20 05:55:33 PM PDT 24
Peak memory 217852 kb
Host smart-6735aff0-6b23-4921-a6c5-b4b8093b4adc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084271512 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.4084271512
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2084068235
Short name T371
Test name
Test status
Simulation time 181372110 ps
CPU time 2.38 seconds
Started Jul 20 05:55:07 PM PDT 24
Finished Jul 20 05:55:12 PM PDT 24
Peak memory 213564 kb
Host smart-1fa82719-ddc4-4709-8c2a-4ce287f4eafd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084068235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2084068235
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2238431061
Short name T388
Test name
Test status
Simulation time 190072099912 ps
CPU time 88.25 seconds
Started Jul 20 05:55:03 PM PDT 24
Finished Jul 20 05:56:33 PM PDT 24
Peak memory 209016 kb
Host smart-1331bab7-f807-4b77-a68f-432e32773ac1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238431061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2238431061
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.771327397
Short name T365
Test name
Test status
Simulation time 27565030665 ps
CPU time 70.41 seconds
Started Jul 20 05:55:30 PM PDT 24
Finished Jul 20 05:56:42 PM PDT 24
Peak memory 205224 kb
Host smart-956da01d-f28d-4d9e-8660-70096b3d10f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771327397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.771327397
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1398070716
Short name T92
Test name
Test status
Simulation time 1879729333 ps
CPU time 2.02 seconds
Started Jul 20 05:55:01 PM PDT 24
Finished Jul 20 05:55:05 PM PDT 24
Peak memory 205244 kb
Host smart-31d70d27-38a6-49d8-bb71-713e9a33d1c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398070716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1398070716
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2964693911
Short name T367
Test name
Test status
Simulation time 5613924188 ps
CPU time 10.17 seconds
Started Jul 20 05:55:08 PM PDT 24
Finished Jul 20 05:55:20 PM PDT 24
Peak memory 205352 kb
Host smart-e66c5a7c-26f7-4b4d-8e65-31fc3c440c24
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964693911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
964693911
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2340988569
Short name T335
Test name
Test status
Simulation time 1114777134 ps
CPU time 3.39 seconds
Started Jul 20 05:55:07 PM PDT 24
Finished Jul 20 05:55:12 PM PDT 24
Peak memory 204976 kb
Host smart-a090df05-9304-4b98-8a65-16ee43f130cc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340988569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2340988569
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.462876054
Short name T412
Test name
Test status
Simulation time 9898474951 ps
CPU time 8.59 seconds
Started Jul 20 05:55:08 PM PDT 24
Finished Jul 20 05:55:18 PM PDT 24
Peak memory 205288 kb
Host smart-936d36de-466f-40a5-8c6b-8d32f08f0a2f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462876054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.462876054
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.147073794
Short name T304
Test name
Test status
Simulation time 778536015 ps
CPU time 1.58 seconds
Started Jul 20 05:55:09 PM PDT 24
Finished Jul 20 05:55:12 PM PDT 24
Peak memory 205040 kb
Host smart-c33cefd7-b319-4c4b-b8f4-c3217b0f6efe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147073794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.147073794
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.811761582
Short name T353
Test name
Test status
Simulation time 849161418 ps
CPU time 2.94 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 05:55:08 PM PDT 24
Peak memory 204880 kb
Host smart-51ef8b5d-4a18-441e-920e-93bcd968476d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811761582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.811761582
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1402477340
Short name T314
Test name
Test status
Simulation time 131675722 ps
CPU time 0.78 seconds
Started Jul 20 05:55:07 PM PDT 24
Finished Jul 20 05:55:09 PM PDT 24
Peak memory 205020 kb
Host smart-642e1f40-58d2-4416-8332-92e1f81bfae6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402477340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1402477340
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.4127470381
Short name T414
Test name
Test status
Simulation time 38785146 ps
CPU time 0.74 seconds
Started Jul 20 05:55:35 PM PDT 24
Finished Jul 20 05:55:39 PM PDT 24
Peak memory 204984 kb
Host smart-80e656fc-be71-4102-8796-05ddb516e7ab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127470381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.4127470381
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2079175298
Short name T363
Test name
Test status
Simulation time 339123546 ps
CPU time 4.18 seconds
Started Jul 20 05:55:35 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 205340 kb
Host smart-71d733a7-1d58-4fb8-9cc2-33f39c2afe80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079175298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2079175298
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1181018246
Short name T387
Test name
Test status
Simulation time 80706396 ps
CPU time 3.32 seconds
Started Jul 20 05:55:29 PM PDT 24
Finished Jul 20 05:55:34 PM PDT 24
Peak memory 213624 kb
Host smart-c8f333b1-cd6f-4f1f-9964-99149fc558da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181018246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1181018246
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.342872901
Short name T347
Test name
Test status
Simulation time 4536549136 ps
CPU time 6.51 seconds
Started Jul 20 05:55:26 PM PDT 24
Finished Jul 20 05:55:34 PM PDT 24
Peak memory 221932 kb
Host smart-1a484148-582d-4373-9575-4fd7d7cc1ffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342872901 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.342872901
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2349310976
Short name T303
Test name
Test status
Simulation time 65150073 ps
CPU time 1.53 seconds
Started Jul 20 05:55:25 PM PDT 24
Finished Jul 20 05:55:29 PM PDT 24
Peak memory 213572 kb
Host smart-4cdd1dcb-6c43-41be-bf7d-da1de86d2629
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349310976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2349310976
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1684669068
Short name T349
Test name
Test status
Simulation time 2473302749 ps
CPU time 2.21 seconds
Started Jul 20 05:55:15 PM PDT 24
Finished Jul 20 05:55:18 PM PDT 24
Peak memory 205268 kb
Host smart-474e32e3-e28c-4296-b7fa-5ad080cda589
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684669068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.1684669068
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1504425202
Short name T287
Test name
Test status
Simulation time 1589758012 ps
CPU time 5.57 seconds
Started Jul 20 05:55:04 PM PDT 24
Finished Jul 20 05:55:11 PM PDT 24
Peak memory 205116 kb
Host smart-cf3a7090-a87b-48ee-b9ba-83ccdd4aa502
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504425202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
504425202
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1348282280
Short name T310
Test name
Test status
Simulation time 398140033 ps
CPU time 1.78 seconds
Started Jul 20 05:55:15 PM PDT 24
Finished Jul 20 05:55:18 PM PDT 24
Peak memory 204904 kb
Host smart-57e25a37-d716-4082-bb5e-8a329e20f233
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348282280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
348282280
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.4130544206
Short name T383
Test name
Test status
Simulation time 91274034 ps
CPU time 3.53 seconds
Started Jul 20 05:55:17 PM PDT 24
Finished Jul 20 05:55:23 PM PDT 24
Peak memory 205432 kb
Host smart-6eb97a13-9771-43c3-b4a3-87afcf3a0dd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130544206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.4130544206
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2316130010
Short name T294
Test name
Test status
Simulation time 63370437535 ps
CPU time 56.08 seconds
Started Jul 20 05:55:17 PM PDT 24
Finished Jul 20 05:56:15 PM PDT 24
Peak memory 221452 kb
Host smart-0fb214fe-59da-4e41-85de-7da253205f21
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316130010 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2316130010
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2090349019
Short name T292
Test name
Test status
Simulation time 256969815 ps
CPU time 3.99 seconds
Started Jul 20 05:55:27 PM PDT 24
Finished Jul 20 05:55:33 PM PDT 24
Peak memory 213676 kb
Host smart-a4a58f26-0d45-4ac3-9684-216a35169a3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090349019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2090349019
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1077258063
Short name T152
Test name
Test status
Simulation time 4142278435 ps
CPU time 24.89 seconds
Started Jul 20 05:55:15 PM PDT 24
Finished Jul 20 05:55:41 PM PDT 24
Peak memory 213588 kb
Host smart-9b982e07-5aa9-48cc-ba57-0784957a9315
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077258063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1077258063
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2515991006
Short name T322
Test name
Test status
Simulation time 4773113139 ps
CPU time 7.22 seconds
Started Jul 20 05:55:29 PM PDT 24
Finished Jul 20 05:55:37 PM PDT 24
Peak memory 220484 kb
Host smart-ecf374cb-1608-4e24-87fb-8741fd314cf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515991006 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2515991006
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1198467820
Short name T111
Test name
Test status
Simulation time 64458360 ps
CPU time 1.44 seconds
Started Jul 20 05:55:19 PM PDT 24
Finished Jul 20 05:55:22 PM PDT 24
Peak memory 213516 kb
Host smart-39cc73ac-cb6d-4980-a372-f92cb4dd54ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198467820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1198467820
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1721122416
Short name T344
Test name
Test status
Simulation time 5469222206 ps
CPU time 9.81 seconds
Started Jul 20 05:55:15 PM PDT 24
Finished Jul 20 05:55:26 PM PDT 24
Peak memory 205304 kb
Host smart-a7b8e8c0-6ae9-4cca-803c-bd4b1e9bdd55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721122416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.1721122416
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1086303202
Short name T299
Test name
Test status
Simulation time 6611895854 ps
CPU time 10.23 seconds
Started Jul 20 05:55:15 PM PDT 24
Finished Jul 20 05:55:26 PM PDT 24
Peak memory 205240 kb
Host smart-ce8efd33-21a6-41ba-a9d4-3b81eeef07b5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086303202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
086303202
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.137374685
Short name T334
Test name
Test status
Simulation time 1205543610 ps
CPU time 1.61 seconds
Started Jul 20 05:55:20 PM PDT 24
Finished Jul 20 05:55:23 PM PDT 24
Peak memory 204972 kb
Host smart-2903f9ba-e543-4ebd-a843-8fb3117383a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137374685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.137374685
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3401906755
Short name T101
Test name
Test status
Simulation time 1178453446 ps
CPU time 7.72 seconds
Started Jul 20 05:55:25 PM PDT 24
Finished Jul 20 05:55:34 PM PDT 24
Peak memory 205304 kb
Host smart-8c37ff99-2331-4640-b37b-de80e32c2b1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401906755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3401906755
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1789104341
Short name T300
Test name
Test status
Simulation time 47687800599 ps
CPU time 135.13 seconds
Started Jul 20 05:55:13 PM PDT 24
Finished Jul 20 05:57:29 PM PDT 24
Peak memory 221980 kb
Host smart-00268def-5be2-41a5-95b5-727a935f01a3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789104341 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.1789104341
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1289855660
Short name T377
Test name
Test status
Simulation time 321887485 ps
CPU time 3.31 seconds
Started Jul 20 05:55:22 PM PDT 24
Finished Jul 20 05:55:26 PM PDT 24
Peak memory 213628 kb
Host smart-3099c4fb-0cc1-4acc-acad-215451156af9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289855660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1289855660
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3582205798
Short name T154
Test name
Test status
Simulation time 1995659249 ps
CPU time 11.65 seconds
Started Jul 20 05:55:15 PM PDT 24
Finished Jul 20 05:55:28 PM PDT 24
Peak memory 213632 kb
Host smart-9e80f738-3180-4c00-95bb-985ca5ad4ed3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582205798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3582205798
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.4164490269
Short name T413
Test name
Test status
Simulation time 1499636651 ps
CPU time 3.14 seconds
Started Jul 20 05:55:12 PM PDT 24
Finished Jul 20 05:55:16 PM PDT 24
Peak memory 222008 kb
Host smart-caa0f51b-301e-47fc-b7df-5cd0566fd568
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164490269 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.4164490269
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4141888336
Short name T405
Test name
Test status
Simulation time 298322618 ps
CPU time 2.14 seconds
Started Jul 20 05:55:18 PM PDT 24
Finished Jul 20 05:55:22 PM PDT 24
Peak memory 213524 kb
Host smart-c553277c-509c-45d8-80c5-0fff4b72e55f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141888336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.4141888336
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3499206400
Short name T316
Test name
Test status
Simulation time 18463532795 ps
CPU time 53.08 seconds
Started Jul 20 05:55:17 PM PDT 24
Finished Jul 20 05:56:12 PM PDT 24
Peak memory 205340 kb
Host smart-9a0417a5-48bc-4a0e-b758-b60caad8f153
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499206400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.3499206400
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1183503569
Short name T326
Test name
Test status
Simulation time 2984067437 ps
CPU time 3.39 seconds
Started Jul 20 05:55:26 PM PDT 24
Finished Jul 20 05:55:31 PM PDT 24
Peak memory 205308 kb
Host smart-828734fe-2fbf-494d-86dc-73f6b19301dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183503569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
183503569
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.507847772
Short name T339
Test name
Test status
Simulation time 1173539633 ps
CPU time 4.01 seconds
Started Jul 20 05:55:17 PM PDT 24
Finished Jul 20 05:55:22 PM PDT 24
Peak memory 204940 kb
Host smart-9df839b0-39a7-4918-967e-251274c8104b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507847772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.507847772
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2741852026
Short name T438
Test name
Test status
Simulation time 398273587 ps
CPU time 4.53 seconds
Started Jul 20 05:55:26 PM PDT 24
Finished Jul 20 05:55:32 PM PDT 24
Peak memory 205388 kb
Host smart-a7a36d8b-0c6a-4177-80da-d81b6a3a0204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741852026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2741852026
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2168157962
Short name T117
Test name
Test status
Simulation time 1315939803 ps
CPU time 5.34 seconds
Started Jul 20 05:55:14 PM PDT 24
Finished Jul 20 05:55:20 PM PDT 24
Peak memory 213692 kb
Host smart-39b8cd92-937f-485d-a26e-18d771f1247d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168157962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2168157962
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1523892641
Short name T156
Test name
Test status
Simulation time 4083401630 ps
CPU time 18.04 seconds
Started Jul 20 05:55:16 PM PDT 24
Finished Jul 20 05:55:35 PM PDT 24
Peak memory 213672 kb
Host smart-7b804d4a-0c1e-45a5-a470-c1324d66630b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523892641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1523892641
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2425914305
Short name T59
Test name
Test status
Simulation time 387014311 ps
CPU time 4.06 seconds
Started Jul 20 05:55:17 PM PDT 24
Finished Jul 20 05:55:22 PM PDT 24
Peak memory 221816 kb
Host smart-f1728538-cc3d-4387-8a9c-f57e8da9866f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425914305 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2425914305
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1528222062
Short name T400
Test name
Test status
Simulation time 185936500 ps
CPU time 2.27 seconds
Started Jul 20 05:55:17 PM PDT 24
Finished Jul 20 05:55:20 PM PDT 24
Peak memory 213548 kb
Host smart-9e996c53-63b7-4fb8-a9df-40fb9ccb1e44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528222062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1528222062
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3931680260
Short name T432
Test name
Test status
Simulation time 2018673935 ps
CPU time 2.43 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:36 PM PDT 24
Peak memory 205224 kb
Host smart-d0d72349-b5a3-40a4-9fa4-a8df4055f2cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931680260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.3931680260
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1310263891
Short name T293
Test name
Test status
Simulation time 2956008268 ps
CPU time 9.28 seconds
Started Jul 20 05:55:19 PM PDT 24
Finished Jul 20 05:55:30 PM PDT 24
Peak memory 205252 kb
Host smart-3fd6909f-c57c-431a-811b-4f301de0c155
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310263891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
310263891
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3072089576
Short name T433
Test name
Test status
Simulation time 234669838 ps
CPU time 1.28 seconds
Started Jul 20 05:55:18 PM PDT 24
Finished Jul 20 05:55:21 PM PDT 24
Peak memory 204972 kb
Host smart-9a2a98c3-4673-4883-86d3-d76b24d9fceb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072089576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
072089576
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4183086651
Short name T63
Test name
Test status
Simulation time 1233981876 ps
CPU time 8.21 seconds
Started Jul 20 05:55:12 PM PDT 24
Finished Jul 20 05:55:21 PM PDT 24
Peak memory 205368 kb
Host smart-b6a60855-5173-4bce-95da-9e84afa41600
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183086651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.4183086651
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.4001082575
Short name T384
Test name
Test status
Simulation time 339734677 ps
CPU time 4.55 seconds
Started Jul 20 05:55:16 PM PDT 24
Finished Jul 20 05:55:22 PM PDT 24
Peak memory 213616 kb
Host smart-d65a1561-dcf7-4e9a-b2d8-278bba733dcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001082575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.4001082575
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2591681542
Short name T118
Test name
Test status
Simulation time 1123604032 ps
CPU time 17.59 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:52 PM PDT 24
Peak memory 213592 kb
Host smart-1c866d5e-6cb1-4ca0-b448-e8df8db86931
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591681542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2591681542
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4143423283
Short name T319
Test name
Test status
Simulation time 705332185 ps
CPU time 2.76 seconds
Started Jul 20 05:55:18 PM PDT 24
Finished Jul 20 05:55:23 PM PDT 24
Peak memory 217796 kb
Host smart-0d694d33-e603-4ab1-a196-d7c56d6bd826
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143423283 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.4143423283
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2381239065
Short name T89
Test name
Test status
Simulation time 132022373 ps
CPU time 1.57 seconds
Started Jul 20 05:55:17 PM PDT 24
Finished Jul 20 05:55:20 PM PDT 24
Peak memory 213500 kb
Host smart-04ef1493-6808-4879-a967-eeab1e314c10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381239065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2381239065
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2307251965
Short name T342
Test name
Test status
Simulation time 92391692 ps
CPU time 0.8 seconds
Started Jul 20 05:55:15 PM PDT 24
Finished Jul 20 05:55:17 PM PDT 24
Peak memory 204872 kb
Host smart-b3c239ef-4372-4aa1-b67c-ea2822b87428
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307251965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2307251965
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1665184874
Short name T290
Test name
Test status
Simulation time 2616712385 ps
CPU time 2.95 seconds
Started Jul 20 05:55:17 PM PDT 24
Finished Jul 20 05:55:21 PM PDT 24
Peak memory 205192 kb
Host smart-cec754b5-65bb-485c-9afa-44bb738335e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665184874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
665184874
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2235938121
Short name T364
Test name
Test status
Simulation time 578559474 ps
CPU time 2.13 seconds
Started Jul 20 05:55:32 PM PDT 24
Finished Jul 20 05:55:38 PM PDT 24
Peak memory 204904 kb
Host smart-8630167b-d592-4326-a595-4d8806f09171
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235938121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
235938121
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4143200009
Short name T112
Test name
Test status
Simulation time 873190687 ps
CPU time 7.74 seconds
Started Jul 20 05:55:17 PM PDT 24
Finished Jul 20 05:55:26 PM PDT 24
Peak memory 205412 kb
Host smart-769d1eca-ab94-4b51-81f3-21580af987b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143200009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.4143200009
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2687116795
Short name T146
Test name
Test status
Simulation time 54441230842 ps
CPU time 34.5 seconds
Started Jul 20 05:55:16 PM PDT 24
Finished Jul 20 05:55:51 PM PDT 24
Peak memory 222132 kb
Host smart-9f068e0c-039a-4445-8367-d910831ec268
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687116795 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2687116795
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1093058919
Short name T301
Test name
Test status
Simulation time 235027160 ps
CPU time 3.76 seconds
Started Jul 20 05:55:15 PM PDT 24
Finished Jul 20 05:55:19 PM PDT 24
Peak memory 213720 kb
Host smart-8c92fde7-0086-4b38-994d-a2923542bb57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093058919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1093058919
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.4266452981
Short name T202
Test name
Test status
Simulation time 54430765 ps
CPU time 0.77 seconds
Started Jul 20 06:47:23 PM PDT 24
Finished Jul 20 06:47:25 PM PDT 24
Peak memory 204992 kb
Host smart-0b863383-5b0d-47a1-bad8-d8954d1ff888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266452981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.4266452981
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1820814035
Short name T270
Test name
Test status
Simulation time 3858055899 ps
CPU time 3.93 seconds
Started Jul 20 06:47:22 PM PDT 24
Finished Jul 20 06:47:27 PM PDT 24
Peak memory 213676 kb
Host smart-67f65f80-716e-4a84-abe3-b86800e67ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820814035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1820814035
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2068711217
Short name T206
Test name
Test status
Simulation time 276432583 ps
CPU time 1.38 seconds
Started Jul 20 06:47:21 PM PDT 24
Finished Jul 20 06:47:23 PM PDT 24
Peak memory 205000 kb
Host smart-a0eca571-6d25-48fb-8152-f537480d7bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068711217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2068711217
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3027176783
Short name T36
Test name
Test status
Simulation time 2351682286 ps
CPU time 4.09 seconds
Started Jul 20 06:47:23 PM PDT 24
Finished Jul 20 06:47:28 PM PDT 24
Peak memory 205040 kb
Host smart-221bd797-df71-4481-a372-16d3aca3dbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027176783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3027176783
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1339097283
Short name T194
Test name
Test status
Simulation time 116458622 ps
CPU time 0.84 seconds
Started Jul 20 06:47:22 PM PDT 24
Finished Jul 20 06:47:24 PM PDT 24
Peak memory 204968 kb
Host smart-61a2016a-4d2e-4a75-99a6-749db6d8b657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339097283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1339097283
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2734337728
Short name T235
Test name
Test status
Simulation time 2601280092 ps
CPU time 8.6 seconds
Started Jul 20 06:47:17 PM PDT 24
Finished Jul 20 06:47:27 PM PDT 24
Peak memory 205416 kb
Host smart-c91d74a2-07e6-406d-820f-1004edfa61ef
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734337728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2734337728
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.919731797
Short name T54
Test name
Test status
Simulation time 153083333 ps
CPU time 0.84 seconds
Started Jul 20 06:47:22 PM PDT 24
Finished Jul 20 06:47:24 PM PDT 24
Peak memory 204876 kb
Host smart-156e2865-5a29-484f-9dbb-ca90018df5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919731797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.919731797
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2613153854
Short name T39
Test name
Test status
Simulation time 1667262202 ps
CPU time 2.43 seconds
Started Jul 20 06:47:23 PM PDT 24
Finished Jul 20 06:47:26 PM PDT 24
Peak memory 204996 kb
Host smart-d8bab1ad-ea59-4c45-aaf7-91378ebec7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613153854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2613153854
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.4146360879
Short name T265
Test name
Test status
Simulation time 462220093 ps
CPU time 1 seconds
Started Jul 20 06:47:21 PM PDT 24
Finished Jul 20 06:47:23 PM PDT 24
Peak memory 205008 kb
Host smart-19116b22-04ed-452f-9e45-17b06df7a9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146360879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.4146360879
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4193339830
Short name T284
Test name
Test status
Simulation time 1522198804 ps
CPU time 2.76 seconds
Started Jul 20 06:47:19 PM PDT 24
Finished Jul 20 06:47:23 PM PDT 24
Peak memory 204800 kb
Host smart-331c9140-2315-4743-a5e5-0a5a0b6e3f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193339830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4193339830
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.760233009
Short name T260
Test name
Test status
Simulation time 5514883626 ps
CPU time 9.28 seconds
Started Jul 20 06:47:27 PM PDT 24
Finished Jul 20 06:47:37 PM PDT 24
Peak memory 205312 kb
Host smart-51380291-f0c5-4337-851c-9666e4b875cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760233009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.760233009
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1414109619
Short name T33
Test name
Test status
Simulation time 323639191 ps
CPU time 1.59 seconds
Started Jul 20 06:47:21 PM PDT 24
Finished Jul 20 06:47:24 PM PDT 24
Peak memory 205000 kb
Host smart-3b2a69d7-de46-4f60-b55c-d82a4355a611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414109619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1414109619
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1549762726
Short name T166
Test name
Test status
Simulation time 911745939 ps
CPU time 2.05 seconds
Started Jul 20 06:47:27 PM PDT 24
Finished Jul 20 06:47:30 PM PDT 24
Peak memory 205012 kb
Host smart-8c8806cc-59ec-4819-8aed-e883e0552c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549762726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1549762726
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.4121958317
Short name T164
Test name
Test status
Simulation time 5564958074 ps
CPU time 15.58 seconds
Started Jul 20 06:47:19 PM PDT 24
Finished Jul 20 06:47:35 PM PDT 24
Peak memory 205388 kb
Host smart-4c5aeff5-fe85-41b7-bebe-064a1a956627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121958317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.4121958317
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3811736981
Short name T34
Test name
Test status
Simulation time 124761801 ps
CPU time 0.81 seconds
Started Jul 20 06:47:22 PM PDT 24
Finished Jul 20 06:47:24 PM PDT 24
Peak memory 213212 kb
Host smart-6030df83-b991-4db4-be5b-811ce80bb9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811736981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3811736981
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2559430849
Short name T69
Test name
Test status
Simulation time 2276917865 ps
CPU time 3.78 seconds
Started Jul 20 06:47:22 PM PDT 24
Finished Jul 20 06:47:27 PM PDT 24
Peak memory 205136 kb
Host smart-3c0a1fa4-b405-4ab0-8d07-799816f46b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559430849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2559430849
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3247975869
Short name T264
Test name
Test status
Simulation time 6563957645 ps
CPU time 10.45 seconds
Started Jul 20 06:47:15 PM PDT 24
Finished Jul 20 06:47:27 PM PDT 24
Peak memory 213700 kb
Host smart-e572fc0d-5457-4178-9c70-1e13100db051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247975869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3247975869
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1439095377
Short name T53
Test name
Test status
Simulation time 777037569 ps
CPU time 1.6 seconds
Started Jul 20 06:47:21 PM PDT 24
Finished Jul 20 06:47:23 PM PDT 24
Peak memory 229304 kb
Host smart-81e6f52a-5e43-42ea-ad13-fe06bd49e327
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439095377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1439095377
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.734030010
Short name T278
Test name
Test status
Simulation time 1712404919 ps
CPU time 5.73 seconds
Started Jul 20 06:47:16 PM PDT 24
Finished Jul 20 06:47:24 PM PDT 24
Peak memory 205024 kb
Host smart-7e0129f2-1f07-4a8e-83d3-3a6ad3c9a2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734030010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.734030010
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2129882509
Short name T9
Test name
Test status
Simulation time 7796683879 ps
CPU time 21.5 seconds
Started Jul 20 06:47:16 PM PDT 24
Finished Jul 20 06:47:39 PM PDT 24
Peak memory 205392 kb
Host smart-271776c4-703d-4cf9-8460-4ed7b69733ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129882509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2129882509
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1187090190
Short name T40
Test name
Test status
Simulation time 109756197 ps
CPU time 1.02 seconds
Started Jul 20 06:47:27 PM PDT 24
Finished Jul 20 06:47:30 PM PDT 24
Peak memory 205008 kb
Host smart-fabd523c-1f47-4308-ac51-c8623ffdb300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187090190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1187090190
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2607322653
Short name T207
Test name
Test status
Simulation time 129077462 ps
CPU time 0.89 seconds
Started Jul 20 06:47:28 PM PDT 24
Finished Jul 20 06:47:31 PM PDT 24
Peak memory 204992 kb
Host smart-8d2db3e0-30da-4526-ad7a-3bf50ba08b74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607322653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2607322653
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2653326097
Short name T272
Test name
Test status
Simulation time 107769876245 ps
CPU time 76.86 seconds
Started Jul 20 06:47:21 PM PDT 24
Finished Jul 20 06:48:39 PM PDT 24
Peak memory 216840 kb
Host smart-9e6c1398-8f54-48f8-88d6-90e4609ab590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653326097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2653326097
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2276725225
Short name T173
Test name
Test status
Simulation time 1977078563 ps
CPU time 2.35 seconds
Started Jul 20 06:47:22 PM PDT 24
Finished Jul 20 06:47:26 PM PDT 24
Peak memory 205404 kb
Host smart-edbf8c44-dd33-42b6-bbec-d3f24e2b6a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276725225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2276725225
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1348676583
Short name T13
Test name
Test status
Simulation time 1025857347 ps
CPU time 3.35 seconds
Started Jul 20 06:47:31 PM PDT 24
Finished Jul 20 06:47:36 PM PDT 24
Peak memory 205036 kb
Host smart-2d77c6ea-ae98-4869-bffc-af10ac920ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348676583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1348676583
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.117824617
Short name T42
Test name
Test status
Simulation time 1229123777 ps
CPU time 2.97 seconds
Started Jul 20 06:47:29 PM PDT 24
Finished Jul 20 06:47:34 PM PDT 24
Peak memory 204992 kb
Host smart-fca02fff-c23c-49d0-a1d7-f1dce0dc7ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117824617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.117824617
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.544975606
Short name T165
Test name
Test status
Simulation time 293325760 ps
CPU time 1.14 seconds
Started Jul 20 06:47:30 PM PDT 24
Finished Jul 20 06:47:32 PM PDT 24
Peak memory 205024 kb
Host smart-c88bac92-3c1e-4d21-b28f-03a50b3428bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544975606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.544975606
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2725836387
Short name T8
Test name
Test status
Simulation time 331692016 ps
CPU time 1.14 seconds
Started Jul 20 06:47:28 PM PDT 24
Finished Jul 20 06:47:31 PM PDT 24
Peak memory 204988 kb
Host smart-34fbf1ce-a101-44d1-a070-8706a80e76b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725836387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2725836387
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.3626765049
Short name T58
Test name
Test status
Simulation time 93773436 ps
CPU time 0.92 seconds
Started Jul 20 06:47:29 PM PDT 24
Finished Jul 20 06:47:32 PM PDT 24
Peak memory 215500 kb
Host smart-3e941514-5fe7-4d56-b17e-ba234c9e79fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626765049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3626765049
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1266152814
Short name T17
Test name
Test status
Simulation time 3103464386 ps
CPU time 5.5 seconds
Started Jul 20 06:47:21 PM PDT 24
Finished Jul 20 06:47:28 PM PDT 24
Peak memory 213812 kb
Host smart-d0e3d292-ade5-4757-bc58-0dcecf19f074
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1266152814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.1266152814
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.12477704
Short name T55
Test name
Test status
Simulation time 150613225 ps
CPU time 0.99 seconds
Started Jul 20 06:47:31 PM PDT 24
Finished Jul 20 06:47:33 PM PDT 24
Peak memory 204988 kb
Host smart-d2ce48b3-d8a9-4e18-985b-148cf761da5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12477704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.12477704
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.161704972
Short name T167
Test name
Test status
Simulation time 1506632759 ps
CPU time 1.45 seconds
Started Jul 20 06:47:28 PM PDT 24
Finished Jul 20 06:47:31 PM PDT 24
Peak memory 204980 kb
Host smart-c397f979-d137-49e7-bc0c-64177d0ab6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161704972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.161704972
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3461665374
Short name T269
Test name
Test status
Simulation time 68611375 ps
CPU time 0.85 seconds
Started Jul 20 06:47:29 PM PDT 24
Finished Jul 20 06:47:32 PM PDT 24
Peak memory 205000 kb
Host smart-05294dc8-f0e8-4a3e-83d8-8b4ac4b47862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461665374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3461665374
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1998406568
Short name T224
Test name
Test status
Simulation time 367628334 ps
CPU time 1.21 seconds
Started Jul 20 06:47:31 PM PDT 24
Finished Jul 20 06:47:33 PM PDT 24
Peak memory 205024 kb
Host smart-dd3bedf5-4960-4c64-a6c3-f274c22e022f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998406568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1998406568
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3743527504
Short name T251
Test name
Test status
Simulation time 2305370133 ps
CPU time 2.25 seconds
Started Jul 20 06:47:29 PM PDT 24
Finished Jul 20 06:47:33 PM PDT 24
Peak memory 204908 kb
Host smart-bd7f3d6a-524f-4ac8-9ee9-079a82c32f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743527504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3743527504
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3900230906
Short name T245
Test name
Test status
Simulation time 942325306 ps
CPU time 2.18 seconds
Started Jul 20 06:47:29 PM PDT 24
Finished Jul 20 06:47:33 PM PDT 24
Peak memory 204980 kb
Host smart-a6c502a7-69ce-4674-be19-f23a4ea5c294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900230906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3900230906
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3826100515
Short name T183
Test name
Test status
Simulation time 380543870 ps
CPU time 1.09 seconds
Started Jul 20 06:47:28 PM PDT 24
Finished Jul 20 06:47:31 PM PDT 24
Peak memory 205000 kb
Host smart-2de7a7cc-b517-4214-8c05-c016c26101d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826100515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3826100515
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.4188897041
Short name T163
Test name
Test status
Simulation time 361460319 ps
CPU time 1.47 seconds
Started Jul 20 06:47:28 PM PDT 24
Finished Jul 20 06:47:31 PM PDT 24
Peak memory 204988 kb
Host smart-84873100-8cd1-4014-a42a-a4ebca5cecde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188897041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.4188897041
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2342590170
Short name T29
Test name
Test status
Simulation time 5696251263 ps
CPU time 6.57 seconds
Started Jul 20 06:47:29 PM PDT 24
Finished Jul 20 06:47:37 PM PDT 24
Peak memory 205416 kb
Host smart-670cf517-3733-4d60-bffb-29663203d31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342590170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2342590170
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3202562670
Short name T168
Test name
Test status
Simulation time 365102477 ps
CPU time 1.75 seconds
Started Jul 20 06:47:28 PM PDT 24
Finished Jul 20 06:47:31 PM PDT 24
Peak memory 213188 kb
Host smart-e41afa6e-e214-4121-9581-ddff51a462e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202562670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3202562670
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1387443738
Short name T24
Test name
Test status
Simulation time 924258397 ps
CPU time 2.05 seconds
Started Jul 20 06:47:30 PM PDT 24
Finished Jul 20 06:47:34 PM PDT 24
Peak memory 204928 kb
Host smart-5282ab30-e23d-4019-81f0-922ed8426ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387443738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1387443738
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1118014234
Short name T7
Test name
Test status
Simulation time 427454376 ps
CPU time 1.7 seconds
Started Jul 20 06:47:30 PM PDT 24
Finished Jul 20 06:47:34 PM PDT 24
Peak memory 204964 kb
Host smart-724022ab-e78b-4906-9bce-9abe7f40e6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118014234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1118014234
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2743471638
Short name T37
Test name
Test status
Simulation time 134797106 ps
CPU time 1.11 seconds
Started Jul 20 06:47:32 PM PDT 24
Finished Jul 20 06:47:34 PM PDT 24
Peak memory 213312 kb
Host smart-3b90f57e-b49e-4037-b55b-4f3d4c87e7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743471638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2743471638
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2743066286
Short name T47
Test name
Test status
Simulation time 974057510 ps
CPU time 1.82 seconds
Started Jul 20 06:47:22 PM PDT 24
Finished Jul 20 06:47:25 PM PDT 24
Peak memory 205324 kb
Host smart-9cef5d44-990e-4ac1-a4ab-b624b77711de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743066286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2743066286
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.4227087298
Short name T280
Test name
Test status
Simulation time 885329868 ps
CPU time 1.41 seconds
Started Jul 20 06:47:24 PM PDT 24
Finished Jul 20 06:47:27 PM PDT 24
Peak memory 204996 kb
Host smart-b4379c54-f3cb-41b2-a740-5c8913b631cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227087298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.4227087298
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.3886745128
Short name T162
Test name
Test status
Simulation time 6487432087 ps
CPU time 10.36 seconds
Started Jul 20 06:47:28 PM PDT 24
Finished Jul 20 06:47:40 PM PDT 24
Peak memory 213536 kb
Host smart-b58ac475-79a2-4335-a164-cf3174010937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886745128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3886745128
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1263304336
Short name T228
Test name
Test status
Simulation time 54631191 ps
CPU time 0.78 seconds
Started Jul 20 06:47:51 PM PDT 24
Finished Jul 20 06:47:53 PM PDT 24
Peak memory 205020 kb
Host smart-edb5c528-845d-4b69-b7ee-0a2054cea9ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263304336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1263304336
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3533846620
Short name T196
Test name
Test status
Simulation time 12990757036 ps
CPU time 8.04 seconds
Started Jul 20 06:47:50 PM PDT 24
Finished Jul 20 06:47:59 PM PDT 24
Peak memory 213708 kb
Host smart-daa975fc-0bdb-4e10-84bc-b02d75e49225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533846620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3533846620
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3765740900
Short name T236
Test name
Test status
Simulation time 4883693209 ps
CPU time 5.02 seconds
Started Jul 20 06:47:51 PM PDT 24
Finished Jul 20 06:47:58 PM PDT 24
Peak memory 213648 kb
Host smart-edba765e-40a1-4855-95c6-d29e7082b5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765740900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3765740900
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1492678980
Short name T279
Test name
Test status
Simulation time 1811813874 ps
CPU time 2.72 seconds
Started Jul 20 06:47:46 PM PDT 24
Finished Jul 20 06:47:49 PM PDT 24
Peak memory 205360 kb
Host smart-1c55c62e-1b67-4419-9e2a-977fde427389
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1492678980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1492678980
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.362658087
Short name T45
Test name
Test status
Simulation time 4875962781 ps
CPU time 8.68 seconds
Started Jul 20 06:47:45 PM PDT 24
Finished Jul 20 06:47:55 PM PDT 24
Peak memory 205476 kb
Host smart-b288d8d0-b456-470a-b96b-321fe31b54a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362658087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.362658087
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.125065359
Short name T248
Test name
Test status
Simulation time 44012842 ps
CPU time 0.81 seconds
Started Jul 20 06:47:47 PM PDT 24
Finished Jul 20 06:47:49 PM PDT 24
Peak memory 204988 kb
Host smart-bd438ad2-46fb-4877-b7ff-9a5cb887288a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125065359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.125065359
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.87285924
Short name T28
Test name
Test status
Simulation time 15771878044 ps
CPU time 9.78 seconds
Started Jul 20 06:47:45 PM PDT 24
Finished Jul 20 06:47:55 PM PDT 24
Peak memory 213588 kb
Host smart-39aa5cf9-a01b-434b-9dc0-40f22a3e6554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87285924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.87285924
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1679804829
Short name T68
Test name
Test status
Simulation time 7258307327 ps
CPU time 6.41 seconds
Started Jul 20 06:47:48 PM PDT 24
Finished Jul 20 06:47:56 PM PDT 24
Peak memory 215096 kb
Host smart-8093968f-3185-457c-91dd-f943d8488fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679804829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1679804829
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.955204186
Short name T281
Test name
Test status
Simulation time 1921502222 ps
CPU time 3.18 seconds
Started Jul 20 06:47:47 PM PDT 24
Finished Jul 20 06:47:52 PM PDT 24
Peak memory 205316 kb
Host smart-c4a7c84c-5e4e-49cc-a8f5-637b348423ea
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955204186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.955204186
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2832210052
Short name T254
Test name
Test status
Simulation time 1737835918 ps
CPU time 6.22 seconds
Started Jul 20 06:47:48 PM PDT 24
Finished Jul 20 06:47:56 PM PDT 24
Peak memory 205244 kb
Host smart-9dda82ad-a1fb-43f2-acb0-3eaf231a9ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832210052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2832210052
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2680489028
Short name T200
Test name
Test status
Simulation time 33684043 ps
CPU time 0.75 seconds
Started Jul 20 06:47:46 PM PDT 24
Finished Jul 20 06:47:48 PM PDT 24
Peak memory 204996 kb
Host smart-da182916-ae53-49cd-a3f1-cf52a06958ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680489028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2680489028
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2730521333
Short name T253
Test name
Test status
Simulation time 3536428182 ps
CPU time 4.36 seconds
Started Jul 20 06:47:48 PM PDT 24
Finished Jul 20 06:47:54 PM PDT 24
Peak memory 205544 kb
Host smart-9f044ec8-5615-4fd2-b420-61a3a812cab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730521333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2730521333
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3788533233
Short name T125
Test name
Test status
Simulation time 6191950986 ps
CPU time 9.25 seconds
Started Jul 20 06:47:49 PM PDT 24
Finished Jul 20 06:48:00 PM PDT 24
Peak memory 205544 kb
Host smart-758b2f9d-4296-4ae2-84ee-42a0b684f633
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3788533233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3788533233
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3908231030
Short name T2
Test name
Test status
Simulation time 10324042972 ps
CPU time 10.95 seconds
Started Jul 20 06:47:46 PM PDT 24
Finished Jul 20 06:47:58 PM PDT 24
Peak memory 213656 kb
Host smart-46742805-06ee-4ed6-9dca-2100a8841289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908231030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3908231030
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.525242946
Short name T211
Test name
Test status
Simulation time 146321018 ps
CPU time 0.89 seconds
Started Jul 20 06:47:47 PM PDT 24
Finished Jul 20 06:47:50 PM PDT 24
Peak memory 205000 kb
Host smart-a85020d9-0769-4c8d-ae4f-0a5d44d59855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525242946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.525242946
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1028730404
Short name T262
Test name
Test status
Simulation time 8603757435 ps
CPU time 29.8 seconds
Started Jul 20 06:47:50 PM PDT 24
Finished Jul 20 06:48:21 PM PDT 24
Peak memory 205528 kb
Host smart-a800bd11-c32c-4e6a-aa0b-077f52199076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028730404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1028730404
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.536859887
Short name T209
Test name
Test status
Simulation time 6358162666 ps
CPU time 16.59 seconds
Started Jul 20 06:47:51 PM PDT 24
Finished Jul 20 06:48:09 PM PDT 24
Peak memory 215028 kb
Host smart-310231a2-474d-440a-82be-d57c0118aa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536859887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.536859887
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3776402784
Short name T175
Test name
Test status
Simulation time 4766370333 ps
CPU time 7.66 seconds
Started Jul 20 06:47:45 PM PDT 24
Finished Jul 20 06:47:53 PM PDT 24
Peak memory 213652 kb
Host smart-c4fc9370-57d9-483a-be91-1ecdbf507b99
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776402784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3776402784
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1314678871
Short name T222
Test name
Test status
Simulation time 6203034710 ps
CPU time 9.26 seconds
Started Jul 20 06:47:44 PM PDT 24
Finished Jul 20 06:47:54 PM PDT 24
Peak memory 213716 kb
Host smart-ba7c7547-b255-409c-8c32-0a5317bd5b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314678871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1314678871
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1031660797
Short name T213
Test name
Test status
Simulation time 99450007 ps
CPU time 0.77 seconds
Started Jul 20 06:47:45 PM PDT 24
Finished Jul 20 06:47:47 PM PDT 24
Peak memory 204968 kb
Host smart-f2e712fd-3d72-4be9-bd16-c4b76fe3996e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031660797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1031660797
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.85621660
Short name T186
Test name
Test status
Simulation time 25379907712 ps
CPU time 34.86 seconds
Started Jul 20 06:47:44 PM PDT 24
Finished Jul 20 06:48:20 PM PDT 24
Peak memory 213716 kb
Host smart-51cdfad1-af23-40da-b270-848f2a959cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85621660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.85621660
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.990879025
Short name T285
Test name
Test status
Simulation time 6297446934 ps
CPU time 18.52 seconds
Started Jul 20 06:47:44 PM PDT 24
Finished Jul 20 06:48:04 PM PDT 24
Peak memory 213684 kb
Host smart-f1a78085-62b9-44d2-8f93-53247ae6fd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990879025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.990879025
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2244107109
Short name T263
Test name
Test status
Simulation time 2195141514 ps
CPU time 2.79 seconds
Started Jul 20 06:47:48 PM PDT 24
Finished Jul 20 06:47:53 PM PDT 24
Peak memory 205304 kb
Host smart-fed21d1a-9661-474e-8db0-dc14c0e107d0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2244107109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.2244107109
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.4129556982
Short name T193
Test name
Test status
Simulation time 6318911552 ps
CPU time 7.09 seconds
Started Jul 20 06:47:50 PM PDT 24
Finished Jul 20 06:47:58 PM PDT 24
Peak memory 213732 kb
Host smart-24f3ad88-b546-4344-bad0-ee29790e3b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129556982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.4129556982
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2414089757
Short name T172
Test name
Test status
Simulation time 93975796 ps
CPU time 0.82 seconds
Started Jul 20 06:47:51 PM PDT 24
Finished Jul 20 06:47:54 PM PDT 24
Peak memory 204996 kb
Host smart-3d73c296-408d-4e4c-a80f-6a3603472a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414089757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2414089757
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.126891653
Short name T252
Test name
Test status
Simulation time 18842073776 ps
CPU time 14.96 seconds
Started Jul 20 06:47:47 PM PDT 24
Finished Jul 20 06:48:04 PM PDT 24
Peak memory 213720 kb
Host smart-4c608503-2bda-44e3-b8dd-3e6943155cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126891653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.126891653
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2586239607
Short name T233
Test name
Test status
Simulation time 1068639994 ps
CPU time 3.82 seconds
Started Jul 20 06:47:46 PM PDT 24
Finished Jul 20 06:47:51 PM PDT 24
Peak memory 205568 kb
Host smart-ea5d7439-4cac-41d9-847f-33ca8566d2ce
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586239607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2586239607
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.363941551
Short name T133
Test name
Test status
Simulation time 889764212 ps
CPU time 3.15 seconds
Started Jul 20 06:47:44 PM PDT 24
Finished Jul 20 06:47:48 PM PDT 24
Peak memory 213588 kb
Host smart-de931a4e-d2c2-42e4-97ea-e1c8938b615a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363941551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.363941551
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.2886224091
Short name T160
Test name
Test status
Simulation time 11227586221 ps
CPU time 17.37 seconds
Started Jul 20 06:47:52 PM PDT 24
Finished Jul 20 06:48:11 PM PDT 24
Peak memory 205320 kb
Host smart-8f1b30ea-4598-4d62-88f9-d0e5454a56a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886224091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.2886224091
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3134743704
Short name T276
Test name
Test status
Simulation time 140519519 ps
CPU time 0.76 seconds
Started Jul 20 06:47:51 PM PDT 24
Finished Jul 20 06:47:53 PM PDT 24
Peak memory 205028 kb
Host smart-eb2c0235-e018-4818-90b2-7447f15f6341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134743704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3134743704
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.4059269369
Short name T275
Test name
Test status
Simulation time 6113635508 ps
CPU time 4.52 seconds
Started Jul 20 06:47:52 PM PDT 24
Finished Jul 20 06:47:58 PM PDT 24
Peak memory 205472 kb
Host smart-af9c6258-dd23-4e20-aea7-d7da40c48815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059269369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.4059269369
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.81143799
Short name T219
Test name
Test status
Simulation time 7601483669 ps
CPU time 23.6 seconds
Started Jul 20 06:47:52 PM PDT 24
Finished Jul 20 06:48:18 PM PDT 24
Peak memory 213668 kb
Host smart-99195434-b8cc-4d4f-9881-7c745de40f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81143799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.81143799
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.695765256
Short name T247
Test name
Test status
Simulation time 2117905751 ps
CPU time 6.89 seconds
Started Jul 20 06:47:53 PM PDT 24
Finished Jul 20 06:48:01 PM PDT 24
Peak memory 213520 kb
Host smart-9a337909-8aff-4fc8-9ce4-f472ffd17578
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=695765256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.695765256
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1531948168
Short name T242
Test name
Test status
Simulation time 1943740549 ps
CPU time 2.68 seconds
Started Jul 20 06:47:57 PM PDT 24
Finished Jul 20 06:48:00 PM PDT 24
Peak memory 205420 kb
Host smart-b9e98da4-062f-4eb0-a145-5818b0434787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531948168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1531948168
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1353517445
Short name T3
Test name
Test status
Simulation time 73112190 ps
CPU time 0.72 seconds
Started Jul 20 06:47:54 PM PDT 24
Finished Jul 20 06:47:56 PM PDT 24
Peak memory 205028 kb
Host smart-03861c83-dc2f-4b53-ae95-790a4170ae79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353517445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1353517445
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.796771121
Short name T126
Test name
Test status
Simulation time 10935144444 ps
CPU time 32.97 seconds
Started Jul 20 06:47:52 PM PDT 24
Finished Jul 20 06:48:26 PM PDT 24
Peak memory 213756 kb
Host smart-339025c7-c5a3-4af0-9e99-9004f4a5458b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796771121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.796771121
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3005986754
Short name T177
Test name
Test status
Simulation time 2269440694 ps
CPU time 4.72 seconds
Started Jul 20 06:47:53 PM PDT 24
Finished Jul 20 06:47:59 PM PDT 24
Peak memory 221844 kb
Host smart-532b91e7-3c0f-425f-bed5-d43c1b1986f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005986754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3005986754
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3965483399
Short name T268
Test name
Test status
Simulation time 2492462550 ps
CPU time 8.29 seconds
Started Jul 20 06:47:52 PM PDT 24
Finished Jul 20 06:48:02 PM PDT 24
Peak memory 213620 kb
Host smart-d60c7ced-4fa5-42ca-9f33-bae0b004e0b6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3965483399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3965483399
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3474561517
Short name T215
Test name
Test status
Simulation time 1031405102 ps
CPU time 1.77 seconds
Started Jul 20 06:47:54 PM PDT 24
Finished Jul 20 06:47:57 PM PDT 24
Peak memory 205348 kb
Host smart-b5fd72f4-ac9b-4625-953d-5d873dbc1df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474561517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3474561517
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.893035891
Short name T11
Test name
Test status
Simulation time 9063976370 ps
CPU time 5.71 seconds
Started Jul 20 06:47:58 PM PDT 24
Finished Jul 20 06:48:06 PM PDT 24
Peak memory 213436 kb
Host smart-d96f62b1-fcb7-4f07-9d6a-e10b2b3563f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893035891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.893035891
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2825110413
Short name T180
Test name
Test status
Simulation time 144957961 ps
CPU time 0.74 seconds
Started Jul 20 06:47:58 PM PDT 24
Finished Jul 20 06:48:01 PM PDT 24
Peak memory 204984 kb
Host smart-9d3bca42-5fd8-4783-aa91-549ca5fbb971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825110413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2825110413
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3622904129
Short name T182
Test name
Test status
Simulation time 11374349580 ps
CPU time 11.93 seconds
Started Jul 20 06:47:52 PM PDT 24
Finished Jul 20 06:48:06 PM PDT 24
Peak memory 205480 kb
Host smart-4e69614c-dc08-4bc1-a68e-b5a9a3e6bdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622904129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3622904129
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.4145422447
Short name T256
Test name
Test status
Simulation time 1500081450 ps
CPU time 1.89 seconds
Started Jul 20 06:47:53 PM PDT 24
Finished Jul 20 06:47:57 PM PDT 24
Peak memory 205332 kb
Host smart-7d95c815-1cf1-4fca-b116-4b8b98da82fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145422447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.4145422447
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2808756801
Short name T48
Test name
Test status
Simulation time 4367778491 ps
CPU time 3.32 seconds
Started Jul 20 06:47:54 PM PDT 24
Finished Jul 20 06:47:58 PM PDT 24
Peak memory 205468 kb
Host smart-2f621df1-db04-47af-9510-b98d3a6506d5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2808756801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2808756801
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.2250307867
Short name T67
Test name
Test status
Simulation time 908369475 ps
CPU time 1.2 seconds
Started Jul 20 06:47:54 PM PDT 24
Finished Jul 20 06:47:56 PM PDT 24
Peak memory 213608 kb
Host smart-c413880c-7d89-4b5b-9ba6-c94dda90ef1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250307867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2250307867
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2814408638
Short name T15
Test name
Test status
Simulation time 7184396357 ps
CPU time 2.69 seconds
Started Jul 20 06:47:58 PM PDT 24
Finished Jul 20 06:48:02 PM PDT 24
Peak memory 213576 kb
Host smart-775fda6f-8d36-43a9-ae14-344281e3b55b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814408638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2814408638
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.4011404067
Short name T220
Test name
Test status
Simulation time 38990111 ps
CPU time 0.78 seconds
Started Jul 20 06:47:54 PM PDT 24
Finished Jul 20 06:47:56 PM PDT 24
Peak memory 205012 kb
Host smart-c085dbb5-7933-4619-89f4-1ee00ad6ceee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011404067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.4011404067
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.488979927
Short name T197
Test name
Test status
Simulation time 5218338002 ps
CPU time 11.37 seconds
Started Jul 20 06:47:54 PM PDT 24
Finished Jul 20 06:48:06 PM PDT 24
Peak memory 221876 kb
Host smart-18d1c20e-b76b-4e9b-bab0-3cf817f3397b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488979927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.488979927
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2622455850
Short name T271
Test name
Test status
Simulation time 17401121370 ps
CPU time 17.77 seconds
Started Jul 20 06:47:54 PM PDT 24
Finished Jul 20 06:48:13 PM PDT 24
Peak memory 213700 kb
Host smart-a1a920c5-173f-4342-b162-44f099433ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622455850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2622455850
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.364703113
Short name T266
Test name
Test status
Simulation time 2367225022 ps
CPU time 7.92 seconds
Started Jul 20 06:47:51 PM PDT 24
Finished Jul 20 06:48:01 PM PDT 24
Peak memory 205404 kb
Host smart-d2342300-0fc2-41c5-a6ac-6d45f19bb292
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364703113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.364703113
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.1260370432
Short name T127
Test name
Test status
Simulation time 2938337173 ps
CPU time 3.33 seconds
Started Jul 20 06:47:53 PM PDT 24
Finished Jul 20 06:47:58 PM PDT 24
Peak memory 213584 kb
Host smart-fa2f0dce-c49a-4cc0-be59-f2d84597be29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260370432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1260370432
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.4088593206
Short name T240
Test name
Test status
Simulation time 40148411 ps
CPU time 0.7 seconds
Started Jul 20 06:47:28 PM PDT 24
Finished Jul 20 06:47:31 PM PDT 24
Peak memory 205016 kb
Host smart-91e888d4-8af2-4eb1-8840-c03c7cfae582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088593206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.4088593206
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.4245030083
Short name T282
Test name
Test status
Simulation time 7433499229 ps
CPU time 11.74 seconds
Started Jul 20 06:47:27 PM PDT 24
Finished Jul 20 06:47:40 PM PDT 24
Peak memory 213668 kb
Host smart-9ea122f1-4d20-4fab-8356-45c3c2b6e08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245030083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.4245030083
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.176195113
Short name T139
Test name
Test status
Simulation time 3652687850 ps
CPU time 3.34 seconds
Started Jul 20 06:47:31 PM PDT 24
Finished Jul 20 06:47:36 PM PDT 24
Peak memory 213616 kb
Host smart-c25ae151-d48f-41d4-876a-6beef33a9c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176195113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.176195113
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.337542805
Short name T267
Test name
Test status
Simulation time 2293429743 ps
CPU time 7.25 seconds
Started Jul 20 06:47:32 PM PDT 24
Finished Jul 20 06:47:40 PM PDT 24
Peak memory 213524 kb
Host smart-fa288c63-ddd1-4ff4-b136-26a367887085
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337542805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.337542805
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3919153145
Short name T241
Test name
Test status
Simulation time 164323534 ps
CPU time 0.79 seconds
Started Jul 20 06:47:28 PM PDT 24
Finished Jul 20 06:47:30 PM PDT 24
Peak memory 205004 kb
Host smart-78834213-abd2-4649-b42d-aa24332c35c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919153145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3919153145
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.4004692842
Short name T250
Test name
Test status
Simulation time 1727797934 ps
CPU time 3.15 seconds
Started Jul 20 06:47:31 PM PDT 24
Finished Jul 20 06:47:35 PM PDT 24
Peak memory 205456 kb
Host smart-d6ff1f9c-4033-4882-8041-903aebca1fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004692842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.4004692842
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1911567371
Short name T51
Test name
Test status
Simulation time 233432692 ps
CPU time 1.7 seconds
Started Jul 20 06:47:31 PM PDT 24
Finished Jul 20 06:47:34 PM PDT 24
Peak memory 229604 kb
Host smart-e2d9edc4-e016-44ee-a386-6f81cf473324
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911567371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1911567371
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1776193933
Short name T189
Test name
Test status
Simulation time 145651709 ps
CPU time 0.92 seconds
Started Jul 20 06:47:58 PM PDT 24
Finished Jul 20 06:48:01 PM PDT 24
Peak memory 205004 kb
Host smart-f759a5a3-4eca-40ad-a89a-7c59212a7182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776193933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1776193933
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1958523122
Short name T210
Test name
Test status
Simulation time 41592081 ps
CPU time 0.78 seconds
Started Jul 20 06:47:54 PM PDT 24
Finished Jul 20 06:47:56 PM PDT 24
Peak memory 204988 kb
Host smart-549ebeea-5062-4379-9ac7-f3b11c290a39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958523122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1958523122
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.494378052
Short name T161
Test name
Test status
Simulation time 4619764553 ps
CPU time 12.4 seconds
Started Jul 20 06:47:53 PM PDT 24
Finished Jul 20 06:48:07 PM PDT 24
Peak memory 213536 kb
Host smart-a8e29ae5-9de0-4e36-a56f-e6a545cbc960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494378052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.494378052
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2832636997
Short name T203
Test name
Test status
Simulation time 81039649 ps
CPU time 0.74 seconds
Started Jul 20 06:47:52 PM PDT 24
Finished Jul 20 06:47:54 PM PDT 24
Peak memory 204992 kb
Host smart-48c67bdd-e90e-4dbd-a851-d38b20dc40b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832636997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2832636997
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1181943671
Short name T195
Test name
Test status
Simulation time 56382291 ps
CPU time 0.68 seconds
Started Jul 20 06:47:59 PM PDT 24
Finished Jul 20 06:48:02 PM PDT 24
Peak memory 205012 kb
Host smart-370acc1c-a0b1-4d7a-bd32-5b43a40de24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181943671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1181943671
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.366674601
Short name T249
Test name
Test status
Simulation time 147188870 ps
CPU time 0.83 seconds
Started Jul 20 06:47:59 PM PDT 24
Finished Jul 20 06:48:01 PM PDT 24
Peak memory 204944 kb
Host smart-9c7ca5f8-ac22-4115-b8b2-05e077e52fb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366674601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.366674601
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.382630784
Short name T216
Test name
Test status
Simulation time 58164035 ps
CPU time 0.72 seconds
Started Jul 20 06:47:58 PM PDT 24
Finished Jul 20 06:47:59 PM PDT 24
Peak memory 205012 kb
Host smart-38647610-eb3b-4613-af1c-20292db77aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382630784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.382630784
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.404315740
Short name T178
Test name
Test status
Simulation time 53610317 ps
CPU time 0.85 seconds
Started Jul 20 06:48:00 PM PDT 24
Finished Jul 20 06:48:03 PM PDT 24
Peak memory 205020 kb
Host smart-b3143cdb-4376-491a-ab9a-d640087d44bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404315740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.404315740
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.2327414274
Short name T138
Test name
Test status
Simulation time 9972017930 ps
CPU time 26.32 seconds
Started Jul 20 06:48:00 PM PDT 24
Finished Jul 20 06:48:28 PM PDT 24
Peak memory 213568 kb
Host smart-f88ff7bd-b2cd-4114-8184-fe1e91a9f1f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327414274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2327414274
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2249919647
Short name T273
Test name
Test status
Simulation time 137876661 ps
CPU time 0.8 seconds
Started Jul 20 06:47:59 PM PDT 24
Finished Jul 20 06:48:01 PM PDT 24
Peak memory 204984 kb
Host smart-4565e180-422c-43e3-8ef9-1782f0f20b00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249919647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2249919647
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.4162708777
Short name T244
Test name
Test status
Simulation time 85692309 ps
CPU time 0.73 seconds
Started Jul 20 06:48:00 PM PDT 24
Finished Jul 20 06:48:03 PM PDT 24
Peak memory 205000 kb
Host smart-2746f7bc-777c-4f71-9c01-5e10a1619b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162708777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.4162708777
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.3118341688
Short name T19
Test name
Test status
Simulation time 4663800731 ps
CPU time 2.49 seconds
Started Jul 20 06:48:01 PM PDT 24
Finished Jul 20 06:48:06 PM PDT 24
Peak memory 213464 kb
Host smart-7cfe4c44-ce8a-4889-9421-eb7382a049ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118341688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3118341688
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3111005120
Short name T225
Test name
Test status
Simulation time 35254972 ps
CPU time 0.74 seconds
Started Jul 20 06:47:37 PM PDT 24
Finished Jul 20 06:47:39 PM PDT 24
Peak memory 205008 kb
Host smart-477684ef-2448-4959-9ccb-ecbf317b2c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111005120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3111005120
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1376465999
Short name T208
Test name
Test status
Simulation time 8260836748 ps
CPU time 10.43 seconds
Started Jul 20 06:47:29 PM PDT 24
Finished Jul 20 06:47:41 PM PDT 24
Peak memory 213664 kb
Host smart-f7b4c63d-bef9-4a2e-b85b-9ed45b1e1634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376465999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1376465999
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.45476271
Short name T123
Test name
Test status
Simulation time 3708236290 ps
CPU time 11.03 seconds
Started Jul 20 06:47:27 PM PDT 24
Finished Jul 20 06:47:39 PM PDT 24
Peak memory 213612 kb
Host smart-0da482a6-e0e9-4fe0-9fba-0f0ab4ea018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45476271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.45476271
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4263377753
Short name T227
Test name
Test status
Simulation time 5081729772 ps
CPU time 9.01 seconds
Started Jul 20 06:47:30 PM PDT 24
Finished Jul 20 06:47:41 PM PDT 24
Peak memory 205432 kb
Host smart-fabebbb2-69a4-4da8-b523-d26595893eb8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263377753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.4263377753
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.105274619
Short name T136
Test name
Test status
Simulation time 123620419 ps
CPU time 1.04 seconds
Started Jul 20 06:47:29 PM PDT 24
Finished Jul 20 06:47:31 PM PDT 24
Peak memory 205000 kb
Host smart-90799740-6f14-473d-bfd8-ffe345ae5226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105274619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.105274619
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3640691019
Short name T181
Test name
Test status
Simulation time 2927410687 ps
CPU time 2.79 seconds
Started Jul 20 06:47:29 PM PDT 24
Finished Jul 20 06:47:33 PM PDT 24
Peak memory 205468 kb
Host smart-e70c70cc-d129-4788-8302-367cb7c767e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640691019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3640691019
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1625055990
Short name T65
Test name
Test status
Simulation time 1194330190 ps
CPU time 1.96 seconds
Started Jul 20 06:47:41 PM PDT 24
Finished Jul 20 06:47:44 PM PDT 24
Peak memory 229396 kb
Host smart-3a12b8a1-9861-4634-a554-df745055be98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625055990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1625055990
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.1144447137
Short name T145
Test name
Test status
Simulation time 6458735980 ps
CPU time 10.27 seconds
Started Jul 20 06:47:40 PM PDT 24
Finished Jul 20 06:47:51 PM PDT 24
Peak memory 213480 kb
Host smart-1f99113a-00fe-4b3d-b0b5-d4edea70e105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144447137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1144447137
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2768006223
Short name T234
Test name
Test status
Simulation time 103324626 ps
CPU time 0.79 seconds
Started Jul 20 06:48:00 PM PDT 24
Finished Jul 20 06:48:04 PM PDT 24
Peak memory 204984 kb
Host smart-b61e0784-0e65-441a-a1ed-44bb76bcaf95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768006223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2768006223
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.4076117833
Short name T169
Test name
Test status
Simulation time 6177133748 ps
CPU time 9.06 seconds
Started Jul 20 06:47:59 PM PDT 24
Finished Jul 20 06:48:10 PM PDT 24
Peak memory 205400 kb
Host smart-4c4c62e0-659a-480c-ab20-dea28827b524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076117833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.4076117833
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3138326827
Short name T201
Test name
Test status
Simulation time 49328525 ps
CPU time 0.77 seconds
Started Jul 20 06:48:02 PM PDT 24
Finished Jul 20 06:48:04 PM PDT 24
Peak memory 205008 kb
Host smart-47a1c077-553e-46a7-87e7-8b0da72d9e36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138326827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3138326827
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.360880190
Short name T121
Test name
Test status
Simulation time 10198797663 ps
CPU time 31.56 seconds
Started Jul 20 06:48:03 PM PDT 24
Finished Jul 20 06:48:35 PM PDT 24
Peak memory 213504 kb
Host smart-92b1ea05-5ce0-4241-a92c-96d6353112c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360880190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.360880190
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3867516703
Short name T231
Test name
Test status
Simulation time 65323683 ps
CPU time 0.91 seconds
Started Jul 20 06:47:58 PM PDT 24
Finished Jul 20 06:48:00 PM PDT 24
Peak memory 205032 kb
Host smart-1a509491-c596-46cd-adc5-dc2544a0e358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867516703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3867516703
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.817476384
Short name T4
Test name
Test status
Simulation time 2484983406 ps
CPU time 7.87 seconds
Started Jul 20 06:48:00 PM PDT 24
Finished Jul 20 06:48:10 PM PDT 24
Peak memory 205252 kb
Host smart-50068ff0-5e20-4c51-bdb2-fa4e91f507fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817476384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.817476384
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.160581939
Short name T230
Test name
Test status
Simulation time 91728893 ps
CPU time 0.74 seconds
Started Jul 20 06:47:59 PM PDT 24
Finished Jul 20 06:48:02 PM PDT 24
Peak memory 205052 kb
Host smart-b9c13116-217a-46bf-b884-ffd2b39e6359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160581939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.160581939
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.2733104833
Short name T135
Test name
Test status
Simulation time 5383889351 ps
CPU time 9.12 seconds
Started Jul 20 06:47:59 PM PDT 24
Finished Jul 20 06:48:10 PM PDT 24
Peak memory 205364 kb
Host smart-3190d454-9f7e-4611-a6e2-6608a9a2b19d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733104833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2733104833
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3756375615
Short name T176
Test name
Test status
Simulation time 168126773 ps
CPU time 0.89 seconds
Started Jul 20 06:48:00 PM PDT 24
Finished Jul 20 06:48:02 PM PDT 24
Peak memory 205004 kb
Host smart-11c9b233-b67d-458f-8f7f-4c9c67f3800f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756375615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3756375615
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.765595349
Short name T6
Test name
Test status
Simulation time 9104329699 ps
CPU time 27.36 seconds
Started Jul 20 06:48:01 PM PDT 24
Finished Jul 20 06:48:31 PM PDT 24
Peak memory 205384 kb
Host smart-a93f53fe-4e98-4caa-8278-f43639932b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765595349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.765595349
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1755406288
Short name T226
Test name
Test status
Simulation time 119426491 ps
CPU time 0.78 seconds
Started Jul 20 06:48:01 PM PDT 24
Finished Jul 20 06:48:04 PM PDT 24
Peak memory 204936 kb
Host smart-03348242-f029-403f-9861-0857dc297279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755406288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1755406288
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3066717030
Short name T243
Test name
Test status
Simulation time 139310683 ps
CPU time 0.86 seconds
Started Jul 20 06:48:03 PM PDT 24
Finished Jul 20 06:48:05 PM PDT 24
Peak memory 204988 kb
Host smart-3e584b90-2e39-470a-8e80-d0d39e3a10fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066717030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3066717030
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.157161638
Short name T144
Test name
Test status
Simulation time 4000015887 ps
CPU time 6.73 seconds
Started Jul 20 06:48:01 PM PDT 24
Finished Jul 20 06:48:10 PM PDT 24
Peak memory 205308 kb
Host smart-518330e0-4e13-42e1-ab18-be7e0202bf91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157161638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.157161638
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3124951925
Short name T232
Test name
Test status
Simulation time 113149338 ps
CPU time 0.97 seconds
Started Jul 20 06:47:58 PM PDT 24
Finished Jul 20 06:48:01 PM PDT 24
Peak memory 205016 kb
Host smart-f0d0136e-9f45-40a9-81ea-6568ac819a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124951925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3124951925
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1753031667
Short name T238
Test name
Test status
Simulation time 46138875 ps
CPU time 0.78 seconds
Started Jul 20 06:48:01 PM PDT 24
Finished Jul 20 06:48:04 PM PDT 24
Peak memory 205000 kb
Host smart-11b670d6-6aa9-4099-bac7-13ba5b16a221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753031667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1753031667
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.3737221655
Short name T174
Test name
Test status
Simulation time 41613633 ps
CPU time 0.81 seconds
Started Jul 20 06:48:01 PM PDT 24
Finished Jul 20 06:48:04 PM PDT 24
Peak memory 205016 kb
Host smart-f254e127-a695-4261-872a-fe1aa3814e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737221655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3737221655
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3458391964
Short name T131
Test name
Test status
Simulation time 12601360187 ps
CPU time 7.47 seconds
Started Jul 20 06:48:03 PM PDT 24
Finished Jul 20 06:48:11 PM PDT 24
Peak memory 213512 kb
Host smart-f1bbb316-1c10-4181-b1a7-20c68405e3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458391964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3458391964
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1366174853
Short name T179
Test name
Test status
Simulation time 68915179 ps
CPU time 0.83 seconds
Started Jul 20 06:47:40 PM PDT 24
Finished Jul 20 06:47:42 PM PDT 24
Peak memory 205028 kb
Host smart-84a3b67c-7cc9-42e0-9191-af4d5c199050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366174853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1366174853
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3417872299
Short name T223
Test name
Test status
Simulation time 7251950818 ps
CPU time 19.66 seconds
Started Jul 20 06:47:38 PM PDT 24
Finished Jul 20 06:47:58 PM PDT 24
Peak memory 213684 kb
Host smart-f3952b45-23d3-4d2e-92bd-c7042ef464a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417872299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3417872299
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3463003296
Short name T261
Test name
Test status
Simulation time 4319847106 ps
CPU time 13.96 seconds
Started Jul 20 06:47:39 PM PDT 24
Finished Jul 20 06:47:54 PM PDT 24
Peak memory 213636 kb
Host smart-3c79077b-fe5d-4e80-ac2c-25237d6d19d8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3463003296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3463003296
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.794828326
Short name T1
Test name
Test status
Simulation time 205440788 ps
CPU time 1.19 seconds
Started Jul 20 06:47:39 PM PDT 24
Finished Jul 20 06:47:41 PM PDT 24
Peak memory 204972 kb
Host smart-f2dc8561-ee11-47a7-8183-c21d2d2caaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794828326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.794828326
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1657075550
Short name T134
Test name
Test status
Simulation time 7163922931 ps
CPU time 7.35 seconds
Started Jul 20 06:47:40 PM PDT 24
Finished Jul 20 06:47:48 PM PDT 24
Peak memory 213660 kb
Host smart-24210999-9034-4278-b3d5-d5e37b55a48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657075550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1657075550
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.620217901
Short name T64
Test name
Test status
Simulation time 503294569 ps
CPU time 1.73 seconds
Started Jul 20 06:47:38 PM PDT 24
Finished Jul 20 06:47:41 PM PDT 24
Peak memory 229392 kb
Host smart-c8c7db8d-378b-4701-a4e0-90aee6aa35db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620217901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.620217901
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.797715993
Short name T122
Test name
Test status
Simulation time 7782166779 ps
CPU time 5.99 seconds
Started Jul 20 06:47:37 PM PDT 24
Finished Jul 20 06:47:44 PM PDT 24
Peak memory 213500 kb
Host smart-5c64e2a3-23db-4200-ad43-73de56c8207c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797715993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.797715993
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3754450036
Short name T204
Test name
Test status
Simulation time 119110756 ps
CPU time 0.77 seconds
Started Jul 20 06:47:59 PM PDT 24
Finished Jul 20 06:48:02 PM PDT 24
Peak memory 204972 kb
Host smart-b5b22035-dee1-4aec-8eee-7eca2023b7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754450036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3754450036
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.4227423486
Short name T20
Test name
Test status
Simulation time 7394806958 ps
CPU time 2.06 seconds
Started Jul 20 06:48:00 PM PDT 24
Finished Jul 20 06:48:05 PM PDT 24
Peak memory 213520 kb
Host smart-4fea9882-3c79-41d8-9d23-9a317063de55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227423486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.4227423486
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3027124013
Short name T192
Test name
Test status
Simulation time 65089400 ps
CPU time 0.72 seconds
Started Jul 20 06:48:00 PM PDT 24
Finished Jul 20 06:48:03 PM PDT 24
Peak memory 205056 kb
Host smart-dd64831e-ab9a-4796-adf7-ea91b37ae03e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027124013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3027124013
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1270633077
Short name T199
Test name
Test status
Simulation time 97130179 ps
CPU time 0.72 seconds
Started Jul 20 06:48:08 PM PDT 24
Finished Jul 20 06:48:10 PM PDT 24
Peak memory 205008 kb
Host smart-0bcc9017-8a68-429c-a2be-65f7f28c6716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270633077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1270633077
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.1500135314
Short name T140
Test name
Test status
Simulation time 3192202368 ps
CPU time 1.88 seconds
Started Jul 20 06:48:07 PM PDT 24
Finished Jul 20 06:48:11 PM PDT 24
Peak memory 205284 kb
Host smart-d5d6f606-c718-43e4-8b62-b9cb1726d540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500135314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1500135314
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1185963527
Short name T49
Test name
Test status
Simulation time 31870248 ps
CPU time 0.78 seconds
Started Jul 20 06:48:08 PM PDT 24
Finished Jul 20 06:48:11 PM PDT 24
Peak memory 204984 kb
Host smart-38a18914-880e-41dd-ad50-7b32cc540786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185963527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1185963527
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.3154468950
Short name T14
Test name
Test status
Simulation time 1267347163 ps
CPU time 1.94 seconds
Started Jul 20 06:48:08 PM PDT 24
Finished Jul 20 06:48:12 PM PDT 24
Peak memory 205220 kb
Host smart-f2ce0c7a-67dd-4a07-aa29-9f8187cce751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154468950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3154468950
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2594548675
Short name T205
Test name
Test status
Simulation time 232531236 ps
CPU time 0.81 seconds
Started Jul 20 06:48:09 PM PDT 24
Finished Jul 20 06:48:12 PM PDT 24
Peak memory 205004 kb
Host smart-052bf46e-88c9-4c67-be31-474a6bca1338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594548675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2594548675
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.4215605369
Short name T246
Test name
Test status
Simulation time 99343283 ps
CPU time 0.78 seconds
Started Jul 20 06:48:11 PM PDT 24
Finished Jul 20 06:48:13 PM PDT 24
Peak memory 205004 kb
Host smart-20cd1f97-742c-4c23-9dc2-bad41e4aff14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215605369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.4215605369
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2821655581
Short name T214
Test name
Test status
Simulation time 173576508 ps
CPU time 0.83 seconds
Started Jul 20 06:48:06 PM PDT 24
Finished Jul 20 06:48:08 PM PDT 24
Peak memory 205008 kb
Host smart-ab4e3ea4-2720-415f-b110-1b5e75acdaa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821655581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2821655581
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1166299711
Short name T187
Test name
Test status
Simulation time 73400645 ps
CPU time 0.81 seconds
Started Jul 20 06:48:07 PM PDT 24
Finished Jul 20 06:48:09 PM PDT 24
Peak memory 205024 kb
Host smart-c40c75b3-60d9-48a4-bab3-0a02001797fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166299711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1166299711
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.229983886
Short name T171
Test name
Test status
Simulation time 147641820 ps
CPU time 1.09 seconds
Started Jul 20 06:48:10 PM PDT 24
Finished Jul 20 06:48:14 PM PDT 24
Peak memory 204988 kb
Host smart-b46e0048-b90b-4578-9581-d8934f5db11d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229983886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.229983886
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1496974479
Short name T170
Test name
Test status
Simulation time 52062244 ps
CPU time 0.73 seconds
Started Jul 20 06:48:08 PM PDT 24
Finished Jul 20 06:48:11 PM PDT 24
Peak memory 205032 kb
Host smart-b1543963-8016-4453-b2ce-5d332bfba228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496974479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1496974479
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.3241937451
Short name T128
Test name
Test status
Simulation time 6837923718 ps
CPU time 6.93 seconds
Started Jul 20 06:48:08 PM PDT 24
Finished Jul 20 06:48:16 PM PDT 24
Peak memory 213508 kb
Host smart-11176e61-40e4-4ad6-93cb-4e6dc87f199c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241937451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3241937451
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.96367264
Short name T113
Test name
Test status
Simulation time 76997768 ps
CPU time 0.77 seconds
Started Jul 20 06:47:39 PM PDT 24
Finished Jul 20 06:47:41 PM PDT 24
Peak memory 204984 kb
Host smart-5138c506-d0c9-4077-9f0b-883489aaa5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96367264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.96367264
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1513451067
Short name T77
Test name
Test status
Simulation time 8771572761 ps
CPU time 23.69 seconds
Started Jul 20 06:47:37 PM PDT 24
Finished Jul 20 06:48:02 PM PDT 24
Peak memory 213628 kb
Host smart-783be0a9-e661-42cd-9dc7-fba6ea84434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513451067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1513451067
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2263710634
Short name T257
Test name
Test status
Simulation time 2235462956 ps
CPU time 4.6 seconds
Started Jul 20 06:47:37 PM PDT 24
Finished Jul 20 06:47:43 PM PDT 24
Peak memory 213596 kb
Host smart-445b46ca-6b42-4ee9-9dfe-f575c31543af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263710634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2263710634
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2140197026
Short name T258
Test name
Test status
Simulation time 2437073333 ps
CPU time 7.7 seconds
Started Jul 20 06:47:37 PM PDT 24
Finished Jul 20 06:47:46 PM PDT 24
Peak memory 213572 kb
Host smart-aa2e6380-5ff5-44ba-8378-9ac842c81ac5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2140197026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2140197026
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.246587858
Short name T129
Test name
Test status
Simulation time 7018340672 ps
CPU time 7.52 seconds
Started Jul 20 06:47:39 PM PDT 24
Finished Jul 20 06:47:48 PM PDT 24
Peak memory 205560 kb
Host smart-d27d9576-f7ad-46b2-bf09-df2820c7b93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246587858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.246587858
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.310054460
Short name T283
Test name
Test status
Simulation time 2683837583 ps
CPU time 2.63 seconds
Started Jul 20 06:47:37 PM PDT 24
Finished Jul 20 06:47:40 PM PDT 24
Peak memory 205216 kb
Host smart-336b4038-7a86-464e-8752-97af16ac34e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310054460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.310054460
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2693759695
Short name T198
Test name
Test status
Simulation time 216789576 ps
CPU time 0.82 seconds
Started Jul 20 06:47:39 PM PDT 24
Finished Jul 20 06:47:41 PM PDT 24
Peak memory 204988 kb
Host smart-c0d9c0cc-96cc-4d1c-966c-ed5e8d22e33c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693759695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2693759695
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3943584354
Short name T221
Test name
Test status
Simulation time 7305752279 ps
CPU time 5.32 seconds
Started Jul 20 06:47:42 PM PDT 24
Finished Jul 20 06:47:48 PM PDT 24
Peak memory 215376 kb
Host smart-6335a5e6-58f5-48da-ab3c-847c1e6bc0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943584354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3943584354
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.836713506
Short name T132
Test name
Test status
Simulation time 17504616285 ps
CPU time 50.13 seconds
Started Jul 20 06:47:38 PM PDT 24
Finished Jul 20 06:48:29 PM PDT 24
Peak memory 213656 kb
Host smart-6e4fb0ba-25c2-45e2-825e-ce84aa982bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836713506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.836713506
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.503442184
Short name T218
Test name
Test status
Simulation time 7183148589 ps
CPU time 19.69 seconds
Started Jul 20 06:47:37 PM PDT 24
Finished Jul 20 06:47:57 PM PDT 24
Peak memory 213696 kb
Host smart-4048d79c-b28d-4aa3-8548-18b51b75bc84
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503442184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.503442184
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1839683580
Short name T274
Test name
Test status
Simulation time 3091859074 ps
CPU time 8.73 seconds
Started Jul 20 06:47:40 PM PDT 24
Finished Jul 20 06:47:50 PM PDT 24
Peak memory 205524 kb
Host smart-06780adf-a64d-4e7b-982a-123e2c68628f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839683580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1839683580
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1732144825
Short name T185
Test name
Test status
Simulation time 74710605 ps
CPU time 0.88 seconds
Started Jul 20 06:47:50 PM PDT 24
Finished Jul 20 06:47:53 PM PDT 24
Peak memory 205016 kb
Host smart-69746c94-0291-468d-a6b4-6e9e6fc26f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732144825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1732144825
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3141519687
Short name T184
Test name
Test status
Simulation time 6036160085 ps
CPU time 15.44 seconds
Started Jul 20 06:47:39 PM PDT 24
Finished Jul 20 06:47:56 PM PDT 24
Peak memory 213720 kb
Host smart-53d7125c-6e50-488a-9cc4-d999570556af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141519687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3141519687
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3549952840
Short name T27
Test name
Test status
Simulation time 8211611052 ps
CPU time 7.2 seconds
Started Jul 20 06:47:37 PM PDT 24
Finished Jul 20 06:47:45 PM PDT 24
Peak memory 213676 kb
Host smart-571e52e9-2b27-4e68-a997-9a3aedb7544f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549952840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3549952840
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1109254134
Short name T212
Test name
Test status
Simulation time 2746931076 ps
CPU time 5.51 seconds
Started Jul 20 06:47:39 PM PDT 24
Finished Jul 20 06:47:46 PM PDT 24
Peak memory 213620 kb
Host smart-5f8f9c36-124b-4389-9149-cf41c5a80f64
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1109254134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1109254134
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.133567161
Short name T229
Test name
Test status
Simulation time 1637257953 ps
CPU time 1.95 seconds
Started Jul 20 06:47:39 PM PDT 24
Finished Jul 20 06:47:42 PM PDT 24
Peak memory 205312 kb
Host smart-482b9cba-a793-4d05-b772-e45fcf14f272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133567161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.133567161
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.426844836
Short name T141
Test name
Test status
Simulation time 2368168607 ps
CPU time 1.85 seconds
Started Jul 20 06:47:38 PM PDT 24
Finished Jul 20 06:47:41 PM PDT 24
Peak memory 213476 kb
Host smart-d278b81a-21bb-4582-8c59-56b582d598e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426844836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.426844836
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.615977572
Short name T190
Test name
Test status
Simulation time 142635613 ps
CPU time 0.81 seconds
Started Jul 20 06:47:48 PM PDT 24
Finished Jul 20 06:47:51 PM PDT 24
Peak memory 204928 kb
Host smart-ae9293cb-3929-4422-aea8-aa765560597f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615977572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.615977572
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.4092026608
Short name T188
Test name
Test status
Simulation time 18200533649 ps
CPU time 9.62 seconds
Started Jul 20 06:47:45 PM PDT 24
Finished Jul 20 06:47:55 PM PDT 24
Peak memory 213692 kb
Host smart-5731a5f6-07e9-4fb3-ac71-105f86c71c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092026608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.4092026608
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.767044919
Short name T277
Test name
Test status
Simulation time 1682503018 ps
CPU time 3.1 seconds
Started Jul 20 06:47:47 PM PDT 24
Finished Jul 20 06:47:51 PM PDT 24
Peak memory 205352 kb
Host smart-4b178bad-11e7-4fdc-9fec-a7f424ead6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767044919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.767044919
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1874874320
Short name T66
Test name
Test status
Simulation time 5887633013 ps
CPU time 13.52 seconds
Started Jul 20 06:47:51 PM PDT 24
Finished Jul 20 06:48:06 PM PDT 24
Peak memory 213652 kb
Host smart-f108f536-1b0b-479b-8a94-8ce336f7d1aa
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1874874320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.1874874320
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.2836946372
Short name T57
Test name
Test status
Simulation time 2702314800 ps
CPU time 3.82 seconds
Started Jul 20 06:47:45 PM PDT 24
Finished Jul 20 06:47:49 PM PDT 24
Peak memory 205504 kb
Host smart-a2882d47-6e55-42dd-a969-f992194415b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836946372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2836946372
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.2628647008
Short name T237
Test name
Test status
Simulation time 3690639627 ps
CPU time 12.02 seconds
Started Jul 20 06:47:46 PM PDT 24
Finished Jul 20 06:47:59 PM PDT 24
Peak memory 213524 kb
Host smart-665128d9-5eb8-4237-a45b-0717eeb59240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628647008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2628647008
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1501719271
Short name T191
Test name
Test status
Simulation time 95272765 ps
CPU time 0.74 seconds
Started Jul 20 06:47:46 PM PDT 24
Finished Jul 20 06:47:48 PM PDT 24
Peak memory 204916 kb
Host smart-a4ac460d-c181-4c77-8606-6f8ec4ca04ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501719271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1501719271
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1506403533
Short name T31
Test name
Test status
Simulation time 10967140491 ps
CPU time 16.81 seconds
Started Jul 20 06:47:46 PM PDT 24
Finished Jul 20 06:48:05 PM PDT 24
Peak memory 213592 kb
Host smart-34687623-20f2-49ec-956d-7623c2dc46dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506403533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1506403533
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2876490059
Short name T255
Test name
Test status
Simulation time 1530723339 ps
CPU time 3.05 seconds
Started Jul 20 06:47:46 PM PDT 24
Finished Jul 20 06:47:50 PM PDT 24
Peak memory 205340 kb
Host smart-a66bfd28-2ed6-4a98-8384-8dd034f5c66b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876490059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2876490059
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1296322516
Short name T137
Test name
Test status
Simulation time 2020886268 ps
CPU time 2.08 seconds
Started Jul 20 06:47:48 PM PDT 24
Finished Jul 20 06:47:52 PM PDT 24
Peak memory 205400 kb
Host smart-84d29a73-e3d9-4538-837c-a80efcf91144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296322516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1296322516
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.757897833
Short name T259
Test name
Test status
Simulation time 10242701497 ps
CPU time 28.87 seconds
Started Jul 20 06:47:46 PM PDT 24
Finished Jul 20 06:48:15 PM PDT 24
Peak memory 213564 kb
Host smart-481b8f7f-891d-48f6-aa5d-ea756fb686c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757897833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.757897833
Directory /workspace/9.rv_dm_stress_all/latest
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