Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.83 95.57 81.38 89.91 75.00 86.33 98.53 53.09


Total test records in report: 433
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T290 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.309697103 Jul 22 05:45:21 PM PDT 24 Jul 22 05:45:30 PM PDT 24 3983973286 ps
T291 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1151574243 Jul 22 05:45:31 PM PDT 24 Jul 22 05:45:34 PM PDT 24 240618966 ps
T142 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.176126829 Jul 22 05:45:22 PM PDT 24 Jul 22 05:45:35 PM PDT 24 3937286749 ps
T292 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1159567351 Jul 22 05:45:03 PM PDT 24 Jul 22 05:45:05 PM PDT 24 329028357 ps
T97 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.632938999 Jul 22 05:45:22 PM PDT 24 Jul 22 05:45:26 PM PDT 24 155875795 ps
T293 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.573441957 Jul 22 05:45:20 PM PDT 24 Jul 22 05:45:23 PM PDT 24 628128319 ps
T294 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3563778956 Jul 22 05:45:04 PM PDT 24 Jul 22 05:45:06 PM PDT 24 130146124 ps
T295 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3691259281 Jul 22 05:45:23 PM PDT 24 Jul 22 05:45:50 PM PDT 24 8345956416 ps
T113 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.756404951 Jul 22 05:45:34 PM PDT 24 Jul 22 05:45:40 PM PDT 24 729211973 ps
T296 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1723825695 Jul 22 05:45:18 PM PDT 24 Jul 22 05:45:20 PM PDT 24 399492822 ps
T98 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3698299141 Jul 22 05:45:44 PM PDT 24 Jul 22 05:45:49 PM PDT 24 287706738 ps
T297 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2245381297 Jul 22 05:48:19 PM PDT 24 Jul 22 05:48:21 PM PDT 24 179327722 ps
T298 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3823679745 Jul 22 05:45:03 PM PDT 24 Jul 22 05:45:06 PM PDT 24 343827930 ps
T299 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1680760697 Jul 22 05:45:34 PM PDT 24 Jul 22 05:45:38 PM PDT 24 1482891270 ps
T300 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1120681866 Jul 22 05:45:14 PM PDT 24 Jul 22 05:45:51 PM PDT 24 13406029983 ps
T301 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1635619155 Jul 22 05:45:41 PM PDT 24 Jul 22 05:45:45 PM PDT 24 217025602 ps
T302 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2843957315 Jul 22 05:45:25 PM PDT 24 Jul 22 05:45:30 PM PDT 24 3544422148 ps
T303 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.144255284 Jul 22 05:45:32 PM PDT 24 Jul 22 05:45:36 PM PDT 24 117495052 ps
T304 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2820324111 Jul 22 05:45:41 PM PDT 24 Jul 22 05:45:45 PM PDT 24 628957679 ps
T122 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2604153597 Jul 22 05:45:23 PM PDT 24 Jul 22 05:49:00 PM PDT 24 49913340987 ps
T114 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2395097126 Jul 22 05:45:34 PM PDT 24 Jul 22 05:45:39 PM PDT 24 334305329 ps
T305 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1238601190 Jul 22 05:45:33 PM PDT 24 Jul 22 05:45:36 PM PDT 24 449646591 ps
T306 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2147149557 Jul 22 05:45:04 PM PDT 24 Jul 22 05:45:17 PM PDT 24 3407606070 ps
T307 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.519398519 Jul 22 05:45:06 PM PDT 24 Jul 22 05:46:57 PM PDT 24 68280599434 ps
T104 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3699912542 Jul 22 05:45:35 PM PDT 24 Jul 22 05:45:38 PM PDT 24 428695903 ps
T308 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3562056416 Jul 22 05:45:14 PM PDT 24 Jul 22 05:46:35 PM PDT 24 29139312758 ps
T99 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.271640873 Jul 22 05:45:24 PM PDT 24 Jul 22 05:45:27 PM PDT 24 137172185 ps
T309 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2296983636 Jul 22 05:45:35 PM PDT 24 Jul 22 05:46:15 PM PDT 24 13574831912 ps
T105 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.769662949 Jul 22 05:45:44 PM PDT 24 Jul 22 05:45:47 PM PDT 24 184520040 ps
T310 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3079627985 Jul 22 05:45:21 PM PDT 24 Jul 22 05:45:24 PM PDT 24 110718458 ps
T152 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2683228908 Jul 22 05:48:00 PM PDT 24 Jul 22 05:52:00 PM PDT 24 50821810952 ps
T106 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3160937167 Jul 22 05:45:20 PM PDT 24 Jul 22 05:45:22 PM PDT 24 163049692 ps
T100 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3380867259 Jul 22 05:45:13 PM PDT 24 Jul 22 05:45:17 PM PDT 24 191786157 ps
T311 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2230548886 Jul 22 05:45:33 PM PDT 24 Jul 22 05:45:37 PM PDT 24 5866082404 ps
T115 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1139795240 Jul 22 05:45:35 PM PDT 24 Jul 22 05:45:40 PM PDT 24 170232048 ps
T312 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.283128666 Jul 22 05:45:15 PM PDT 24 Jul 22 05:45:17 PM PDT 24 510542569 ps
T313 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3106074616 Jul 22 05:45:14 PM PDT 24 Jul 22 05:46:31 PM PDT 24 109138755767 ps
T314 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4116293660 Jul 22 05:45:04 PM PDT 24 Jul 22 05:45:08 PM PDT 24 536657560 ps
T315 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2112212511 Jul 22 05:45:14 PM PDT 24 Jul 22 05:45:16 PM PDT 24 33373899 ps
T316 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4026958548 Jul 22 05:45:34 PM PDT 24 Jul 22 05:46:11 PM PDT 24 11872811219 ps
T317 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.681569486 Jul 22 05:48:20 PM PDT 24 Jul 22 05:48:37 PM PDT 24 5756595308 ps
T318 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1206930603 Jul 22 05:45:23 PM PDT 24 Jul 22 05:45:54 PM PDT 24 23998922242 ps
T91 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2078686316 Jul 22 05:45:03 PM PDT 24 Jul 22 05:45:11 PM PDT 24 6772710515 ps
T319 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3323372285 Jul 22 05:45:21 PM PDT 24 Jul 22 05:45:26 PM PDT 24 97979219 ps
T107 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3671305128 Jul 22 05:45:13 PM PDT 24 Jul 22 05:45:16 PM PDT 24 253932844 ps
T101 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4120412544 Jul 22 05:45:31 PM PDT 24 Jul 22 05:45:38 PM PDT 24 418978714 ps
T153 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.518533453 Jul 22 05:45:14 PM PDT 24 Jul 22 05:45:46 PM PDT 24 17685926874 ps
T320 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1346575590 Jul 22 05:45:01 PM PDT 24 Jul 22 05:45:28 PM PDT 24 818869020 ps
T321 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.692435575 Jul 22 05:45:14 PM PDT 24 Jul 22 05:45:16 PM PDT 24 764715682 ps
T322 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1931152394 Jul 22 05:45:41 PM PDT 24 Jul 22 05:45:45 PM PDT 24 219220548 ps
T323 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.23541368 Jul 22 05:45:37 PM PDT 24 Jul 22 05:45:44 PM PDT 24 3492967553 ps
T324 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1658139754 Jul 22 05:45:34 PM PDT 24 Jul 22 05:45:40 PM PDT 24 387485445 ps
T110 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2101478458 Jul 22 05:45:06 PM PDT 24 Jul 22 05:45:08 PM PDT 24 69174521 ps
T325 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3146520152 Jul 22 05:45:01 PM PDT 24 Jul 22 05:45:03 PM PDT 24 93406711 ps
T326 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1648182322 Jul 22 05:45:32 PM PDT 24 Jul 22 05:46:38 PM PDT 24 27639219446 ps
T116 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4216348547 Jul 22 05:46:40 PM PDT 24 Jul 22 05:46:46 PM PDT 24 212346564 ps
T327 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.122990463 Jul 22 05:45:22 PM PDT 24 Jul 22 05:45:30 PM PDT 24 1105079445 ps
T328 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1985257177 Jul 22 05:45:34 PM PDT 24 Jul 22 05:45:39 PM PDT 24 4679694305 ps
T146 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2998596106 Jul 22 05:48:18 PM PDT 24 Jul 22 05:48:38 PM PDT 24 4113745610 ps
T329 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.525393696 Jul 22 05:45:01 PM PDT 24 Jul 22 05:45:06 PM PDT 24 4147167615 ps
T330 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1464383365 Jul 22 05:45:02 PM PDT 24 Jul 22 05:45:17 PM PDT 24 2609233794 ps
T151 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1687251635 Jul 22 05:45:20 PM PDT 24 Jul 22 05:45:37 PM PDT 24 2032376133 ps
T331 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3006733009 Jul 22 05:45:04 PM PDT 24 Jul 22 05:45:17 PM PDT 24 15748026319 ps
T332 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1694008690 Jul 22 05:45:11 PM PDT 24 Jul 22 05:45:16 PM PDT 24 5749383893 ps
T333 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3232264513 Jul 22 05:45:14 PM PDT 24 Jul 22 05:45:15 PM PDT 24 90983662 ps
T334 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2097094496 Jul 22 05:45:03 PM PDT 24 Jul 22 05:45:31 PM PDT 24 628679747 ps
T335 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.894441211 Jul 22 05:45:23 PM PDT 24 Jul 22 05:45:25 PM PDT 24 697270434 ps
T336 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3196423295 Jul 22 05:45:07 PM PDT 24 Jul 22 05:45:19 PM PDT 24 7496933052 ps
T117 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.698548361 Jul 22 05:45:45 PM PDT 24 Jul 22 05:45:52 PM PDT 24 273924305 ps
T337 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4121305549 Jul 22 05:45:29 PM PDT 24 Jul 22 05:45:32 PM PDT 24 90133841 ps
T112 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1363319842 Jul 22 05:45:50 PM PDT 24 Jul 22 05:45:53 PM PDT 24 200891142 ps
T338 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.520258052 Jul 22 05:45:28 PM PDT 24 Jul 22 05:45:32 PM PDT 24 2526738483 ps
T339 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2966266362 Jul 22 05:45:23 PM PDT 24 Jul 22 05:45:25 PM PDT 24 154645145 ps
T147 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1214861865 Jul 22 05:45:10 PM PDT 24 Jul 22 05:45:38 PM PDT 24 5156541344 ps
T340 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1992237609 Jul 22 05:45:31 PM PDT 24 Jul 22 05:45:33 PM PDT 24 153259676 ps
T341 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3957972474 Jul 22 05:45:22 PM PDT 24 Jul 22 05:45:24 PM PDT 24 61260276 ps
T143 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1691296659 Jul 22 05:45:43 PM PDT 24 Jul 22 05:45:59 PM PDT 24 2974716748 ps
T342 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1810942078 Jul 22 05:45:07 PM PDT 24 Jul 22 05:45:08 PM PDT 24 176496979 ps
T343 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3371757634 Jul 22 05:45:21 PM PDT 24 Jul 22 05:45:27 PM PDT 24 4079902542 ps
T344 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.330925828 Jul 22 05:45:27 PM PDT 24 Jul 22 05:45:32 PM PDT 24 5928855935 ps
T102 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4173867566 Jul 22 05:45:44 PM PDT 24 Jul 22 05:45:53 PM PDT 24 1590088734 ps
T111 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4076023944 Jul 22 05:45:22 PM PDT 24 Jul 22 05:45:25 PM PDT 24 143168792 ps
T345 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.80849471 Jul 22 05:45:21 PM PDT 24 Jul 22 05:45:25 PM PDT 24 171760539 ps
T346 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.511357584 Jul 22 05:45:21 PM PDT 24 Jul 22 05:45:23 PM PDT 24 33873991 ps
T103 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1805486376 Jul 22 05:45:12 PM PDT 24 Jul 22 05:45:17 PM PDT 24 1948629753 ps
T347 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2037324409 Jul 22 05:45:12 PM PDT 24 Jul 22 05:46:17 PM PDT 24 4299421188 ps
T348 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.576091457 Jul 22 05:45:28 PM PDT 24 Jul 22 05:45:33 PM PDT 24 2680852564 ps
T349 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3872614199 Jul 22 05:45:01 PM PDT 24 Jul 22 05:45:06 PM PDT 24 206177201 ps
T108 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4149343267 Jul 22 05:45:04 PM PDT 24 Jul 22 05:46:14 PM PDT 24 1201340515 ps
T109 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.258886977 Jul 22 05:45:38 PM PDT 24 Jul 22 05:45:41 PM PDT 24 56525010 ps
T92 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.123907128 Jul 22 05:45:11 PM PDT 24 Jul 22 05:45:15 PM PDT 24 3304094261 ps
T350 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.169542672 Jul 22 05:45:21 PM PDT 24 Jul 22 05:45:29 PM PDT 24 313675551 ps
T351 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2886398806 Jul 22 05:45:45 PM PDT 24 Jul 22 05:45:47 PM PDT 24 443293804 ps
T352 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.409666766 Jul 22 05:45:21 PM PDT 24 Jul 22 05:46:03 PM PDT 24 53176126285 ps
T144 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.340117822 Jul 22 05:48:06 PM PDT 24 Jul 22 05:48:29 PM PDT 24 3384298385 ps
T353 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1334597537 Jul 22 05:45:35 PM PDT 24 Jul 22 05:45:39 PM PDT 24 197893366 ps
T354 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.621576831 Jul 22 05:45:10 PM PDT 24 Jul 22 05:45:17 PM PDT 24 322361437 ps
T355 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3985840627 Jul 22 05:45:07 PM PDT 24 Jul 22 05:45:27 PM PDT 24 16092053069 ps
T93 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.902590164 Jul 22 05:45:02 PM PDT 24 Jul 22 05:45:08 PM PDT 24 2647337393 ps
T356 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.21691038 Jul 22 05:45:32 PM PDT 24 Jul 22 05:45:34 PM PDT 24 313224355 ps
T357 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1703403987 Jul 22 05:45:20 PM PDT 24 Jul 22 05:45:23 PM PDT 24 172827564 ps
T358 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1149926932 Jul 22 05:45:33 PM PDT 24 Jul 22 05:45:59 PM PDT 24 9198051789 ps
T145 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.231582488 Jul 22 05:45:20 PM PDT 24 Jul 22 05:45:33 PM PDT 24 3421154713 ps
T359 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2154037228 Jul 22 05:45:02 PM PDT 24 Jul 22 05:46:37 PM PDT 24 64761394052 ps
T360 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1247300529 Jul 22 05:45:11 PM PDT 24 Jul 22 05:45:14 PM PDT 24 168449342 ps
T361 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.102985197 Jul 22 05:45:23 PM PDT 24 Jul 22 05:45:30 PM PDT 24 1751528752 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.329018524 Jul 22 05:45:02 PM PDT 24 Jul 22 05:45:30 PM PDT 24 1588842630 ps
T363 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2318631830 Jul 22 05:45:02 PM PDT 24 Jul 22 05:45:23 PM PDT 24 7148820769 ps
T364 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.901475284 Jul 22 05:45:24 PM PDT 24 Jul 22 05:45:32 PM PDT 24 479369097 ps
T365 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2933605753 Jul 22 05:45:02 PM PDT 24 Jul 22 05:45:05 PM PDT 24 328422862 ps
T148 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.123048953 Jul 22 05:45:21 PM PDT 24 Jul 22 05:45:34 PM PDT 24 1854416933 ps
T366 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3459307267 Jul 22 05:45:41 PM PDT 24 Jul 22 05:45:44 PM PDT 24 263273623 ps
T367 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1706986810 Jul 22 05:45:01 PM PDT 24 Jul 22 05:45:10 PM PDT 24 2044844430 ps
T368 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2923766374 Jul 22 05:45:13 PM PDT 24 Jul 22 05:45:17 PM PDT 24 3396325070 ps
T94 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3413119347 Jul 22 05:45:02 PM PDT 24 Jul 22 05:45:10 PM PDT 24 4251730655 ps
T369 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.386109348 Jul 22 05:46:40 PM PDT 24 Jul 22 05:46:55 PM PDT 24 2999727180 ps
T370 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3214656688 Jul 22 05:47:49 PM PDT 24 Jul 22 05:47:57 PM PDT 24 2335678853 ps
T371 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1391630703 Jul 22 05:45:10 PM PDT 24 Jul 22 05:46:18 PM PDT 24 23664262286 ps
T372 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1226692331 Jul 22 05:45:38 PM PDT 24 Jul 22 05:46:06 PM PDT 24 7016767079 ps
T373 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3047515529 Jul 22 05:45:02 PM PDT 24 Jul 22 05:45:04 PM PDT 24 94687556 ps
T374 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.238823568 Jul 22 05:45:43 PM PDT 24 Jul 22 05:46:03 PM PDT 24 6927565433 ps
T375 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2388532317 Jul 22 05:45:06 PM PDT 24 Jul 22 05:45:07 PM PDT 24 63440952 ps
T376 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.626523410 Jul 22 05:45:32 PM PDT 24 Jul 22 05:45:36 PM PDT 24 208919928 ps
T377 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4216992962 Jul 22 05:45:33 PM PDT 24 Jul 22 05:45:35 PM PDT 24 210450514 ps
T378 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3545993593 Jul 22 05:45:20 PM PDT 24 Jul 22 05:45:38 PM PDT 24 9590007215 ps
T379 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.624736074 Jul 22 05:47:49 PM PDT 24 Jul 22 05:47:53 PM PDT 24 157830717 ps
T380 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2520134590 Jul 22 05:45:06 PM PDT 24 Jul 22 05:45:10 PM PDT 24 900502263 ps
T381 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2441864078 Jul 22 05:45:41 PM PDT 24 Jul 22 05:45:43 PM PDT 24 1097792413 ps
T382 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2682772138 Jul 22 05:45:12 PM PDT 24 Jul 22 05:45:14 PM PDT 24 285178802 ps
T383 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.809929732 Jul 22 05:45:15 PM PDT 24 Jul 22 05:45:16 PM PDT 24 36997581 ps
T384 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1843417882 Jul 22 05:48:20 PM PDT 24 Jul 22 05:48:21 PM PDT 24 336098067 ps
T385 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3713168809 Jul 22 05:45:13 PM PDT 24 Jul 22 05:45:17 PM PDT 24 142370585 ps
T386 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1624025503 Jul 22 05:45:11 PM PDT 24 Jul 22 05:48:23 PM PDT 24 143183460240 ps
T387 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1761003207 Jul 22 05:45:35 PM PDT 24 Jul 22 05:45:40 PM PDT 24 113060525 ps
T388 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4109020286 Jul 22 05:45:12 PM PDT 24 Jul 22 05:45:50 PM PDT 24 70891869664 ps
T389 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.861398368 Jul 22 05:45:11 PM PDT 24 Jul 22 05:45:38 PM PDT 24 25614302677 ps
T390 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.306528781 Jul 22 05:45:45 PM PDT 24 Jul 22 05:45:51 PM PDT 24 839270327 ps
T391 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2405879273 Jul 22 05:45:04 PM PDT 24 Jul 22 05:45:06 PM PDT 24 383723483 ps
T392 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2138994757 Jul 22 05:45:03 PM PDT 24 Jul 22 05:50:45 PM PDT 24 227100082807 ps
T393 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2568325280 Jul 22 05:45:43 PM PDT 24 Jul 22 05:45:53 PM PDT 24 1108942255 ps
T150 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.224211023 Jul 22 05:45:04 PM PDT 24 Jul 22 05:45:14 PM PDT 24 2072852221 ps
T394 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1552812955 Jul 22 05:45:03 PM PDT 24 Jul 22 05:45:39 PM PDT 24 8744948235 ps
T395 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.734096126 Jul 22 05:45:10 PM PDT 24 Jul 22 05:45:12 PM PDT 24 461712308 ps
T396 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3780379828 Jul 22 05:45:45 PM PDT 24 Jul 22 05:45:47 PM PDT 24 291163438 ps
T397 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3584407510 Jul 22 05:45:11 PM PDT 24 Jul 22 05:45:47 PM PDT 24 14630437454 ps
T398 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2670687537 Jul 22 05:45:21 PM PDT 24 Jul 22 05:45:24 PM PDT 24 806268274 ps
T399 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3586070503 Jul 22 05:45:12 PM PDT 24 Jul 22 05:45:38 PM PDT 24 27319177351 ps
T400 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1705087649 Jul 22 05:45:32 PM PDT 24 Jul 22 05:45:36 PM PDT 24 218176722 ps
T401 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3416334183 Jul 22 05:45:03 PM PDT 24 Jul 22 05:45:07 PM PDT 24 320697548 ps
T402 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1787460585 Jul 22 05:45:03 PM PDT 24 Jul 22 05:45:06 PM PDT 24 129992982 ps
T403 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2415003862 Jul 22 05:45:11 PM PDT 24 Jul 22 05:48:43 PM PDT 24 56797659460 ps
T404 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3119484478 Jul 22 05:45:19 PM PDT 24 Jul 22 05:45:21 PM PDT 24 186978781 ps
T405 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1186364897 Jul 22 05:45:23 PM PDT 24 Jul 22 05:45:31 PM PDT 24 6844399961 ps
T406 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.177176334 Jul 22 05:45:10 PM PDT 24 Jul 22 05:45:14 PM PDT 24 5313888927 ps
T407 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.698565952 Jul 22 05:45:12 PM PDT 24 Jul 22 05:45:15 PM PDT 24 156707787 ps
T408 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3842696329 Jul 22 05:45:38 PM PDT 24 Jul 22 05:45:58 PM PDT 24 3576295653 ps
T149 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3235791971 Jul 22 05:45:33 PM PDT 24 Jul 22 05:45:51 PM PDT 24 5804656571 ps
T409 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2121275668 Jul 22 05:45:42 PM PDT 24 Jul 22 05:45:45 PM PDT 24 346812316 ps
T410 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.561907241 Jul 22 05:48:00 PM PDT 24 Jul 22 05:50:10 PM PDT 24 42884902979 ps
T95 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3028723485 Jul 22 05:45:04 PM PDT 24 Jul 22 05:45:15 PM PDT 24 6425100821 ps
T411 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1310075434 Jul 22 05:45:15 PM PDT 24 Jul 22 05:45:23 PM PDT 24 4051136490 ps
T412 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2302742419 Jul 22 05:45:14 PM PDT 24 Jul 22 05:45:15 PM PDT 24 474285563 ps
T413 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3458892587 Jul 22 05:45:14 PM PDT 24 Jul 22 05:45:28 PM PDT 24 4777323632 ps
T414 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1257313765 Jul 22 05:48:19 PM PDT 24 Jul 22 05:48:25 PM PDT 24 103858390 ps
T415 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1752027434 Jul 22 05:45:02 PM PDT 24 Jul 22 05:45:05 PM PDT 24 352202652 ps
T416 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.484897878 Jul 22 05:45:32 PM PDT 24 Jul 22 05:45:37 PM PDT 24 3483320794 ps
T417 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4110535155 Jul 22 05:45:32 PM PDT 24 Jul 22 05:45:36 PM PDT 24 174436655 ps
T418 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3215953014 Jul 22 05:45:01 PM PDT 24 Jul 22 05:45:04 PM PDT 24 1085194335 ps
T419 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2114487406 Jul 22 05:45:34 PM PDT 24 Jul 22 05:45:36 PM PDT 24 59335539 ps
T420 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.954448169 Jul 22 05:45:34 PM PDT 24 Jul 22 05:45:40 PM PDT 24 341879750 ps
T421 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2375009523 Jul 22 05:47:48 PM PDT 24 Jul 22 05:48:11 PM PDT 24 74163986469 ps
T422 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.751160077 Jul 22 05:45:22 PM PDT 24 Jul 22 05:45:25 PM PDT 24 417854841 ps
T423 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.674807725 Jul 22 05:45:33 PM PDT 24 Jul 22 05:45:41 PM PDT 24 8503707763 ps
T424 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3640674171 Jul 22 05:45:23 PM PDT 24 Jul 22 05:45:28 PM PDT 24 1189116650 ps
T425 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2620131256 Jul 22 05:45:34 PM PDT 24 Jul 22 05:45:50 PM PDT 24 5292065660 ps
T426 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1685721410 Jul 22 05:45:07 PM PDT 24 Jul 22 05:45:08 PM PDT 24 139639036 ps
T427 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.551083017 Jul 22 05:48:18 PM PDT 24 Jul 22 05:48:21 PM PDT 24 173009568 ps
T428 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2720676767 Jul 22 05:45:30 PM PDT 24 Jul 22 05:45:33 PM PDT 24 161988180 ps
T429 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3058912562 Jul 22 05:45:11 PM PDT 24 Jul 22 05:45:14 PM PDT 24 242656834 ps
T430 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3684560481 Jul 22 05:45:05 PM PDT 24 Jul 22 05:45:07 PM PDT 24 348187216 ps
T431 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.548558856 Jul 22 05:45:04 PM PDT 24 Jul 22 05:45:07 PM PDT 24 184971562 ps
T432 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3562390054 Jul 22 05:45:40 PM PDT 24 Jul 22 05:45:46 PM PDT 24 784762439 ps
T433 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1217922489 Jul 22 05:45:05 PM PDT 24 Jul 22 05:45:08 PM PDT 24 396561858 ps

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3970594355
Short name T10
Test name
Test status
Simulation time 7567055420 ps
CPU time 18.71 seconds
Started Jul 22 05:46:24 PM PDT 24
Finished Jul 22 05:46:43 PM PDT 24
Peak memory 213452 kb
Host smart-dfc389f8-72b0-4ae0-af80-ceb06e0192dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970594355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3970594355
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.3021334264
Short name T6
Test name
Test status
Simulation time 7484779335 ps
CPU time 3.13 seconds
Started Jul 22 05:46:22 PM PDT 24
Finished Jul 22 05:46:26 PM PDT 24
Peak memory 213176 kb
Host smart-9033a324-bc3a-498d-8c55-0985d510b8f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021334264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3021334264
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1952379555
Short name T58
Test name
Test status
Simulation time 33758587331 ps
CPU time 319.91 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:50:23 PM PDT 24
Peak memory 216816 kb
Host smart-48d2d594-d07f-406e-9721-522fdbe690ac
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952379555 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1952379555
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.3172708108
Short name T5
Test name
Test status
Simulation time 4682856009 ps
CPU time 2.13 seconds
Started Jul 22 05:46:22 PM PDT 24
Finished Jul 22 05:46:25 PM PDT 24
Peak memory 213144 kb
Host smart-38ca473c-744b-4933-aaf6-405965d53fa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172708108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3172708108
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4256202197
Short name T57
Test name
Test status
Simulation time 2372704542 ps
CPU time 18.27 seconds
Started Jul 22 05:45:32 PM PDT 24
Finished Jul 22 05:45:52 PM PDT 24
Peak memory 213316 kb
Host smart-0ae24c05-d719-4d69-b696-b56bd03f08c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256202197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.4
256202197
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3288728636
Short name T221
Test name
Test status
Simulation time 26993892775 ps
CPU time 73.6 seconds
Started Jul 22 05:45:50 PM PDT 24
Finished Jul 22 05:47:04 PM PDT 24
Peak memory 213400 kb
Host smart-9ad3227e-6314-445e-84d4-ff7e9eacbb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288728636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3288728636
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1249127722
Short name T55
Test name
Test status
Simulation time 65598608 ps
CPU time 0.81 seconds
Started Jul 22 05:46:27 PM PDT 24
Finished Jul 22 05:46:28 PM PDT 24
Peak memory 204672 kb
Host smart-0ae1f6e6-0dee-4aae-b1e7-e120d4e13e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249127722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1249127722
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3528462167
Short name T29
Test name
Test status
Simulation time 122635744 ps
CPU time 0.86 seconds
Started Jul 22 05:45:47 PM PDT 24
Finished Jul 22 05:45:49 PM PDT 24
Peak memory 204632 kb
Host smart-77156df2-3d38-4f53-9ba0-8ac72fab844a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528462167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3528462167
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.3507153494
Short name T13
Test name
Test status
Simulation time 11811084209 ps
CPU time 6.39 seconds
Started Jul 22 05:46:01 PM PDT 24
Finished Jul 22 05:46:08 PM PDT 24
Peak memory 213156 kb
Host smart-13fff542-749a-4163-b4ba-69ea458b8173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507153494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3507153494
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2694267869
Short name T22
Test name
Test status
Simulation time 601706694 ps
CPU time 1.11 seconds
Started Jul 22 05:45:46 PM PDT 24
Finished Jul 22 05:45:48 PM PDT 24
Peak memory 204712 kb
Host smart-94f7bbf5-5a28-49b7-9404-dd6284c1ad9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694267869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2694267869
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.3403945570
Short name T16
Test name
Test status
Simulation time 2450767577 ps
CPU time 7.76 seconds
Started Jul 22 05:46:21 PM PDT 24
Finished Jul 22 05:46:30 PM PDT 24
Peak memory 204948 kb
Host smart-991e60ff-052a-4324-9e94-eb2834d5634a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403945570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.3403945570
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.271640873
Short name T99
Test name
Test status
Simulation time 137172185 ps
CPU time 2.25 seconds
Started Jul 22 05:45:24 PM PDT 24
Finished Jul 22 05:45:27 PM PDT 24
Peak memory 213192 kb
Host smart-26b2b0a4-d74e-48bd-b829-f60626fc4211
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271640873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.271640873
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.1146040613
Short name T71
Test name
Test status
Simulation time 44891927 ps
CPU time 0.96 seconds
Started Jul 22 05:47:44 PM PDT 24
Finished Jul 22 05:47:45 PM PDT 24
Peak memory 214936 kb
Host smart-23467d34-8835-4351-8e84-e169c19a0355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146040613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.1146040613
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2043451595
Short name T70
Test name
Test status
Simulation time 2776685825 ps
CPU time 8.13 seconds
Started Jul 22 05:45:53 PM PDT 24
Finished Jul 22 05:46:02 PM PDT 24
Peak memory 205012 kb
Host smart-7fd20588-6b2f-4850-8b6b-52ea0ddef7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043451595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2043451595
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1326716744
Short name T35
Test name
Test status
Simulation time 276665775 ps
CPU time 0.9 seconds
Started Jul 22 05:45:50 PM PDT 24
Finished Jul 22 05:45:52 PM PDT 24
Peak memory 212988 kb
Host smart-d8aec9ed-16c2-432f-ac60-2a1a174f9493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326716744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1326716744
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.761758970
Short name T43
Test name
Test status
Simulation time 395843004 ps
CPU time 1.59 seconds
Started Jul 22 05:45:51 PM PDT 24
Finished Jul 22 05:45:54 PM PDT 24
Peak memory 228436 kb
Host smart-90b9d519-e9a5-456b-a86d-bd3d487ef6e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761758970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.761758970
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.882596893
Short name T127
Test name
Test status
Simulation time 7776911051 ps
CPU time 11.26 seconds
Started Jul 22 05:46:07 PM PDT 24
Finished Jul 22 05:46:20 PM PDT 24
Peak memory 213408 kb
Host smart-b3a4ae21-350b-4331-b74e-c63a86aad381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882596893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.882596893
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.2383049676
Short name T46
Test name
Test status
Simulation time 103463893 ps
CPU time 0.76 seconds
Started Jul 22 05:45:46 PM PDT 24
Finished Jul 22 05:45:48 PM PDT 24
Peak memory 204692 kb
Host smart-13f905d1-8a09-45b7-9fb8-39d2af5369a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383049676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2383049676
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.340117822
Short name T144
Test name
Test status
Simulation time 3384298385 ps
CPU time 22.41 seconds
Started Jul 22 05:48:06 PM PDT 24
Finished Jul 22 05:48:29 PM PDT 24
Peak memory 213316 kb
Host smart-fb9f78bf-da25-4d25-870c-e32ec19bc149
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340117822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.340117822
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.3942567424
Short name T37
Test name
Test status
Simulation time 6342367745 ps
CPU time 6.96 seconds
Started Jul 22 05:46:32 PM PDT 24
Finished Jul 22 05:46:39 PM PDT 24
Peak memory 213152 kb
Host smart-7b0895cd-262d-44cd-9bcd-09d47ffd46b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942567424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3942567424
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.711922752
Short name T4
Test name
Test status
Simulation time 271737958 ps
CPU time 1.41 seconds
Started Jul 22 05:45:51 PM PDT 24
Finished Jul 22 05:45:54 PM PDT 24
Peak memory 204628 kb
Host smart-6a93780b-a08f-4c55-a729-89b9f8ac7b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711922752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.711922752
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.4245060139
Short name T20
Test name
Test status
Simulation time 255360431 ps
CPU time 1.02 seconds
Started Jul 22 05:45:46 PM PDT 24
Finished Jul 22 05:45:49 PM PDT 24
Peak memory 204720 kb
Host smart-0bbd5937-4e35-4c4a-ab05-9deeb8629de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245060139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.4245060139
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3621759263
Short name T23
Test name
Test status
Simulation time 709067895 ps
CPU time 2.4 seconds
Started Jul 22 05:45:47 PM PDT 24
Finished Jul 22 05:45:51 PM PDT 24
Peak memory 204612 kb
Host smart-c78ca3b8-a935-46f0-bfa9-a0ae3ae9e9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621759263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3621759263
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2415003862
Short name T403
Test name
Test status
Simulation time 56797659460 ps
CPU time 211.56 seconds
Started Jul 22 05:45:11 PM PDT 24
Finished Jul 22 05:48:43 PM PDT 24
Peak memory 221796 kb
Host smart-6bf55e86-bfa1-4e8a-85e4-d6d9096f2457
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415003862 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2415003862
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2445610985
Short name T12
Test name
Test status
Simulation time 2534558248 ps
CPU time 2.6 seconds
Started Jul 22 05:48:05 PM PDT 24
Finished Jul 22 05:48:09 PM PDT 24
Peak memory 204980 kb
Host smart-3d06e64d-90fe-4c9b-a259-051eb9c15ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445610985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2445610985
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.3958068023
Short name T14
Test name
Test status
Simulation time 2997284922 ps
CPU time 3.6 seconds
Started Jul 22 05:46:31 PM PDT 24
Finished Jul 22 05:46:35 PM PDT 24
Peak memory 204964 kb
Host smart-281381e5-e126-43bc-876b-593a45cf2f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958068023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3958068023
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.868575730
Short name T27
Test name
Test status
Simulation time 141804016 ps
CPU time 1.03 seconds
Started Jul 22 05:47:44 PM PDT 24
Finished Jul 22 05:47:45 PM PDT 24
Peak memory 204668 kb
Host smart-879164f7-fade-4df2-9c89-4a97237093f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868575730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.868575730
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1611872455
Short name T19
Test name
Test status
Simulation time 3026832612 ps
CPU time 9.77 seconds
Started Jul 22 05:46:20 PM PDT 24
Finished Jul 22 05:46:31 PM PDT 24
Peak memory 205084 kb
Host smart-013538f3-7f00-43ec-b31e-8b4716120d00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611872455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1611872455
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.972573753
Short name T49
Test name
Test status
Simulation time 2377353913 ps
CPU time 7.78 seconds
Started Jul 22 05:46:25 PM PDT 24
Finished Jul 22 05:46:33 PM PDT 24
Peak memory 213392 kb
Host smart-09fdddee-32b1-4ed4-a6af-31cdd35a1c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972573753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.972573753
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.367948696
Short name T133
Test name
Test status
Simulation time 9176992725 ps
CPU time 6.07 seconds
Started Jul 22 05:45:46 PM PDT 24
Finished Jul 22 05:45:54 PM PDT 24
Peak memory 215140 kb
Host smart-ff832ea6-fad8-4139-a8a6-532a2cc1d3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367948696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.367948696
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.859229314
Short name T68
Test name
Test status
Simulation time 391583451 ps
CPU time 1.57 seconds
Started Jul 22 05:45:22 PM PDT 24
Finished Jul 22 05:45:25 PM PDT 24
Peak memory 204684 kb
Host smart-a8712628-5878-4e32-b292-cfb79b9cbc30
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859229314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.859229314
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.902590164
Short name T93
Test name
Test status
Simulation time 2647337393 ps
CPU time 4.82 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:45:08 PM PDT 24
Peak memory 205056 kb
Host smart-34867495-b109-4de7-aa40-bd6c3edf72d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902590164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.902590164
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.756404951
Short name T113
Test name
Test status
Simulation time 729211973 ps
CPU time 4.32 seconds
Started Jul 22 05:45:34 PM PDT 24
Finished Jul 22 05:45:40 PM PDT 24
Peak memory 204924 kb
Host smart-8fc631f4-bea7-4f43-9616-88dd6f1eabd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756404951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.756404951
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.380406218
Short name T134
Test name
Test status
Simulation time 2928133766 ps
CPU time 7.06 seconds
Started Jul 22 05:46:09 PM PDT 24
Finished Jul 22 05:46:17 PM PDT 24
Peak memory 205408 kb
Host smart-f7c5a939-3951-469b-aef6-25774027dfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380406218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.380406218
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2499288661
Short name T33
Test name
Test status
Simulation time 3178015274 ps
CPU time 1.98 seconds
Started Jul 22 05:45:46 PM PDT 24
Finished Jul 22 05:45:49 PM PDT 24
Peak memory 204676 kb
Host smart-723a656c-bfc9-4bb8-b9f8-f3421795ebf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499288661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2499288661
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.224211023
Short name T150
Test name
Test status
Simulation time 2072852221 ps
CPU time 8.36 seconds
Started Jul 22 05:45:04 PM PDT 24
Finished Jul 22 05:45:14 PM PDT 24
Peak memory 213276 kb
Host smart-cd9b882e-fa0d-4a57-9169-3b3a23619d36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224211023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.224211023
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1226692331
Short name T372
Test name
Test status
Simulation time 7016767079 ps
CPU time 27.32 seconds
Started Jul 22 05:45:38 PM PDT 24
Finished Jul 22 05:46:06 PM PDT 24
Peak memory 213312 kb
Host smart-9d3754bf-2170-445f-baa5-33aec1d585b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226692331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
226692331
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3542546292
Short name T161
Test name
Test status
Simulation time 409557731 ps
CPU time 1.29 seconds
Started Jul 22 05:45:43 PM PDT 24
Finished Jul 22 05:45:45 PM PDT 24
Peak memory 204692 kb
Host smart-4ed4f374-6bb6-46e5-8021-dce725c99bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542546292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3542546292
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.2194132067
Short name T124
Test name
Test status
Simulation time 2965823692 ps
CPU time 2.99 seconds
Started Jul 22 05:46:12 PM PDT 24
Finished Jul 22 05:46:15 PM PDT 24
Peak memory 213800 kb
Host smart-3e9d8557-7408-40ee-a54b-252d3d94d55a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194132067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2194132067
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.3637018548
Short name T24
Test name
Test status
Simulation time 5123599494 ps
CPU time 2.88 seconds
Started Jul 22 05:46:29 PM PDT 24
Finished Jul 22 05:46:32 PM PDT 24
Peak memory 205032 kb
Host smart-c5f4e64d-1a56-4209-966f-5c008abda41a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637018548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3637018548
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4149343267
Short name T108
Test name
Test status
Simulation time 1201340515 ps
CPU time 68.85 seconds
Started Jul 22 05:45:04 PM PDT 24
Finished Jul 22 05:46:14 PM PDT 24
Peak memory 205044 kb
Host smart-362e0b99-d3ff-41d2-a9fb-899c9bfc1598
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149343267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.4149343267
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1691296659
Short name T143
Test name
Test status
Simulation time 2974716748 ps
CPU time 15.03 seconds
Started Jul 22 05:45:43 PM PDT 24
Finished Jul 22 05:45:59 PM PDT 24
Peak memory 213228 kb
Host smart-e562d767-f68e-4887-9397-2e95c5a6dbe7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691296659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
691296659
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1857713101
Short name T237
Test name
Test status
Simulation time 2488687490 ps
CPU time 6.01 seconds
Started Jul 22 05:46:09 PM PDT 24
Finished Jul 22 05:46:16 PM PDT 24
Peak memory 205372 kb
Host smart-cf461a55-3e62-429b-a12c-54296dcb3e72
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857713101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1857713101
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.509967493
Short name T2
Test name
Test status
Simulation time 2516401503 ps
CPU time 2.01 seconds
Started Jul 22 05:45:42 PM PDT 24
Finished Jul 22 05:45:45 PM PDT 24
Peak memory 204896 kb
Host smart-b8dfc9dd-67b3-41ef-ab7e-6b8e18e23e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509967493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.509967493
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1717189964
Short name T96
Test name
Test status
Simulation time 4748135269 ps
CPU time 78.02 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:46:21 PM PDT 24
Peak memory 205100 kb
Host smart-5fb87f69-4eb3-41ce-a62a-5bc3f0114c14
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717189964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1717189964
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1346575590
Short name T320
Test name
Test status
Simulation time 818869020 ps
CPU time 26.73 seconds
Started Jul 22 05:45:01 PM PDT 24
Finished Jul 22 05:45:28 PM PDT 24
Peak memory 204980 kb
Host smart-f22b7d5a-3eb2-4121-b45c-b3db1984a4c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346575590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1346575590
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3671305128
Short name T107
Test name
Test status
Simulation time 253932844 ps
CPU time 2.48 seconds
Started Jul 22 05:45:13 PM PDT 24
Finished Jul 22 05:45:16 PM PDT 24
Peak memory 213024 kb
Host smart-e71df414-1141-438e-8577-d257f0cf3603
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671305128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3671305128
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3416334183
Short name T401
Test name
Test status
Simulation time 320697548 ps
CPU time 2.5 seconds
Started Jul 22 05:45:03 PM PDT 24
Finished Jul 22 05:45:07 PM PDT 24
Peak memory 216948 kb
Host smart-299f8690-e6bc-4132-974d-05aa6dfbe555
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416334183 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3416334183
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2101478458
Short name T110
Test name
Test status
Simulation time 69174521 ps
CPU time 1.43 seconds
Started Jul 22 05:45:06 PM PDT 24
Finished Jul 22 05:45:08 PM PDT 24
Peak memory 213152 kb
Host smart-db52329d-f193-47df-97a9-99508ad255f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101478458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2101478458
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.519398519
Short name T307
Test name
Test status
Simulation time 68280599434 ps
CPU time 110.35 seconds
Started Jul 22 05:45:06 PM PDT 24
Finished Jul 22 05:46:57 PM PDT 24
Peak memory 204924 kb
Host smart-39b53e2d-b702-4479-bcea-c4313abc64df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519398519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.519398519
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2159167226
Short name T281
Test name
Test status
Simulation time 17855764397 ps
CPU time 23.48 seconds
Started Jul 22 05:45:01 PM PDT 24
Finished Jul 22 05:45:25 PM PDT 24
Peak memory 204924 kb
Host smart-ea4a8478-42c3-46ee-9992-ba5c890d34c0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159167226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.2159167226
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.525393696
Short name T329
Test name
Test status
Simulation time 4147167615 ps
CPU time 3.87 seconds
Started Jul 22 05:45:01 PM PDT 24
Finished Jul 22 05:45:06 PM PDT 24
Peak memory 205000 kb
Host smart-e9bfb7d9-b36c-418e-8149-5c850b04dd23
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525393696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.525393696
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2933605753
Short name T365
Test name
Test status
Simulation time 328422862 ps
CPU time 1.59 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:45:05 PM PDT 24
Peak memory 204792 kb
Host smart-e33ccea4-a4f7-4e8c-bb52-57d94f9c2ec9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933605753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2933605753
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3985840627
Short name T355
Test name
Test status
Simulation time 16092053069 ps
CPU time 19.59 seconds
Started Jul 22 05:45:07 PM PDT 24
Finished Jul 22 05:45:27 PM PDT 24
Peak memory 205116 kb
Host smart-996d68bf-8ca5-4346-bd77-01b9e7b88869
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985840627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3985840627
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4116293660
Short name T314
Test name
Test status
Simulation time 536657560 ps
CPU time 2.12 seconds
Started Jul 22 05:45:04 PM PDT 24
Finished Jul 22 05:45:08 PM PDT 24
Peak memory 204796 kb
Host smart-47935775-4582-4031-94e6-18808f527f31
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116293660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.4116293660
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1810942078
Short name T342
Test name
Test status
Simulation time 176496979 ps
CPU time 0.82 seconds
Started Jul 22 05:45:07 PM PDT 24
Finished Jul 22 05:45:08 PM PDT 24
Peak memory 204788 kb
Host smart-275f8618-4326-4fbf-b392-30fd452d327f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810942078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
810942078
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3232264513
Short name T333
Test name
Test status
Simulation time 90983662 ps
CPU time 0.88 seconds
Started Jul 22 05:45:14 PM PDT 24
Finished Jul 22 05:45:15 PM PDT 24
Peak memory 204696 kb
Host smart-80ea240b-2a41-4187-8202-65c94d4e7135
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232264513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3232264513
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3563778956
Short name T294
Test name
Test status
Simulation time 130146124 ps
CPU time 0.99 seconds
Started Jul 22 05:45:04 PM PDT 24
Finished Jul 22 05:45:06 PM PDT 24
Peak memory 204772 kb
Host smart-31115b55-b0bd-4b79-b260-45ab225c9c52
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563778956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3563778956
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3872614199
Short name T349
Test name
Test status
Simulation time 206177201 ps
CPU time 3.73 seconds
Started Jul 22 05:45:01 PM PDT 24
Finished Jul 22 05:45:06 PM PDT 24
Peak memory 205000 kb
Host smart-73c46795-4ce0-496d-ae93-00f1c2ef1657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872614199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3872614199
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.4204887109
Short name T141
Test name
Test status
Simulation time 225500744 ps
CPU time 3.16 seconds
Started Jul 22 05:44:59 PM PDT 24
Finished Jul 22 05:45:02 PM PDT 24
Peak memory 213256 kb
Host smart-a4b7433b-bd5b-42ea-8a6d-18a616aed72f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204887109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.4204887109
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1464383365
Short name T330
Test name
Test status
Simulation time 2609233794 ps
CPU time 14.32 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:45:17 PM PDT 24
Peak memory 213332 kb
Host smart-7abfb37e-c2bd-4c5e-b3ca-b4c9024a1ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464383365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1464383365
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.329018524
Short name T362
Test name
Test status
Simulation time 1588842630 ps
CPU time 26.95 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:45:30 PM PDT 24
Peak memory 205036 kb
Host smart-f4684c39-b4ee-4402-9a13-9f6758973fa1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329018524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.329018524
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.558752764
Short name T83
Test name
Test status
Simulation time 647486066 ps
CPU time 1.82 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:45:05 PM PDT 24
Peak memory 213228 kb
Host smart-672d6633-0aa0-491e-aab2-4cc3fddf1fa8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558752764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.558752764
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1217922489
Short name T433
Test name
Test status
Simulation time 396561858 ps
CPU time 2.46 seconds
Started Jul 22 05:45:05 PM PDT 24
Finished Jul 22 05:45:08 PM PDT 24
Peak memory 213300 kb
Host smart-45423c12-eb96-4973-ac3f-bc8901459688
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217922489 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1217922489
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.548558856
Short name T431
Test name
Test status
Simulation time 184971562 ps
CPU time 2.41 seconds
Started Jul 22 05:45:04 PM PDT 24
Finished Jul 22 05:45:07 PM PDT 24
Peak memory 213272 kb
Host smart-e6ff5630-3d92-4137-b707-282877567545
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548558856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.548558856
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2138994757
Short name T392
Test name
Test status
Simulation time 227100082807 ps
CPU time 340.42 seconds
Started Jul 22 05:45:03 PM PDT 24
Finished Jul 22 05:50:45 PM PDT 24
Peak memory 211136 kb
Host smart-b1829d4e-4904-46de-90fd-00eb1ad82004
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138994757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2138994757
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3006733009
Short name T331
Test name
Test status
Simulation time 15748026319 ps
CPU time 12.02 seconds
Started Jul 22 05:45:04 PM PDT 24
Finished Jul 22 05:45:17 PM PDT 24
Peak memory 205036 kb
Host smart-b672e7bd-9056-481c-8b4d-545f8779ce25
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006733009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3006733009
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3413119347
Short name T94
Test name
Test status
Simulation time 4251730655 ps
CPU time 7.05 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:45:10 PM PDT 24
Peak memory 205068 kb
Host smart-b17f53a0-c2a6-4f87-80fa-c7b9367b9244
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413119347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3413119347
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2923766374
Short name T368
Test name
Test status
Simulation time 3396325070 ps
CPU time 3.15 seconds
Started Jul 22 05:45:13 PM PDT 24
Finished Jul 22 05:45:17 PM PDT 24
Peak memory 204968 kb
Host smart-03805a64-24a6-42ec-b543-832fc2df6d2f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923766374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
923766374
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3215953014
Short name T418
Test name
Test status
Simulation time 1085194335 ps
CPU time 2.1 seconds
Started Jul 22 05:45:01 PM PDT 24
Finished Jul 22 05:45:04 PM PDT 24
Peak memory 205024 kb
Host smart-022e456a-ea2c-4fd4-bf4a-9b459c505546
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215953014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3215953014
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2318631830
Short name T363
Test name
Test status
Simulation time 7148820769 ps
CPU time 19.91 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:45:23 PM PDT 24
Peak memory 205004 kb
Host smart-599c4520-e74b-4295-b206-7a61726430f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318631830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2318631830
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2302742419
Short name T412
Test name
Test status
Simulation time 474285563 ps
CPU time 1.13 seconds
Started Jul 22 05:45:14 PM PDT 24
Finished Jul 22 05:45:15 PM PDT 24
Peak memory 204760 kb
Host smart-f67b7210-368b-4bf5-be9f-76235071dd4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302742419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2302742419
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2405879273
Short name T391
Test name
Test status
Simulation time 383723483 ps
CPU time 1.23 seconds
Started Jul 22 05:45:04 PM PDT 24
Finished Jul 22 05:45:06 PM PDT 24
Peak memory 204784 kb
Host smart-9cdaa2ce-b33e-4bc2-a03c-72568f9b4b46
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405879273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
405879273
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3047515529
Short name T373
Test name
Test status
Simulation time 94687556 ps
CPU time 0.71 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:45:04 PM PDT 24
Peak memory 204712 kb
Host smart-86d54308-5a1b-49cb-971d-1d6601fff098
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047515529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3047515529
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2388532317
Short name T375
Test name
Test status
Simulation time 63440952 ps
CPU time 0.79 seconds
Started Jul 22 05:45:06 PM PDT 24
Finished Jul 22 05:45:07 PM PDT 24
Peak memory 204712 kb
Host smart-250d76d7-8980-43d1-8b21-0e7b0586ec31
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388532317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2388532317
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2520134590
Short name T380
Test name
Test status
Simulation time 900502263 ps
CPU time 4.12 seconds
Started Jul 22 05:45:06 PM PDT 24
Finished Jul 22 05:45:10 PM PDT 24
Peak memory 204964 kb
Host smart-59294c0d-13b0-443d-be4c-b3d41da30871
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520134590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2520134590
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2410502497
Short name T65
Test name
Test status
Simulation time 16273861339 ps
CPU time 55.24 seconds
Started Jul 22 05:45:05 PM PDT 24
Finished Jul 22 05:46:01 PM PDT 24
Peak memory 221292 kb
Host smart-5b7d14e5-73df-4493-9ddb-3bf8f544467e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410502497 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2410502497
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2244040359
Short name T72
Test name
Test status
Simulation time 264705033 ps
CPU time 3.52 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:45:06 PM PDT 24
Peak memory 213328 kb
Host smart-b6c8d1b6-a060-4885-abbf-bfe7ebc4802a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244040359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2244040359
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3126463082
Short name T73
Test name
Test status
Simulation time 175122134 ps
CPU time 2.34 seconds
Started Jul 22 05:45:38 PM PDT 24
Finished Jul 22 05:45:42 PM PDT 24
Peak memory 215440 kb
Host smart-277da12e-120e-452d-96ba-9dd255d09421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126463082 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3126463082
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.626523410
Short name T376
Test name
Test status
Simulation time 208919928 ps
CPU time 2.18 seconds
Started Jul 22 05:45:32 PM PDT 24
Finished Jul 22 05:45:36 PM PDT 24
Peak memory 213252 kb
Host smart-76f567f5-6568-420b-90f5-fa5added222f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626523410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.626523410
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2230548886
Short name T311
Test name
Test status
Simulation time 5866082404 ps
CPU time 2.93 seconds
Started Jul 22 05:45:33 PM PDT 24
Finished Jul 22 05:45:37 PM PDT 24
Peak memory 204984 kb
Host smart-9ed01719-3921-4517-979b-345ae347f99a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230548886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.2230548886
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.375969717
Short name T285
Test name
Test status
Simulation time 11841700870 ps
CPU time 29.88 seconds
Started Jul 22 05:45:20 PM PDT 24
Finished Jul 22 05:45:51 PM PDT 24
Peak memory 205220 kb
Host smart-6f176066-2d6a-4a02-a4c9-8fb17667592a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375969717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.375969717
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.18544872
Short name T77
Test name
Test status
Simulation time 242265637 ps
CPU time 4.67 seconds
Started Jul 22 05:45:29 PM PDT 24
Finished Jul 22 05:45:34 PM PDT 24
Peak memory 213324 kb
Host smart-598aca9e-2158-4696-aaf4-48b895a285d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18544872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.18544872
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4257570026
Short name T75
Test name
Test status
Simulation time 292206638 ps
CPU time 3.84 seconds
Started Jul 22 05:45:31 PM PDT 24
Finished Jul 22 05:45:36 PM PDT 24
Peak memory 219320 kb
Host smart-33a2a1ca-8687-4869-9b5c-c9781aebb1eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257570026 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.4257570026
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.914793317
Short name T82
Test name
Test status
Simulation time 375093591 ps
CPU time 2.19 seconds
Started Jul 22 05:45:34 PM PDT 24
Finished Jul 22 05:45:37 PM PDT 24
Peak memory 213188 kb
Host smart-60e357ca-4e4b-4cba-91cc-c625ae3daf3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914793317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.914793317
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1149926932
Short name T358
Test name
Test status
Simulation time 9198051789 ps
CPU time 25.62 seconds
Started Jul 22 05:45:33 PM PDT 24
Finished Jul 22 05:45:59 PM PDT 24
Peak memory 204992 kb
Host smart-820d707b-2f30-43e5-bcc0-9801d2770e20
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149926932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1149926932
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.674807725
Short name T423
Test name
Test status
Simulation time 8503707763 ps
CPU time 7.01 seconds
Started Jul 22 05:45:33 PM PDT 24
Finished Jul 22 05:45:41 PM PDT 24
Peak memory 205068 kb
Host smart-9b858a7f-fb48-460d-9ebd-9a4c0b1b3894
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674807725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.674807725
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2245381297
Short name T297
Test name
Test status
Simulation time 179327722 ps
CPU time 0.92 seconds
Started Jul 22 05:48:19 PM PDT 24
Finished Jul 22 05:48:21 PM PDT 24
Peak memory 204816 kb
Host smart-b47c1504-caf8-47ff-8c1f-237320867f69
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245381297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2245381297
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2395097126
Short name T114
Test name
Test status
Simulation time 334305329 ps
CPU time 3.58 seconds
Started Jul 22 05:45:34 PM PDT 24
Finished Jul 22 05:45:39 PM PDT 24
Peak memory 205076 kb
Host smart-c09238ea-f0a8-463a-83a3-7acc575973d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395097126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2395097126
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1705087649
Short name T400
Test name
Test status
Simulation time 218176722 ps
CPU time 2.72 seconds
Started Jul 22 05:45:32 PM PDT 24
Finished Jul 22 05:45:36 PM PDT 24
Peak memory 213296 kb
Host smart-4805da63-68a8-48f4-b08f-6e316842d6a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705087649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1705087649
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3673461867
Short name T74
Test name
Test status
Simulation time 6446869058 ps
CPU time 25.57 seconds
Started Jul 22 05:45:31 PM PDT 24
Finished Jul 22 05:45:57 PM PDT 24
Peak memory 213252 kb
Host smart-8cd0bbe8-dd73-49f9-9a7d-2c007f8bb84f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673461867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
673461867
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1658139754
Short name T324
Test name
Test status
Simulation time 387485445 ps
CPU time 4.18 seconds
Started Jul 22 05:45:34 PM PDT 24
Finished Jul 22 05:45:40 PM PDT 24
Peak memory 219384 kb
Host smart-1bb62c7f-9050-43b8-9819-c75831473ae0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658139754 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1658139754
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.258886977
Short name T109
Test name
Test status
Simulation time 56525010 ps
CPU time 2.1 seconds
Started Jul 22 05:45:38 PM PDT 24
Finished Jul 22 05:45:41 PM PDT 24
Peak memory 213240 kb
Host smart-af2d4557-82e8-4ed7-ad23-cf0d48adfc25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258886977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.258886977
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1648182322
Short name T326
Test name
Test status
Simulation time 27639219446 ps
CPU time 65.41 seconds
Started Jul 22 05:45:32 PM PDT 24
Finished Jul 22 05:46:38 PM PDT 24
Peak memory 204996 kb
Host smart-1afac3d3-3c81-4ef4-afea-4e794fe29364
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648182322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.1648182322
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.681569486
Short name T317
Test name
Test status
Simulation time 5756595308 ps
CPU time 16.51 seconds
Started Jul 22 05:48:20 PM PDT 24
Finished Jul 22 05:48:37 PM PDT 24
Peak memory 204724 kb
Host smart-5db73233-fa96-4b5e-bb73-77e0b6f5d945
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681569486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.681569486
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1992237609
Short name T340
Test name
Test status
Simulation time 153259676 ps
CPU time 1.03 seconds
Started Jul 22 05:45:31 PM PDT 24
Finished Jul 22 05:45:33 PM PDT 24
Peak memory 204752 kb
Host smart-5958dcc2-ecb9-4675-8c95-5917178c3074
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992237609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1992237609
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.954448169
Short name T420
Test name
Test status
Simulation time 341879750 ps
CPU time 4.45 seconds
Started Jul 22 05:45:34 PM PDT 24
Finished Jul 22 05:45:40 PM PDT 24
Peak memory 204984 kb
Host smart-0af89ce0-40b1-4356-ade2-f7ef07a5278f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954448169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.954448169
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4121305549
Short name T337
Test name
Test status
Simulation time 90133841 ps
CPU time 2.24 seconds
Started Jul 22 05:45:29 PM PDT 24
Finished Jul 22 05:45:32 PM PDT 24
Peak memory 213276 kb
Host smart-481acc29-3f9b-4d36-99ec-6b9df9cc5529
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121305549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.4121305549
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3235791971
Short name T149
Test name
Test status
Simulation time 5804656571 ps
CPU time 17.57 seconds
Started Jul 22 05:45:33 PM PDT 24
Finished Jul 22 05:45:51 PM PDT 24
Peak memory 213244 kb
Host smart-348d528e-b20e-43fd-a012-1d3dc7623a20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235791971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
235791971
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3710711657
Short name T90
Test name
Test status
Simulation time 328125313 ps
CPU time 2.21 seconds
Started Jul 22 05:45:33 PM PDT 24
Finished Jul 22 05:45:36 PM PDT 24
Peak memory 214796 kb
Host smart-0b499615-2df6-474f-8743-7a858d143321
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710711657 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3710711657
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.551083017
Short name T427
Test name
Test status
Simulation time 173009568 ps
CPU time 2.11 seconds
Started Jul 22 05:48:18 PM PDT 24
Finished Jul 22 05:48:21 PM PDT 24
Peak memory 213260 kb
Host smart-693002c9-47f2-45ac-afa4-5809d661d6c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551083017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.551083017
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1985257177
Short name T328
Test name
Test status
Simulation time 4679694305 ps
CPU time 4.26 seconds
Started Jul 22 05:45:34 PM PDT 24
Finished Jul 22 05:45:39 PM PDT 24
Peak memory 205020 kb
Host smart-a6a9d8ce-85b6-4434-a9f9-6626d432964c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985257177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.1985257177
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.330925828
Short name T344
Test name
Test status
Simulation time 5928855935 ps
CPU time 4.99 seconds
Started Jul 22 05:45:27 PM PDT 24
Finished Jul 22 05:45:32 PM PDT 24
Peak memory 205120 kb
Host smart-7a1fc95f-2782-4d3d-91ec-8bed8d74eeb2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330925828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.330925828
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1843417882
Short name T384
Test name
Test status
Simulation time 336098067 ps
CPU time 0.87 seconds
Started Jul 22 05:48:20 PM PDT 24
Finished Jul 22 05:48:21 PM PDT 24
Peak memory 204816 kb
Host smart-6ded903f-3aa2-43bb-b80a-bd7807124e46
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843417882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1843417882
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.178838381
Short name T84
Test name
Test status
Simulation time 4609086109 ps
CPU time 4.96 seconds
Started Jul 22 05:45:32 PM PDT 24
Finished Jul 22 05:45:37 PM PDT 24
Peak memory 205032 kb
Host smart-d66297aa-d6d8-431a-bcc8-cfb21fa279b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178838381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.178838381
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.144255284
Short name T303
Test name
Test status
Simulation time 117495052 ps
CPU time 2.39 seconds
Started Jul 22 05:45:32 PM PDT 24
Finished Jul 22 05:45:36 PM PDT 24
Peak memory 213280 kb
Host smart-a8cd6990-8dd3-4573-972c-9d3d3f626d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144255284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.144255284
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.386109348
Short name T369
Test name
Test status
Simulation time 2999727180 ps
CPU time 14.54 seconds
Started Jul 22 05:46:40 PM PDT 24
Finished Jul 22 05:46:55 PM PDT 24
Peak memory 213276 kb
Host smart-2fd7bdd0-c62d-496c-9727-d643020ed01b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386109348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.386109348
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4110535155
Short name T417
Test name
Test status
Simulation time 174436655 ps
CPU time 2.51 seconds
Started Jul 22 05:45:32 PM PDT 24
Finished Jul 22 05:45:36 PM PDT 24
Peak memory 218112 kb
Host smart-5c154ace-7112-4b47-8564-09feb919fceb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110535155 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4110535155
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2114487406
Short name T419
Test name
Test status
Simulation time 59335539 ps
CPU time 1.53 seconds
Started Jul 22 05:45:34 PM PDT 24
Finished Jul 22 05:45:36 PM PDT 24
Peak memory 213224 kb
Host smart-8c86e444-6fea-400b-920e-010fb4c711e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114487406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2114487406
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2296983636
Short name T309
Test name
Test status
Simulation time 13574831912 ps
CPU time 38.68 seconds
Started Jul 22 05:45:35 PM PDT 24
Finished Jul 22 05:46:15 PM PDT 24
Peak memory 204864 kb
Host smart-ec4b12cf-e607-4178-accd-685c9abaeea1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296983636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.2296983636
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.520258052
Short name T338
Test name
Test status
Simulation time 2526738483 ps
CPU time 2.72 seconds
Started Jul 22 05:45:28 PM PDT 24
Finished Jul 22 05:45:32 PM PDT 24
Peak memory 204996 kb
Host smart-a4c6f028-b625-4be1-8a8d-d236b8cd3a82
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520258052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.520258052
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4216992962
Short name T377
Test name
Test status
Simulation time 210450514 ps
CPU time 1.17 seconds
Started Jul 22 05:45:33 PM PDT 24
Finished Jul 22 05:45:35 PM PDT 24
Peak memory 204784 kb
Host smart-4cc8ab8a-50db-4764-824d-b0813bb61794
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216992962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
4216992962
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1139795240
Short name T115
Test name
Test status
Simulation time 170232048 ps
CPU time 3.59 seconds
Started Jul 22 05:45:35 PM PDT 24
Finished Jul 22 05:45:40 PM PDT 24
Peak memory 205000 kb
Host smart-36e42632-232b-40ff-803a-163f317a593b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139795240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1139795240
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1761003207
Short name T387
Test name
Test status
Simulation time 113060525 ps
CPU time 4.02 seconds
Started Jul 22 05:45:35 PM PDT 24
Finished Jul 22 05:45:40 PM PDT 24
Peak memory 213160 kb
Host smart-4ec77ac6-64d3-4c22-b24c-fe7d4fd34c43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761003207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1761003207
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1334597537
Short name T353
Test name
Test status
Simulation time 197893366 ps
CPU time 2.52 seconds
Started Jul 22 05:45:35 PM PDT 24
Finished Jul 22 05:45:39 PM PDT 24
Peak memory 221464 kb
Host smart-3825ff2a-e937-40e7-b209-4fdcb975b784
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334597537 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1334597537
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3699912542
Short name T104
Test name
Test status
Simulation time 428695903 ps
CPU time 1.47 seconds
Started Jul 22 05:45:35 PM PDT 24
Finished Jul 22 05:45:38 PM PDT 24
Peak memory 213200 kb
Host smart-1615995b-a997-41ba-abc4-4f3b4548c638
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699912542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3699912542
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2620131256
Short name T425
Test name
Test status
Simulation time 5292065660 ps
CPU time 14.9 seconds
Started Jul 22 05:45:34 PM PDT 24
Finished Jul 22 05:45:50 PM PDT 24
Peak memory 204972 kb
Host smart-0dde1175-a1ac-4ce8-9382-2454ae283435
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620131256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.2620131256
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.484897878
Short name T416
Test name
Test status
Simulation time 3483320794 ps
CPU time 3.65 seconds
Started Jul 22 05:45:32 PM PDT 24
Finished Jul 22 05:45:37 PM PDT 24
Peak memory 204968 kb
Host smart-beb48174-aacd-45bb-a3ca-04197ecf233a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484897878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.484897878
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1238601190
Short name T305
Test name
Test status
Simulation time 449646591 ps
CPU time 1.89 seconds
Started Jul 22 05:45:33 PM PDT 24
Finished Jul 22 05:45:36 PM PDT 24
Peak memory 204808 kb
Host smart-ae1183a6-355f-465b-adf1-5ed355846556
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238601190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1238601190
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4120412544
Short name T101
Test name
Test status
Simulation time 418978714 ps
CPU time 6.39 seconds
Started Jul 22 05:45:31 PM PDT 24
Finished Jul 22 05:45:38 PM PDT 24
Peak memory 204956 kb
Host smart-55dd5abc-2889-4d77-b354-c9abf7dc5269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120412544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.4120412544
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1151574243
Short name T291
Test name
Test status
Simulation time 240618966 ps
CPU time 2.57 seconds
Started Jul 22 05:45:31 PM PDT 24
Finished Jul 22 05:45:34 PM PDT 24
Peak memory 213268 kb
Host smart-b2dee43b-993c-4833-996c-5ff1d030011f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151574243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1151574243
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2998596106
Short name T146
Test name
Test status
Simulation time 4113745610 ps
CPU time 19.27 seconds
Started Jul 22 05:48:18 PM PDT 24
Finished Jul 22 05:48:38 PM PDT 24
Peak memory 213296 kb
Host smart-6369faa1-9ad0-4d56-9027-9b0c99becd8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998596106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
998596106
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1257313765
Short name T414
Test name
Test status
Simulation time 103858390 ps
CPU time 4.31 seconds
Started Jul 22 05:48:19 PM PDT 24
Finished Jul 22 05:48:25 PM PDT 24
Peak memory 219388 kb
Host smart-e14f34e3-0139-4b84-b714-615983273de9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257313765 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1257313765
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.667990755
Short name T88
Test name
Test status
Simulation time 95305375 ps
CPU time 1.48 seconds
Started Jul 22 05:45:34 PM PDT 24
Finished Jul 22 05:45:37 PM PDT 24
Peak memory 213216 kb
Host smart-0f1d3bab-76d8-40d9-aa52-95ae2210ffbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667990755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.667990755
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4026958548
Short name T316
Test name
Test status
Simulation time 11872811219 ps
CPU time 35.18 seconds
Started Jul 22 05:45:34 PM PDT 24
Finished Jul 22 05:46:11 PM PDT 24
Peak memory 204980 kb
Host smart-c9d04b8c-b10d-465d-b399-71a202897785
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026958548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.4026958548
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.576091457
Short name T348
Test name
Test status
Simulation time 2680852564 ps
CPU time 4.49 seconds
Started Jul 22 05:45:28 PM PDT 24
Finished Jul 22 05:45:33 PM PDT 24
Peak memory 204996 kb
Host smart-60e3cb3c-f5b0-4636-bfcc-8a4240bb0597
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576091457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.576091457
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1538434368
Short name T67
Test name
Test status
Simulation time 390918250 ps
CPU time 0.98 seconds
Started Jul 22 05:45:31 PM PDT 24
Finished Jul 22 05:45:33 PM PDT 24
Peak memory 204808 kb
Host smart-74a59a8b-265b-4091-8f64-774fa02f640b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538434368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1538434368
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4216348547
Short name T116
Test name
Test status
Simulation time 212346564 ps
CPU time 6.35 seconds
Started Jul 22 05:46:40 PM PDT 24
Finished Jul 22 05:46:46 PM PDT 24
Peak memory 204916 kb
Host smart-09472aef-8c3c-435e-b7b4-53266fdac392
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216348547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.4216348547
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2720676767
Short name T428
Test name
Test status
Simulation time 161988180 ps
CPU time 2.91 seconds
Started Jul 22 05:45:30 PM PDT 24
Finished Jul 22 05:45:33 PM PDT 24
Peak memory 213320 kb
Host smart-30811071-ed76-42fc-91ca-f6533ef0de9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720676767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2720676767
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3842696329
Short name T408
Test name
Test status
Simulation time 3576295653 ps
CPU time 19.39 seconds
Started Jul 22 05:45:38 PM PDT 24
Finished Jul 22 05:45:58 PM PDT 24
Peak memory 213272 kb
Host smart-a69075b4-3c6e-4d3c-a052-8982128e5b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842696329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
842696329
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2820324111
Short name T304
Test name
Test status
Simulation time 628957679 ps
CPU time 3.89 seconds
Started Jul 22 05:45:41 PM PDT 24
Finished Jul 22 05:45:45 PM PDT 24
Peak memory 221420 kb
Host smart-c4728803-3ac7-4c90-b86d-73f38c6c7ba9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820324111 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2820324111
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.769662949
Short name T105
Test name
Test status
Simulation time 184520040 ps
CPU time 2.07 seconds
Started Jul 22 05:45:44 PM PDT 24
Finished Jul 22 05:45:47 PM PDT 24
Peak memory 213172 kb
Host smart-70cbea12-8d9c-46fe-a34c-a5a149ce8a82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769662949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.769662949
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.23541368
Short name T323
Test name
Test status
Simulation time 3492967553 ps
CPU time 5.74 seconds
Started Jul 22 05:45:37 PM PDT 24
Finished Jul 22 05:45:44 PM PDT 24
Peak memory 205024 kb
Host smart-5c032030-104f-4dc2-9227-9cee7431f95a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23541368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.r
v_dm_jtag_dmi_csr_bit_bash.23541368
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1680760697
Short name T299
Test name
Test status
Simulation time 1482891270 ps
CPU time 2.98 seconds
Started Jul 22 05:45:34 PM PDT 24
Finished Jul 22 05:45:38 PM PDT 24
Peak memory 204968 kb
Host smart-53a0386f-6a42-48e0-9985-34ed7d565b39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680760697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1680760697
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.21691038
Short name T356
Test name
Test status
Simulation time 313224355 ps
CPU time 0.87 seconds
Started Jul 22 05:45:32 PM PDT 24
Finished Jul 22 05:45:34 PM PDT 24
Peak memory 204760 kb
Host smart-bcc57f87-ad96-4ab2-bd03-912a4de8da73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21691038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.21691038
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3698299141
Short name T98
Test name
Test status
Simulation time 287706738 ps
CPU time 3.76 seconds
Started Jul 22 05:45:44 PM PDT 24
Finished Jul 22 05:45:49 PM PDT 24
Peak memory 204968 kb
Host smart-abd8099e-00ec-4ee7-bee2-9868d2641932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698299141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3698299141
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.306528781
Short name T390
Test name
Test status
Simulation time 839270327 ps
CPU time 5.15 seconds
Started Jul 22 05:45:45 PM PDT 24
Finished Jul 22 05:45:51 PM PDT 24
Peak memory 213360 kb
Host smart-6952bf6b-5e7b-4787-9d7c-b59c5ebd2985
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306528781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.306528781
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1931152394
Short name T322
Test name
Test status
Simulation time 219220548 ps
CPU time 2.75 seconds
Started Jul 22 05:45:41 PM PDT 24
Finished Jul 22 05:45:45 PM PDT 24
Peak memory 219088 kb
Host smart-d3a773a8-d1d3-4100-addd-099216c0f65f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931152394 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1931152394
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3459307267
Short name T366
Test name
Test status
Simulation time 263273623 ps
CPU time 1.59 seconds
Started Jul 22 05:45:41 PM PDT 24
Finished Jul 22 05:45:44 PM PDT 24
Peak memory 213188 kb
Host smart-d5ed4ad0-02d3-43a0-8860-7c26cb9d3450
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459307267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3459307267
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2134371400
Short name T283
Test name
Test status
Simulation time 24958997340 ps
CPU time 20 seconds
Started Jul 22 05:45:42 PM PDT 24
Finished Jul 22 05:46:03 PM PDT 24
Peak memory 204960 kb
Host smart-b203613e-b756-4ae1-b617-6a0ff14ba825
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134371400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2134371400
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2441864078
Short name T381
Test name
Test status
Simulation time 1097792413 ps
CPU time 1.41 seconds
Started Jul 22 05:45:41 PM PDT 24
Finished Jul 22 05:45:43 PM PDT 24
Peak memory 204960 kb
Host smart-14508a3b-0a01-430a-9f0a-f6fbbf524ce9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441864078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2441864078
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3780379828
Short name T396
Test name
Test status
Simulation time 291163438 ps
CPU time 1.06 seconds
Started Jul 22 05:45:45 PM PDT 24
Finished Jul 22 05:45:47 PM PDT 24
Peak memory 204812 kb
Host smart-8244022d-0e0f-4fec-b401-c5ee88c5759a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780379828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3780379828
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.698548361
Short name T117
Test name
Test status
Simulation time 273924305 ps
CPU time 6.34 seconds
Started Jul 22 05:45:45 PM PDT 24
Finished Jul 22 05:45:52 PM PDT 24
Peak memory 205056 kb
Host smart-a49ea989-4f4f-4f60-8647-95b767075c7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698548361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.698548361
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1635619155
Short name T301
Test name
Test status
Simulation time 217025602 ps
CPU time 3.35 seconds
Started Jul 22 05:45:41 PM PDT 24
Finished Jul 22 05:45:45 PM PDT 24
Peak memory 213180 kb
Host smart-834f1d52-1b96-467c-9c6c-305ba7f3a881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635619155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1635619155
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2568325280
Short name T393
Test name
Test status
Simulation time 1108942255 ps
CPU time 10.13 seconds
Started Jul 22 05:45:43 PM PDT 24
Finished Jul 22 05:45:53 PM PDT 24
Peak memory 213240 kb
Host smart-1be0758e-1fcc-4179-a848-8cc34d043428
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568325280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
568325280
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2121275668
Short name T409
Test name
Test status
Simulation time 346812316 ps
CPU time 2.41 seconds
Started Jul 22 05:45:42 PM PDT 24
Finished Jul 22 05:45:45 PM PDT 24
Peak memory 213264 kb
Host smart-36046dba-a232-4d5c-8e17-b5e0e0f1e794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121275668 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2121275668
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1363319842
Short name T112
Test name
Test status
Simulation time 200891142 ps
CPU time 1.6 seconds
Started Jul 22 05:45:50 PM PDT 24
Finished Jul 22 05:45:53 PM PDT 24
Peak memory 213216 kb
Host smart-ffcd8798-afbd-4021-bfa9-95fb89e3a5d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363319842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1363319842
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.238823568
Short name T374
Test name
Test status
Simulation time 6927565433 ps
CPU time 18.8 seconds
Started Jul 22 05:45:43 PM PDT 24
Finished Jul 22 05:46:03 PM PDT 24
Peak memory 204884 kb
Host smart-afcbf9f8-05fd-4a8c-829b-51d74644f671
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238823568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.238823568
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3137232750
Short name T282
Test name
Test status
Simulation time 15329695634 ps
CPU time 39.72 seconds
Started Jul 22 05:45:41 PM PDT 24
Finished Jul 22 05:46:22 PM PDT 24
Peak memory 205012 kb
Host smart-f4b50f47-f324-4a31-97de-29b3caac5b21
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137232750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3137232750
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2886398806
Short name T351
Test name
Test status
Simulation time 443293804 ps
CPU time 0.77 seconds
Started Jul 22 05:45:45 PM PDT 24
Finished Jul 22 05:45:47 PM PDT 24
Peak memory 204792 kb
Host smart-25f9dc13-4958-4c3d-bbe3-5d4388392d57
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886398806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2886398806
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4173867566
Short name T102
Test name
Test status
Simulation time 1590088734 ps
CPU time 7.73 seconds
Started Jul 22 05:45:44 PM PDT 24
Finished Jul 22 05:45:53 PM PDT 24
Peak memory 205020 kb
Host smart-21e3bcd0-b4c5-4a0b-9cc1-2d15204608be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173867566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.4173867566
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3562390054
Short name T432
Test name
Test status
Simulation time 784762439 ps
CPU time 5.36 seconds
Started Jul 22 05:45:40 PM PDT 24
Finished Jul 22 05:45:46 PM PDT 24
Peak memory 213288 kb
Host smart-3fd4d6ff-c725-4a41-af51-28ae13b59a45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562390054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3562390054
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1552812955
Short name T394
Test name
Test status
Simulation time 8744948235 ps
CPU time 34.76 seconds
Started Jul 22 05:45:03 PM PDT 24
Finished Jul 22 05:45:39 PM PDT 24
Peak memory 213252 kb
Host smart-2332c427-20ba-4d95-8b30-0b301d781f09
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552812955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1552812955
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3584407510
Short name T397
Test name
Test status
Simulation time 14630437454 ps
CPU time 35.7 seconds
Started Jul 22 05:45:11 PM PDT 24
Finished Jul 22 05:45:47 PM PDT 24
Peak memory 213260 kb
Host smart-8865bb10-4790-493f-be59-0e1a80eac8f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584407510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3584407510
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3135901779
Short name T81
Test name
Test status
Simulation time 115793487 ps
CPU time 1.57 seconds
Started Jul 22 05:45:07 PM PDT 24
Finished Jul 22 05:45:09 PM PDT 24
Peak memory 213264 kb
Host smart-2ee99d85-5d1f-4aed-b0d7-6e9b0ccf226d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135901779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3135901779
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3058912562
Short name T429
Test name
Test status
Simulation time 242656834 ps
CPU time 2.7 seconds
Started Jul 22 05:45:11 PM PDT 24
Finished Jul 22 05:45:14 PM PDT 24
Peak memory 213260 kb
Host smart-e41544b2-96bb-4dde-ba4c-37879c72d66b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058912562 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3058912562
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1787460585
Short name T402
Test name
Test status
Simulation time 129992982 ps
CPU time 1.6 seconds
Started Jul 22 05:45:03 PM PDT 24
Finished Jul 22 05:45:06 PM PDT 24
Peak memory 213384 kb
Host smart-dd40a9a4-ccba-49a4-a52b-4fed586c3a7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787460585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1787460585
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1391630703
Short name T371
Test name
Test status
Simulation time 23664262286 ps
CPU time 67.17 seconds
Started Jul 22 05:45:10 PM PDT 24
Finished Jul 22 05:46:18 PM PDT 24
Peak memory 204976 kb
Host smart-f0be8883-f16d-4031-927c-62ccc14842dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391630703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1391630703
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2154037228
Short name T359
Test name
Test status
Simulation time 64761394052 ps
CPU time 94.51 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:46:37 PM PDT 24
Peak memory 205024 kb
Host smart-8f54eeca-b0af-460c-81c9-6f44564bfcfe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154037228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.2154037228
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2078686316
Short name T91
Test name
Test status
Simulation time 6772710515 ps
CPU time 7.45 seconds
Started Jul 22 05:45:03 PM PDT 24
Finished Jul 22 05:45:11 PM PDT 24
Peak memory 205208 kb
Host smart-8e0eec6a-fa12-4591-8cb1-c45a68706159
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078686316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2078686316
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3196423295
Short name T336
Test name
Test status
Simulation time 7496933052 ps
CPU time 11.52 seconds
Started Jul 22 05:45:07 PM PDT 24
Finished Jul 22 05:45:19 PM PDT 24
Peak memory 204996 kb
Host smart-656d8041-af2d-4a79-ac02-ffb7a42e4963
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196423295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
196423295
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3684560481
Short name T430
Test name
Test status
Simulation time 348187216 ps
CPU time 1.1 seconds
Started Jul 22 05:45:05 PM PDT 24
Finished Jul 22 05:45:07 PM PDT 24
Peak memory 204800 kb
Host smart-89f45173-2369-4e2e-8591-73c84ed82473
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684560481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3684560481
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2147149557
Short name T306
Test name
Test status
Simulation time 3407606070 ps
CPU time 11.46 seconds
Started Jul 22 05:45:04 PM PDT 24
Finished Jul 22 05:45:17 PM PDT 24
Peak memory 204980 kb
Host smart-835cb6d1-c804-4109-8d0c-ec6afaaeaa62
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147149557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2147149557
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.283128666
Short name T312
Test name
Test status
Simulation time 510542569 ps
CPU time 1.04 seconds
Started Jul 22 05:45:15 PM PDT 24
Finished Jul 22 05:45:17 PM PDT 24
Peak memory 204760 kb
Host smart-79555b36-f4cd-4ecd-a4e6-7d37fa3efd53
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283128666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.283128666
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.181836318
Short name T289
Test name
Test status
Simulation time 353796815 ps
CPU time 0.83 seconds
Started Jul 22 05:45:01 PM PDT 24
Finished Jul 22 05:45:03 PM PDT 24
Peak memory 204752 kb
Host smart-a0dbbd50-2fe9-4b25-9fe0-61d63fe1cb8b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181836318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.181836318
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3146520152
Short name T325
Test name
Test status
Simulation time 93406711 ps
CPU time 1.11 seconds
Started Jul 22 05:45:01 PM PDT 24
Finished Jul 22 05:45:03 PM PDT 24
Peak memory 204756 kb
Host smart-abbb669e-d5bf-449c-a2d9-4363775b46fc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146520152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3146520152
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1685721410
Short name T426
Test name
Test status
Simulation time 139639036 ps
CPU time 0.84 seconds
Started Jul 22 05:45:07 PM PDT 24
Finished Jul 22 05:45:08 PM PDT 24
Peak memory 204804 kb
Host smart-24b4551b-d552-4a55-8268-57f7aeda4d7c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685721410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1685721410
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1706986810
Short name T367
Test name
Test status
Simulation time 2044844430 ps
CPU time 8.44 seconds
Started Jul 22 05:45:01 PM PDT 24
Finished Jul 22 05:45:10 PM PDT 24
Peak memory 205072 kb
Host smart-44387108-8b01-4b50-a5e0-c01118665107
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706986810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1706986810
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3713168809
Short name T385
Test name
Test status
Simulation time 142370585 ps
CPU time 2.74 seconds
Started Jul 22 05:45:13 PM PDT 24
Finished Jul 22 05:45:17 PM PDT 24
Peak memory 213116 kb
Host smart-22b8b963-3029-4ada-96e6-136c7c10c321
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713168809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3713168809
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3307186641
Short name T56
Test name
Test status
Simulation time 1177596681 ps
CPU time 10.95 seconds
Started Jul 22 05:45:04 PM PDT 24
Finished Jul 22 05:45:16 PM PDT 24
Peak memory 213152 kb
Host smart-897b2c01-8933-4f7c-b44f-21fb2b097aac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307186641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3307186641
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2097094496
Short name T334
Test name
Test status
Simulation time 628679747 ps
CPU time 26.91 seconds
Started Jul 22 05:45:03 PM PDT 24
Finished Jul 22 05:45:31 PM PDT 24
Peak memory 213220 kb
Host smart-549f77cd-73e6-4de5-93ad-541c373f877d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097094496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2097094496
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3562056416
Short name T308
Test name
Test status
Simulation time 29139312758 ps
CPU time 80.67 seconds
Started Jul 22 05:45:14 PM PDT 24
Finished Jul 22 05:46:35 PM PDT 24
Peak memory 204972 kb
Host smart-b6aa805d-8574-4843-92d0-e0199b0c151a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562056416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3562056416
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1247300529
Short name T360
Test name
Test status
Simulation time 168449342 ps
CPU time 2.65 seconds
Started Jul 22 05:45:11 PM PDT 24
Finished Jul 22 05:45:14 PM PDT 24
Peak memory 213280 kb
Host smart-70875ecf-5af7-48c6-90e4-dd785f841fa7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247300529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1247300529
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.698565952
Short name T407
Test name
Test status
Simulation time 156707787 ps
CPU time 2.37 seconds
Started Jul 22 05:45:12 PM PDT 24
Finished Jul 22 05:45:15 PM PDT 24
Peak memory 221332 kb
Host smart-60174989-5159-4e3f-aabe-cd7b1ce447d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698565952 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.698565952
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.734096126
Short name T395
Test name
Test status
Simulation time 461712308 ps
CPU time 2.38 seconds
Started Jul 22 05:45:10 PM PDT 24
Finished Jul 22 05:45:12 PM PDT 24
Peak memory 213244 kb
Host smart-209fb7cc-bf62-4310-8b75-a710b822c286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734096126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.734096126
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1624025503
Short name T386
Test name
Test status
Simulation time 143183460240 ps
CPU time 191.47 seconds
Started Jul 22 05:45:11 PM PDT 24
Finished Jul 22 05:48:23 PM PDT 24
Peak memory 205532 kb
Host smart-d2508c27-3c34-45d2-8063-7b1e5e1d0d36
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624025503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1624025503
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.944649888
Short name T288
Test name
Test status
Simulation time 24890237666 ps
CPU time 20.7 seconds
Started Jul 22 05:45:04 PM PDT 24
Finished Jul 22 05:45:26 PM PDT 24
Peak memory 205028 kb
Host smart-610478a2-3d3c-4bf1-860c-38fa9305f42c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944649888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
v_dm_jtag_dmi_csr_bit_bash.944649888
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3028723485
Short name T95
Test name
Test status
Simulation time 6425100821 ps
CPU time 9.44 seconds
Started Jul 22 05:45:04 PM PDT 24
Finished Jul 22 05:45:15 PM PDT 24
Peak memory 205044 kb
Host smart-f76cd557-24d2-44fb-9303-7eb97d28b678
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028723485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3028723485
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1694008690
Short name T332
Test name
Test status
Simulation time 5749383893 ps
CPU time 4.83 seconds
Started Jul 22 05:45:11 PM PDT 24
Finished Jul 22 05:45:16 PM PDT 24
Peak memory 204972 kb
Host smart-fe897e3b-0d7b-4dfc-bd6e-adf2438f9e6e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694008690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
694008690
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1752027434
Short name T415
Test name
Test status
Simulation time 352202652 ps
CPU time 1.61 seconds
Started Jul 22 05:45:02 PM PDT 24
Finished Jul 22 05:45:05 PM PDT 24
Peak memory 204668 kb
Host smart-be9b7d64-d40e-4c5f-b9f3-ce0940162a72
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752027434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1752027434
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.177176334
Short name T406
Test name
Test status
Simulation time 5313888927 ps
CPU time 3.13 seconds
Started Jul 22 05:45:10 PM PDT 24
Finished Jul 22 05:45:14 PM PDT 24
Peak memory 204996 kb
Host smart-1e08552f-0bb6-45a5-93cf-83751c6acbe9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177176334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.177176334
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1159567351
Short name T292
Test name
Test status
Simulation time 329028357 ps
CPU time 1.18 seconds
Started Jul 22 05:45:03 PM PDT 24
Finished Jul 22 05:45:05 PM PDT 24
Peak memory 204792 kb
Host smart-33e383ff-9c7a-4a9d-abca-9db63d967d85
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159567351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1159567351
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3823679745
Short name T298
Test name
Test status
Simulation time 343827930 ps
CPU time 1.27 seconds
Started Jul 22 05:45:03 PM PDT 24
Finished Jul 22 05:45:06 PM PDT 24
Peak memory 204760 kb
Host smart-7d20555c-be72-4e6c-8e54-d68b6f5b318d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823679745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
823679745
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3957972474
Short name T341
Test name
Test status
Simulation time 61260276 ps
CPU time 0.78 seconds
Started Jul 22 05:45:22 PM PDT 24
Finished Jul 22 05:45:24 PM PDT 24
Peak memory 204772 kb
Host smart-73708b57-e124-401b-a08b-1a9fcd6515c1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957972474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3957972474
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.809929732
Short name T383
Test name
Test status
Simulation time 36997581 ps
CPU time 0.66 seconds
Started Jul 22 05:45:15 PM PDT 24
Finished Jul 22 05:45:16 PM PDT 24
Peak memory 204776 kb
Host smart-c5f0cc5b-7394-45e7-8fbc-4dd0563220a4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809929732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.809929732
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3380867259
Short name T100
Test name
Test status
Simulation time 191786157 ps
CPU time 3.65 seconds
Started Jul 22 05:45:13 PM PDT 24
Finished Jul 22 05:45:17 PM PDT 24
Peak memory 204984 kb
Host smart-ceb97469-e2e8-4a56-968d-96650287108e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380867259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3380867259
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.518533453
Short name T153
Test name
Test status
Simulation time 17685926874 ps
CPU time 30.51 seconds
Started Jul 22 05:45:14 PM PDT 24
Finished Jul 22 05:45:46 PM PDT 24
Peak memory 221368 kb
Host smart-e74f04a7-f2e5-4a97-b3bf-6d1b3d7c68c5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518533453 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.518533453
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.621576831
Short name T354
Test name
Test status
Simulation time 322361437 ps
CPU time 5.56 seconds
Started Jul 22 05:45:10 PM PDT 24
Finished Jul 22 05:45:17 PM PDT 24
Peak memory 213240 kb
Host smart-ac7c0fe3-dd0b-4fe0-a67b-9df4d7d742c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621576831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.621576831
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1214861865
Short name T147
Test name
Test status
Simulation time 5156541344 ps
CPU time 27.1 seconds
Started Jul 22 05:45:10 PM PDT 24
Finished Jul 22 05:45:38 PM PDT 24
Peak memory 213248 kb
Host smart-17a59cc2-413a-4cc6-8fe0-d9fdbbed508f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214861865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1214861865
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2037324409
Short name T347
Test name
Test status
Simulation time 4299421188 ps
CPU time 65.08 seconds
Started Jul 22 05:45:12 PM PDT 24
Finished Jul 22 05:46:17 PM PDT 24
Peak memory 213160 kb
Host smart-391f4f4f-c7d7-4e06-a896-bbebf063fe52
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037324409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2037324409
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2400171257
Short name T86
Test name
Test status
Simulation time 5109739031 ps
CPU time 63.57 seconds
Started Jul 22 05:47:48 PM PDT 24
Finished Jul 22 05:48:52 PM PDT 24
Peak memory 213220 kb
Host smart-8a0f34d3-ecc9-4f8a-9561-cefe6a0a42cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400171257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2400171257
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.632938999
Short name T97
Test name
Test status
Simulation time 155875795 ps
CPU time 2.66 seconds
Started Jul 22 05:45:22 PM PDT 24
Finished Jul 22 05:45:26 PM PDT 24
Peak memory 213360 kb
Host smart-0005dee1-7d31-462e-9f25-724830cb18ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632938999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.632938999
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.573441957
Short name T293
Test name
Test status
Simulation time 628128319 ps
CPU time 2.31 seconds
Started Jul 22 05:45:20 PM PDT 24
Finished Jul 22 05:45:23 PM PDT 24
Peak memory 215272 kb
Host smart-2985107a-08df-4687-9577-90d27e9b8531
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573441957 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.573441957
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4076023944
Short name T111
Test name
Test status
Simulation time 143168792 ps
CPU time 1.46 seconds
Started Jul 22 05:45:22 PM PDT 24
Finished Jul 22 05:45:25 PM PDT 24
Peak memory 213320 kb
Host smart-48e5f561-a827-4d25-af59-8d0f12ac112f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076023944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.4076023944
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3106074616
Short name T313
Test name
Test status
Simulation time 109138755767 ps
CPU time 76.02 seconds
Started Jul 22 05:45:14 PM PDT 24
Finished Jul 22 05:46:31 PM PDT 24
Peak memory 204964 kb
Host smart-f2f28acd-9c54-4a50-aac5-d29aa6c8b0b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106074616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.3106074616
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.861398368
Short name T389
Test name
Test status
Simulation time 25614302677 ps
CPU time 26.15 seconds
Started Jul 22 05:45:11 PM PDT 24
Finished Jul 22 05:45:38 PM PDT 24
Peak memory 204944 kb
Host smart-b60c2121-ca3e-4926-a44e-73c737307eb3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861398368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.861398368
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.123907128
Short name T92
Test name
Test status
Simulation time 3304094261 ps
CPU time 2.68 seconds
Started Jul 22 05:45:11 PM PDT 24
Finished Jul 22 05:45:15 PM PDT 24
Peak memory 205104 kb
Host smart-4e4a050f-5c69-435e-b7ac-91bedbeb7ca6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123907128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.123907128
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3458892587
Short name T413
Test name
Test status
Simulation time 4777323632 ps
CPU time 13.54 seconds
Started Jul 22 05:45:14 PM PDT 24
Finished Jul 22 05:45:28 PM PDT 24
Peak memory 204956 kb
Host smart-bd9d9ad1-73f8-4848-9c5f-f39a2126b3f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458892587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
458892587
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1561371943
Short name T66
Test name
Test status
Simulation time 333094578 ps
CPU time 1.63 seconds
Started Jul 22 05:45:11 PM PDT 24
Finished Jul 22 05:45:13 PM PDT 24
Peak memory 204788 kb
Host smart-dc6cedf2-139b-404a-bdf4-bb7bfae92345
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561371943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1561371943
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1120681866
Short name T300
Test name
Test status
Simulation time 13406029983 ps
CPU time 35.86 seconds
Started Jul 22 05:45:14 PM PDT 24
Finished Jul 22 05:45:51 PM PDT 24
Peak memory 204968 kb
Host smart-cefc836a-3261-4349-a432-eead7c920e37
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120681866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1120681866
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1723825695
Short name T296
Test name
Test status
Simulation time 399492822 ps
CPU time 1.6 seconds
Started Jul 22 05:45:18 PM PDT 24
Finished Jul 22 05:45:20 PM PDT 24
Peak memory 204792 kb
Host smart-63ddecdd-eab9-4ed9-81a4-73c9f380adb1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723825695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1723825695
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.692435575
Short name T321
Test name
Test status
Simulation time 764715682 ps
CPU time 1.09 seconds
Started Jul 22 05:45:14 PM PDT 24
Finished Jul 22 05:45:16 PM PDT 24
Peak memory 204620 kb
Host smart-fbda9850-dca7-4705-bf09-ce40b158688b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692435575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.692435575
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.511357584
Short name T346
Test name
Test status
Simulation time 33873991 ps
CPU time 0.7 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:45:23 PM PDT 24
Peak memory 204668 kb
Host smart-72af0e11-cba1-4fba-a6df-ac86f9beeb7c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511357584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.511357584
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2112212511
Short name T315
Test name
Test status
Simulation time 33373899 ps
CPU time 0.72 seconds
Started Jul 22 05:45:14 PM PDT 24
Finished Jul 22 05:45:16 PM PDT 24
Peak memory 204772 kb
Host smart-16993a42-3809-47eb-99fe-f475a54a98f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112212511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2112212511
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1310075434
Short name T411
Test name
Test status
Simulation time 4051136490 ps
CPU time 7.92 seconds
Started Jul 22 05:45:15 PM PDT 24
Finished Jul 22 05:45:23 PM PDT 24
Peak memory 205016 kb
Host smart-e4eeecd6-9b3a-4835-b497-9d70c122eee1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310075434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1310075434
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2375009523
Short name T421
Test name
Test status
Simulation time 74163986469 ps
CPU time 22.27 seconds
Started Jul 22 05:47:48 PM PDT 24
Finished Jul 22 05:48:11 PM PDT 24
Peak memory 229656 kb
Host smart-a7617319-9f41-48a9-9f27-96a6d388c827
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375009523 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2375009523
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3323372285
Short name T319
Test name
Test status
Simulation time 97979219 ps
CPU time 4.63 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:45:26 PM PDT 24
Peak memory 213320 kb
Host smart-5c55838f-b5f7-4c3e-8e18-77d2b4c3bc88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323372285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3323372285
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3545993593
Short name T378
Test name
Test status
Simulation time 9590007215 ps
CPU time 17.29 seconds
Started Jul 22 05:45:20 PM PDT 24
Finished Jul 22 05:45:38 PM PDT 24
Peak memory 221144 kb
Host smart-370f58c3-5aa3-4610-bb5e-e43eab8e1840
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545993593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3545993593
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1703403987
Short name T357
Test name
Test status
Simulation time 172827564 ps
CPU time 2.56 seconds
Started Jul 22 05:45:20 PM PDT 24
Finished Jul 22 05:45:23 PM PDT 24
Peak memory 217440 kb
Host smart-535a7299-e17f-4d9f-9275-8dd89bc38a9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703403987 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1703403987
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2114409265
Short name T87
Test name
Test status
Simulation time 72297908 ps
CPU time 1.44 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:45:24 PM PDT 24
Peak memory 213076 kb
Host smart-ff4d3e49-03f7-47cb-8fa7-4ba761c8d0df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114409265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2114409265
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4109020286
Short name T388
Test name
Test status
Simulation time 70891869664 ps
CPU time 37.47 seconds
Started Jul 22 05:45:12 PM PDT 24
Finished Jul 22 05:45:50 PM PDT 24
Peak memory 205024 kb
Host smart-bff7ec1e-0afb-4859-80d8-220b26da0591
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109020286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.4109020286
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2565751227
Short name T287
Test name
Test status
Simulation time 11367110569 ps
CPU time 8.68 seconds
Started Jul 22 05:45:23 PM PDT 24
Finished Jul 22 05:45:33 PM PDT 24
Peak memory 205044 kb
Host smart-5d5c62fb-7899-483e-a99c-2f6a4f901600
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565751227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
565751227
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.751160077
Short name T422
Test name
Test status
Simulation time 417854841 ps
CPU time 1.03 seconds
Started Jul 22 05:45:22 PM PDT 24
Finished Jul 22 05:45:25 PM PDT 24
Peak memory 204836 kb
Host smart-5047defa-d5c0-4c0a-b90b-7b7916dcefdb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751160077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.751160077
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1805486376
Short name T103
Test name
Test status
Simulation time 1948629753 ps
CPU time 4.46 seconds
Started Jul 22 05:45:12 PM PDT 24
Finished Jul 22 05:45:17 PM PDT 24
Peak memory 205072 kb
Host smart-eb933dc7-8ff0-4775-ab4c-5015783dba82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805486376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1805486376
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3586070503
Short name T399
Test name
Test status
Simulation time 27319177351 ps
CPU time 25.37 seconds
Started Jul 22 05:45:12 PM PDT 24
Finished Jul 22 05:45:38 PM PDT 24
Peak memory 221052 kb
Host smart-63d55bbc-076d-48da-95bf-3c059569a71c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586070503 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3586070503
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.624736074
Short name T379
Test name
Test status
Simulation time 157830717 ps
CPU time 3.01 seconds
Started Jul 22 05:47:49 PM PDT 24
Finished Jul 22 05:47:53 PM PDT 24
Peak memory 213204 kb
Host smart-32909bed-f00d-4d6a-ac81-63740f38083d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624736074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.624736074
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.231582488
Short name T145
Test name
Test status
Simulation time 3421154713 ps
CPU time 12.61 seconds
Started Jul 22 05:45:20 PM PDT 24
Finished Jul 22 05:45:33 PM PDT 24
Peak memory 213088 kb
Host smart-bad337c9-b46d-4c9c-b0f7-dda84f44ffb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231582488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.231582488
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3640674171
Short name T424
Test name
Test status
Simulation time 1189116650 ps
CPU time 4.14 seconds
Started Jul 22 05:45:23 PM PDT 24
Finished Jul 22 05:45:28 PM PDT 24
Peak memory 219584 kb
Host smart-06cef592-9fa3-496c-87aa-7568557dded7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640674171 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3640674171
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3119484478
Short name T404
Test name
Test status
Simulation time 186978781 ps
CPU time 1.47 seconds
Started Jul 22 05:45:19 PM PDT 24
Finished Jul 22 05:45:21 PM PDT 24
Peak memory 213296 kb
Host smart-3e9228d9-57b5-4e3c-b171-2697bb3519b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119484478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3119484478
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.409666766
Short name T352
Test name
Test status
Simulation time 53176126285 ps
CPU time 41.94 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:46:03 PM PDT 24
Peak memory 204908 kb
Host smart-54121984-5d8a-4df9-8e6b-fffbf37d9bba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409666766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
v_dm_jtag_dmi_csr_bit_bash.409666766
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3214656688
Short name T370
Test name
Test status
Simulation time 2335678853 ps
CPU time 7.33 seconds
Started Jul 22 05:47:49 PM PDT 24
Finished Jul 22 05:47:57 PM PDT 24
Peak memory 204952 kb
Host smart-684c7175-23ba-4871-81da-5ec23534c08c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214656688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
214656688
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2682772138
Short name T382
Test name
Test status
Simulation time 285178802 ps
CPU time 1.05 seconds
Started Jul 22 05:45:12 PM PDT 24
Finished Jul 22 05:45:14 PM PDT 24
Peak memory 204788 kb
Host smart-15c0f5a0-a553-4398-b134-a6a06f973b07
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682772138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
682772138
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.169542672
Short name T350
Test name
Test status
Simulation time 313675551 ps
CPU time 6.25 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:45:29 PM PDT 24
Peak memory 205028 kb
Host smart-c9e36cc7-9bbc-4dfe-a5de-7f9cf819d591
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169542672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c
sr_outstanding.169542672
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2604153597
Short name T122
Test name
Test status
Simulation time 49913340987 ps
CPU time 216.33 seconds
Started Jul 22 05:45:23 PM PDT 24
Finished Jul 22 05:49:00 PM PDT 24
Peak memory 221468 kb
Host smart-28b1e0a2-3723-4fdd-96b1-c7c6cfd38ba4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604153597 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.2604153597
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.309697103
Short name T290
Test name
Test status
Simulation time 3983973286 ps
CPU time 8.21 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:45:30 PM PDT 24
Peak memory 213264 kb
Host smart-572245b5-e80e-491d-92c7-723ff70c7c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309697103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.309697103
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1207675903
Short name T76
Test name
Test status
Simulation time 2529269496 ps
CPU time 23.2 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:45:44 PM PDT 24
Peak memory 213324 kb
Host smart-4fbd83cc-4036-4f16-9a35-e6616d9471ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207675903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1207675903
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3079627985
Short name T310
Test name
Test status
Simulation time 110718458 ps
CPU time 2.21 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:45:24 PM PDT 24
Peak memory 216580 kb
Host smart-4794f653-58b2-4a66-8053-677c7a1d9004
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079627985 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3079627985
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3160937167
Short name T106
Test name
Test status
Simulation time 163049692 ps
CPU time 1.67 seconds
Started Jul 22 05:45:20 PM PDT 24
Finished Jul 22 05:45:22 PM PDT 24
Peak memory 213192 kb
Host smart-2d2b504d-9362-414d-99c6-e05e5aed7103
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160937167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3160937167
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2843957315
Short name T302
Test name
Test status
Simulation time 3544422148 ps
CPU time 4.12 seconds
Started Jul 22 05:45:25 PM PDT 24
Finished Jul 22 05:45:30 PM PDT 24
Peak memory 204956 kb
Host smart-b5459cd3-cf6d-4b53-9f33-d3ca9d4eb631
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843957315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2843957315
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.102985197
Short name T361
Test name
Test status
Simulation time 1751528752 ps
CPU time 5.83 seconds
Started Jul 22 05:45:23 PM PDT 24
Finished Jul 22 05:45:30 PM PDT 24
Peak memory 204980 kb
Host smart-9fb93c91-b83a-4027-b17f-0c33163b3023
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102985197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.102985197
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1528644875
Short name T286
Test name
Test status
Simulation time 454258100 ps
CPU time 1.34 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:45:24 PM PDT 24
Peak memory 204788 kb
Host smart-93c06148-7956-43f8-a61d-e5b9e2e5275d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528644875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
528644875
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.467818343
Short name T85
Test name
Test status
Simulation time 672496589 ps
CPU time 4.38 seconds
Started Jul 22 05:45:25 PM PDT 24
Finished Jul 22 05:45:30 PM PDT 24
Peak memory 204960 kb
Host smart-cee4484e-b8cd-4974-8da0-8cbb8595e81a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467818343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.467818343
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2683228908
Short name T152
Test name
Test status
Simulation time 50821810952 ps
CPU time 238.45 seconds
Started Jul 22 05:48:00 PM PDT 24
Finished Jul 22 05:52:00 PM PDT 24
Peak memory 221604 kb
Host smart-dcb1d324-99ac-4f1d-adcc-d0d30c09e307
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683228908 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2683228908
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.122990463
Short name T327
Test name
Test status
Simulation time 1105079445 ps
CPU time 6.63 seconds
Started Jul 22 05:45:22 PM PDT 24
Finished Jul 22 05:45:30 PM PDT 24
Peak memory 213512 kb
Host smart-fa17c824-1a09-4628-9ff4-bd2fb6d748b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122990463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.122990463
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.123048953
Short name T148
Test name
Test status
Simulation time 1854416933 ps
CPU time 12.64 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:45:34 PM PDT 24
Peak memory 213236 kb
Host smart-7bc0e370-f715-4989-bbb7-836456a06fe3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123048953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.123048953
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2670687537
Short name T398
Test name
Test status
Simulation time 806268274 ps
CPU time 2.42 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:45:24 PM PDT 24
Peak memory 216148 kb
Host smart-9bd44e77-d8c0-485f-bd2e-95e6052734b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670687537 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2670687537
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2772823658
Short name T80
Test name
Test status
Simulation time 257823574 ps
CPU time 1.6 seconds
Started Jul 22 05:45:22 PM PDT 24
Finished Jul 22 05:45:24 PM PDT 24
Peak memory 213196 kb
Host smart-e96fcecf-0977-459c-828f-116d324914d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772823658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2772823658
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3083476233
Short name T284
Test name
Test status
Simulation time 28237421295 ps
CPU time 61.32 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:46:23 PM PDT 24
Peak memory 205064 kb
Host smart-fcd9c768-6ead-4fd3-9f49-b242e0500ec6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083476233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.3083476233
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3371757634
Short name T343
Test name
Test status
Simulation time 4079902542 ps
CPU time 4.65 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:45:27 PM PDT 24
Peak memory 204964 kb
Host smart-8bc34f1a-1840-4d80-85a2-7b300be095eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371757634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
371757634
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.894441211
Short name T335
Test name
Test status
Simulation time 697270434 ps
CPU time 1.53 seconds
Started Jul 22 05:45:23 PM PDT 24
Finished Jul 22 05:45:25 PM PDT 24
Peak memory 204744 kb
Host smart-bc4535c7-cc98-4254-b826-d788027e3333
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894441211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.894441211
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.901475284
Short name T364
Test name
Test status
Simulation time 479369097 ps
CPU time 7.35 seconds
Started Jul 22 05:45:24 PM PDT 24
Finished Jul 22 05:45:32 PM PDT 24
Peak memory 204996 kb
Host smart-b17dfcd5-4f2c-413a-b5da-aacb08e3be00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901475284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.901475284
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3691259281
Short name T295
Test name
Test status
Simulation time 8345956416 ps
CPU time 25.72 seconds
Started Jul 22 05:45:23 PM PDT 24
Finished Jul 22 05:45:50 PM PDT 24
Peak memory 221352 kb
Host smart-9f6a068a-3890-4978-a057-3190021e0dda
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691259281 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3691259281
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2738156301
Short name T78
Test name
Test status
Simulation time 2544286770 ps
CPU time 6.01 seconds
Started Jul 22 05:45:22 PM PDT 24
Finished Jul 22 05:45:29 PM PDT 24
Peak memory 213292 kb
Host smart-56a37e34-a256-4ad5-9cf7-3a1e938ffa32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738156301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2738156301
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1687251635
Short name T151
Test name
Test status
Simulation time 2032376133 ps
CPU time 15.83 seconds
Started Jul 22 05:45:20 PM PDT 24
Finished Jul 22 05:45:37 PM PDT 24
Peak memory 213228 kb
Host smart-ada4b26a-7f3d-4018-bf2b-f8d63249299c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687251635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1687251635
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2774946537
Short name T89
Test name
Test status
Simulation time 802337121 ps
CPU time 2.46 seconds
Started Jul 22 05:45:22 PM PDT 24
Finished Jul 22 05:45:25 PM PDT 24
Peak memory 217348 kb
Host smart-e738309e-7d7d-4378-98a9-9512e02757e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774946537 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2774946537
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1206930603
Short name T318
Test name
Test status
Simulation time 23998922242 ps
CPU time 29.98 seconds
Started Jul 22 05:45:23 PM PDT 24
Finished Jul 22 05:45:54 PM PDT 24
Peak memory 204996 kb
Host smart-dfb508b7-2e8b-48ae-81a2-2d916f50e559
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206930603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.1206930603
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1186364897
Short name T405
Test name
Test status
Simulation time 6844399961 ps
CPU time 6.37 seconds
Started Jul 22 05:45:23 PM PDT 24
Finished Jul 22 05:45:31 PM PDT 24
Peak memory 204964 kb
Host smart-410334e0-06f5-4d7c-a6fb-0c5f7a7152a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186364897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
186364897
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2966266362
Short name T339
Test name
Test status
Simulation time 154645145 ps
CPU time 0.97 seconds
Started Jul 22 05:45:23 PM PDT 24
Finished Jul 22 05:45:25 PM PDT 24
Peak memory 204784 kb
Host smart-68838bde-18c6-4648-9d97-c10fb1b8f8bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966266362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
966266362
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.80849471
Short name T345
Test name
Test status
Simulation time 171760539 ps
CPU time 3.6 seconds
Started Jul 22 05:45:21 PM PDT 24
Finished Jul 22 05:45:25 PM PDT 24
Peak memory 205056 kb
Host smart-8547ca58-f2bc-4291-ac66-de6f9e502d7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80849471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_cs
r_outstanding.80849471
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.561907241
Short name T410
Test name
Test status
Simulation time 42884902979 ps
CPU time 129.18 seconds
Started Jul 22 05:48:00 PM PDT 24
Finished Jul 22 05:50:10 PM PDT 24
Peak memory 221592 kb
Host smart-330e3ea3-98ad-4de5-9e4f-5d87887d4a21
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561907241 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.561907241
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2728449618
Short name T121
Test name
Test status
Simulation time 155637977 ps
CPU time 3.01 seconds
Started Jul 22 05:45:24 PM PDT 24
Finished Jul 22 05:45:28 PM PDT 24
Peak memory 213368 kb
Host smart-c197d501-1d2a-4e15-8da7-3d78e4aacada
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728449618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2728449618
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.176126829
Short name T142
Test name
Test status
Simulation time 3937286749 ps
CPU time 12.26 seconds
Started Jul 22 05:45:22 PM PDT 24
Finished Jul 22 05:45:35 PM PDT 24
Peak memory 213328 kb
Host smart-0bce88e7-b815-4b05-9136-85d16ac95d47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176126829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.176126829
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1238080050
Short name T202
Test name
Test status
Simulation time 104710054 ps
CPU time 0.8 seconds
Started Jul 22 05:45:44 PM PDT 24
Finished Jul 22 05:45:46 PM PDT 24
Peak memory 204724 kb
Host smart-4a977932-245f-4aca-90fe-0eb054186a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238080050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1238080050
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1184091811
Short name T48
Test name
Test status
Simulation time 17097127690 ps
CPU time 51.79 seconds
Started Jul 22 05:45:44 PM PDT 24
Finished Jul 22 05:46:37 PM PDT 24
Peak memory 213396 kb
Host smart-feb229a6-ac44-4a90-bd4a-3207e5d0b843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184091811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1184091811
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1131679919
Short name T268
Test name
Test status
Simulation time 1298146062 ps
CPU time 2.64 seconds
Started Jul 22 05:45:43 PM PDT 24
Finished Jul 22 05:45:46 PM PDT 24
Peak memory 213400 kb
Host smart-84cc0094-b6ab-42bc-8357-df4f6e7fc33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131679919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1131679919
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1883385984
Short name T25
Test name
Test status
Simulation time 729245827 ps
CPU time 1.25 seconds
Started Jul 22 05:45:42 PM PDT 24
Finished Jul 22 05:45:44 PM PDT 24
Peak memory 204652 kb
Host smart-3db84090-110f-41b7-98de-9e4fe00465aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883385984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1883385984
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.226094847
Short name T234
Test name
Test status
Simulation time 684719226 ps
CPU time 2.66 seconds
Started Jul 22 05:45:43 PM PDT 24
Finished Jul 22 05:45:47 PM PDT 24
Peak memory 204576 kb
Host smart-909f140b-fcb6-4bfe-8a0b-26cc6108d250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226094847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.226094847
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1806885572
Short name T120
Test name
Test status
Simulation time 287001162 ps
CPU time 0.81 seconds
Started Jul 22 05:45:38 PM PDT 24
Finished Jul 22 05:45:40 PM PDT 24
Peak memory 204716 kb
Host smart-838743cd-4282-4edf-b172-baa545e96813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806885572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1806885572
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.4052729859
Short name T248
Test name
Test status
Simulation time 5472051778 ps
CPU time 8.89 seconds
Started Jul 22 05:45:46 PM PDT 24
Finished Jul 22 05:45:56 PM PDT 24
Peak memory 214396 kb
Host smart-cf867024-3265-42fe-b857-97c62fe94804
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4052729859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.4052729859
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.1314032525
Short name T47
Test name
Test status
Simulation time 206761943 ps
CPU time 0.74 seconds
Started Jul 22 05:45:41 PM PDT 24
Finished Jul 22 05:45:42 PM PDT 24
Peak memory 204724 kb
Host smart-cf336720-1f84-4e9b-a09e-7497457a92a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314032525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.1314032525
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.878923033
Short name T155
Test name
Test status
Simulation time 379598674 ps
CPU time 1.39 seconds
Started Jul 22 05:47:44 PM PDT 24
Finished Jul 22 05:47:46 PM PDT 24
Peak memory 204644 kb
Host smart-d3438025-7109-4ad2-ba70-872d1681f394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878923033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.878923033
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2150057742
Short name T197
Test name
Test status
Simulation time 158861964 ps
CPU time 0.77 seconds
Started Jul 22 05:45:40 PM PDT 24
Finished Jul 22 05:45:41 PM PDT 24
Peak memory 204648 kb
Host smart-c648f4a3-8f88-4fec-957b-8da05c684046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150057742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2150057742
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2869021845
Short name T206
Test name
Test status
Simulation time 476527254 ps
CPU time 1.86 seconds
Started Jul 22 05:45:44 PM PDT 24
Finished Jul 22 05:45:47 PM PDT 24
Peak memory 204732 kb
Host smart-92322c8d-d170-41b2-a564-2b322c91177a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869021845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2869021845
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.122154641
Short name T277
Test name
Test status
Simulation time 467134215 ps
CPU time 0.99 seconds
Started Jul 22 05:45:38 PM PDT 24
Finished Jul 22 05:45:40 PM PDT 24
Peak memory 204852 kb
Host smart-92fb2fd2-a08d-430d-bab3-faf6bc3c0c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122154641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.122154641
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1080538488
Short name T224
Test name
Test status
Simulation time 123962693 ps
CPU time 0.99 seconds
Started Jul 22 05:45:46 PM PDT 24
Finished Jul 22 05:45:49 PM PDT 24
Peak memory 204632 kb
Host smart-6ede07a6-a286-46fa-a36a-b758ec372cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080538488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1080538488
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3392340503
Short name T7
Test name
Test status
Simulation time 1358796564 ps
CPU time 1.53 seconds
Started Jul 22 05:45:41 PM PDT 24
Finished Jul 22 05:45:44 PM PDT 24
Peak memory 204976 kb
Host smart-d1c19b81-d69a-480e-8357-5fbbe8a7b368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392340503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3392340503
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3113608027
Short name T274
Test name
Test status
Simulation time 157708417 ps
CPU time 0.8 seconds
Started Jul 22 05:45:50 PM PDT 24
Finished Jul 22 05:45:51 PM PDT 24
Peak memory 212892 kb
Host smart-cccef7ef-8501-4a58-8b57-2003893b6c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113608027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3113608027
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.754354303
Short name T40
Test name
Test status
Simulation time 909600813 ps
CPU time 1.9 seconds
Started Jul 22 05:45:44 PM PDT 24
Finished Jul 22 05:45:47 PM PDT 24
Peak memory 204680 kb
Host smart-1c25bf33-d16f-4f22-bfad-4d472cbc5d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754354303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.754354303
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.761076060
Short name T36
Test name
Test status
Simulation time 72113060 ps
CPU time 0.96 seconds
Started Jul 22 05:45:46 PM PDT 24
Finished Jul 22 05:45:48 PM PDT 24
Peak memory 212888 kb
Host smart-1e5c8568-edfa-4254-945a-1f9b70269052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761076060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.761076060
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.4137071312
Short name T69
Test name
Test status
Simulation time 3376197516 ps
CPU time 1.62 seconds
Started Jul 22 05:45:41 PM PDT 24
Finished Jul 22 05:45:44 PM PDT 24
Peak memory 204904 kb
Host smart-add4c8dd-7652-4d1f-9693-66bd61b8f948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137071312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.4137071312
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2137286110
Short name T223
Test name
Test status
Simulation time 1617094763 ps
CPU time 1.75 seconds
Started Jul 22 05:45:47 PM PDT 24
Finished Jul 22 05:45:50 PM PDT 24
Peak memory 205036 kb
Host smart-0e63a43f-1747-42c3-a55c-9cbf0eda02dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137286110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2137286110
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.156245220
Short name T9
Test name
Test status
Simulation time 616790179 ps
CPU time 1.73 seconds
Started Jul 22 05:45:46 PM PDT 24
Finished Jul 22 05:45:49 PM PDT 24
Peak memory 204628 kb
Host smart-a3024240-3fac-47fa-900d-48de54bea5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156245220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.156245220
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.687237034
Short name T64
Test name
Test status
Simulation time 7983873114 ps
CPU time 3.83 seconds
Started Jul 22 05:45:43 PM PDT 24
Finished Jul 22 05:45:48 PM PDT 24
Peak memory 204972 kb
Host smart-82baa935-8b29-42fd-98a9-129b2a6e177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687237034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.687237034
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.680972506
Short name T38
Test name
Test status
Simulation time 115481680 ps
CPU time 0.96 seconds
Started Jul 22 05:45:51 PM PDT 24
Finished Jul 22 05:45:53 PM PDT 24
Peak memory 204692 kb
Host smart-0e83e204-dd42-415a-95be-1fe82bd11f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680972506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.680972506
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1557049145
Short name T209
Test name
Test status
Simulation time 59268347 ps
CPU time 0.71 seconds
Started Jul 22 05:45:58 PM PDT 24
Finished Jul 22 05:45:59 PM PDT 24
Peak memory 204768 kb
Host smart-d599f269-b5df-4888-89c0-5f2b5afba75b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557049145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1557049145
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2826251693
Short name T244
Test name
Test status
Simulation time 14141031449 ps
CPU time 20.06 seconds
Started Jul 22 05:45:50 PM PDT 24
Finished Jul 22 05:46:11 PM PDT 24
Peak memory 213380 kb
Host smart-513547df-71be-4752-b7c3-660ec9722a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826251693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2826251693
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.719682357
Short name T39
Test name
Test status
Simulation time 243955634 ps
CPU time 1.35 seconds
Started Jul 22 05:45:46 PM PDT 24
Finished Jul 22 05:45:48 PM PDT 24
Peak memory 204716 kb
Host smart-bade831e-17c6-4973-ade7-aab5ef4c5dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719682357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.719682357
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3235918023
Short name T32
Test name
Test status
Simulation time 197837377 ps
CPU time 1.15 seconds
Started Jul 22 05:45:54 PM PDT 24
Finished Jul 22 05:45:56 PM PDT 24
Peak memory 204712 kb
Host smart-20857cf6-43d9-4e5c-9102-d21496a85c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235918023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3235918023
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3007724191
Short name T156
Test name
Test status
Simulation time 779412202 ps
CPU time 2.37 seconds
Started Jul 22 05:45:50 PM PDT 24
Finished Jul 22 05:45:53 PM PDT 24
Peak memory 204688 kb
Host smart-b202ea85-75b8-4d77-b187-fc705ef7876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007724191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3007724191
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3990418817
Short name T160
Test name
Test status
Simulation time 123921929 ps
CPU time 0.78 seconds
Started Jul 22 05:45:50 PM PDT 24
Finished Jul 22 05:45:52 PM PDT 24
Peak memory 204632 kb
Host smart-5fd5778d-bab8-4261-8a8e-0c6420005d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990418817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3990418817
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.1629703605
Short name T53
Test name
Test status
Simulation time 60970041 ps
CPU time 1.05 seconds
Started Jul 22 05:45:52 PM PDT 24
Finished Jul 22 05:45:54 PM PDT 24
Peak memory 215024 kb
Host smart-04d0f179-e96b-4069-91fd-a76642adcc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629703605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1629703605
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.629334315
Short name T246
Test name
Test status
Simulation time 3750846766 ps
CPU time 4.31 seconds
Started Jul 22 05:48:19 PM PDT 24
Finished Jul 22 05:48:25 PM PDT 24
Peak memory 213392 kb
Host smart-5d61344c-c4bb-4a9a-9b0b-0af12d8cc58d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=629334315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl
_access.629334315
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2660314007
Short name T201
Test name
Test status
Simulation time 1810442107 ps
CPU time 1.73 seconds
Started Jul 22 05:45:50 PM PDT 24
Finished Jul 22 05:45:52 PM PDT 24
Peak memory 204648 kb
Host smart-605bd84a-8a24-45b2-86a5-667ad3fc50f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660314007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2660314007
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3895907122
Short name T8
Test name
Test status
Simulation time 73705150 ps
CPU time 0.87 seconds
Started Jul 22 05:45:52 PM PDT 24
Finished Jul 22 05:45:54 PM PDT 24
Peak memory 204612 kb
Host smart-ae70c9d0-2a1b-4ed3-8ea7-9985bc7276a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895907122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3895907122
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2018477777
Short name T250
Test name
Test status
Simulation time 149487386 ps
CPU time 0.84 seconds
Started Jul 22 05:45:51 PM PDT 24
Finished Jul 22 05:45:53 PM PDT 24
Peak memory 204648 kb
Host smart-c39ccfda-1b02-434b-9aa7-cdf1483538c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018477777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2018477777
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.283153639
Short name T28
Test name
Test status
Simulation time 298714691 ps
CPU time 1.59 seconds
Started Jul 22 05:45:50 PM PDT 24
Finished Jul 22 05:45:53 PM PDT 24
Peak memory 204620 kb
Host smart-9861f5fb-7acf-427c-81ef-591a1f99adfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283153639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.283153639
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1436465466
Short name T259
Test name
Test status
Simulation time 114934091 ps
CPU time 1 seconds
Started Jul 22 05:45:55 PM PDT 24
Finished Jul 22 05:45:57 PM PDT 24
Peak memory 204708 kb
Host smart-9d7db460-cba0-4873-bc61-cd451be21f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436465466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1436465466
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.244075254
Short name T200
Test name
Test status
Simulation time 639918630 ps
CPU time 2.15 seconds
Started Jul 22 05:45:55 PM PDT 24
Finished Jul 22 05:45:58 PM PDT 24
Peak memory 204712 kb
Host smart-51f080e0-4a22-46aa-bc67-ba908e0269a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244075254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.244075254
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3806752280
Short name T157
Test name
Test status
Simulation time 359846339 ps
CPU time 1.24 seconds
Started Jul 22 05:45:50 PM PDT 24
Finished Jul 22 05:45:51 PM PDT 24
Peak memory 204504 kb
Host smart-5d801aaf-4a17-42c3-a7b7-43e953988928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806752280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3806752280
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2687988437
Short name T159
Test name
Test status
Simulation time 431615857 ps
CPU time 1.95 seconds
Started Jul 22 05:45:50 PM PDT 24
Finished Jul 22 05:45:53 PM PDT 24
Peak memory 204632 kb
Host smart-b1a0c920-6d81-480c-b2b6-c808aec507f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687988437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2687988437
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2669456226
Short name T79
Test name
Test status
Simulation time 148815575 ps
CPU time 0.83 seconds
Started Jul 22 05:45:51 PM PDT 24
Finished Jul 22 05:45:54 PM PDT 24
Peak memory 212916 kb
Host smart-af0b06c6-dd0d-437f-bb2e-9b0e84357f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669456226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2669456226
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1946968283
Short name T21
Test name
Test status
Simulation time 2814646220 ps
CPU time 8.67 seconds
Started Jul 22 05:45:55 PM PDT 24
Finished Jul 22 05:46:04 PM PDT 24
Peak memory 204824 kb
Host smart-5ca0a180-69c3-4025-a460-41adbf23447e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946968283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1946968283
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.289182116
Short name T222
Test name
Test status
Simulation time 839841813 ps
CPU time 3.23 seconds
Started Jul 22 05:45:43 PM PDT 24
Finished Jul 22 05:45:48 PM PDT 24
Peak memory 205140 kb
Host smart-95a5625e-d992-4ba4-8941-5308bf65a2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289182116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.289182116
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2724329473
Short name T60
Test name
Test status
Simulation time 228802123 ps
CPU time 1.45 seconds
Started Jul 22 05:45:47 PM PDT 24
Finished Jul 22 05:45:50 PM PDT 24
Peak memory 229432 kb
Host smart-59146c27-afe0-4f24-b0e1-7429b4ec668f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724329473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2724329473
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.4273728833
Short name T217
Test name
Test status
Simulation time 2585475198 ps
CPU time 4.65 seconds
Started Jul 22 05:45:46 PM PDT 24
Finished Jul 22 05:45:52 PM PDT 24
Peak memory 204684 kb
Host smart-9a0021a8-b614-4e4b-8265-aa007a71164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273728833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.4273728833
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.1143161078
Short name T129
Test name
Test status
Simulation time 2458078649 ps
CPU time 4.58 seconds
Started Jul 22 05:45:53 PM PDT 24
Finished Jul 22 05:45:58 PM PDT 24
Peak memory 213140 kb
Host smart-a0dbd18f-0468-4f09-852b-2ac61d3022da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143161078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1143161078
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1480461872
Short name T238
Test name
Test status
Simulation time 27908896 ps
CPU time 0.77 seconds
Started Jul 22 05:46:11 PM PDT 24
Finished Jul 22 05:46:13 PM PDT 24
Peak memory 204756 kb
Host smart-6e694b05-6b3b-4fdf-baae-3a53c4bdd64f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480461872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1480461872
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2660253152
Short name T275
Test name
Test status
Simulation time 5251389435 ps
CPU time 3.57 seconds
Started Jul 22 05:46:07 PM PDT 24
Finished Jul 22 05:46:12 PM PDT 24
Peak memory 215308 kb
Host smart-08ebdb9d-42dc-4b34-94be-94a5ecd62b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660253152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2660253152
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.4051369797
Short name T279
Test name
Test status
Simulation time 3732894066 ps
CPU time 3.32 seconds
Started Jul 22 05:46:13 PM PDT 24
Finished Jul 22 05:46:16 PM PDT 24
Peak memory 213392 kb
Host smart-5becc98c-01b4-4a8a-ae78-d7c804502531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051369797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.4051369797
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2191840389
Short name T242
Test name
Test status
Simulation time 4378344723 ps
CPU time 2.24 seconds
Started Jul 22 05:46:08 PM PDT 24
Finished Jul 22 05:46:11 PM PDT 24
Peak memory 213448 kb
Host smart-c902ce91-c281-4198-84a0-3b65c42719a6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2191840389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2191840389
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.398784960
Short name T63
Test name
Test status
Simulation time 11443425922 ps
CPU time 17.3 seconds
Started Jul 22 05:46:14 PM PDT 24
Finished Jul 22 05:46:32 PM PDT 24
Peak memory 213428 kb
Host smart-e3fc6779-032c-4acb-b526-d11a02c679bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398784960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.398784960
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2922764155
Short name T203
Test name
Test status
Simulation time 160457858 ps
CPU time 0.79 seconds
Started Jul 22 05:46:09 PM PDT 24
Finished Jul 22 05:46:10 PM PDT 24
Peak memory 204736 kb
Host smart-2fbfa94d-6179-4d5d-bc45-8e0056468ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922764155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2922764155
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.12424145
Short name T176
Test name
Test status
Simulation time 22553910033 ps
CPU time 16.9 seconds
Started Jul 22 05:46:12 PM PDT 24
Finished Jul 22 05:46:29 PM PDT 24
Peak memory 213468 kb
Host smart-bdad481e-74e6-414e-bba4-6b284992f306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12424145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.12424145
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.451982655
Short name T218
Test name
Test status
Simulation time 2597652320 ps
CPU time 7.43 seconds
Started Jul 22 05:46:10 PM PDT 24
Finished Jul 22 05:46:19 PM PDT 24
Peak memory 205164 kb
Host smart-987aa891-c882-41cf-8785-a222977dddd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451982655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.451982655
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1508534439
Short name T220
Test name
Test status
Simulation time 4761098440 ps
CPU time 4.45 seconds
Started Jul 22 05:46:11 PM PDT 24
Finished Jul 22 05:46:16 PM PDT 24
Peak memory 213380 kb
Host smart-f5b9239c-e7ea-471d-8c12-3b4ac5c36d6c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508534439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1508534439
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3217893031
Short name T264
Test name
Test status
Simulation time 2099565432 ps
CPU time 7.43 seconds
Started Jul 22 05:46:09 PM PDT 24
Finished Jul 22 05:46:17 PM PDT 24
Peak memory 205116 kb
Host smart-1e035cc0-51dc-4502-8a7d-49d803e7caf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217893031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3217893031
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2065234635
Short name T1
Test name
Test status
Simulation time 46787988 ps
CPU time 0.71 seconds
Started Jul 22 05:46:09 PM PDT 24
Finished Jul 22 05:46:11 PM PDT 24
Peak memory 204780 kb
Host smart-600eb7ce-c898-4aa0-ad89-bb8f088ba93f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065234635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2065234635
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.4104006172
Short name T261
Test name
Test status
Simulation time 4448043320 ps
CPU time 8.08 seconds
Started Jul 22 05:46:13 PM PDT 24
Finished Jul 22 05:46:21 PM PDT 24
Peak memory 205096 kb
Host smart-1fac7df5-d4d6-484d-9e02-6315d4f05432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104006172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.4104006172
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3836382435
Short name T186
Test name
Test status
Simulation time 3059746500 ps
CPU time 2.29 seconds
Started Jul 22 05:47:05 PM PDT 24
Finished Jul 22 05:47:08 PM PDT 24
Peak memory 213524 kb
Host smart-34adaeb1-14ac-4e93-bc1f-b412da39308f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836382435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3836382435
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3615071655
Short name T212
Test name
Test status
Simulation time 1604081487 ps
CPU time 3.15 seconds
Started Jul 22 05:46:10 PM PDT 24
Finished Jul 22 05:46:15 PM PDT 24
Peak memory 205168 kb
Host smart-9a9db296-dae8-4411-afa8-4fdec3ad9bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615071655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3615071655
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.1258465436
Short name T17
Test name
Test status
Simulation time 6592080205 ps
CPU time 11.73 seconds
Started Jul 22 05:46:16 PM PDT 24
Finished Jul 22 05:46:28 PM PDT 24
Peak memory 213232 kb
Host smart-9d31cdb4-0699-4726-b573-f4648b7b36fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258465436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1258465436
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3977025470
Short name T208
Test name
Test status
Simulation time 72063822 ps
CPU time 0.78 seconds
Started Jul 22 05:46:16 PM PDT 24
Finished Jul 22 05:46:17 PM PDT 24
Peak memory 204796 kb
Host smart-4492724b-1ba9-445e-95a8-ede9173a96f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977025470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3977025470
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2546379516
Short name T185
Test name
Test status
Simulation time 100033962346 ps
CPU time 257.19 seconds
Started Jul 22 05:46:12 PM PDT 24
Finished Jul 22 05:50:30 PM PDT 24
Peak memory 217784 kb
Host smart-a5e0e4b7-e3e1-46ad-8663-f839b7f2267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546379516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2546379516
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.31470993
Short name T165
Test name
Test status
Simulation time 2141002339 ps
CPU time 2.92 seconds
Started Jul 22 05:46:12 PM PDT 24
Finished Jul 22 05:46:15 PM PDT 24
Peak memory 213496 kb
Host smart-24849d93-be1b-4ac3-aaa7-c38b26b5799d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31470993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.31470993
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1967649131
Short name T52
Test name
Test status
Simulation time 3279479954 ps
CPU time 4.96 seconds
Started Jul 22 05:46:09 PM PDT 24
Finished Jul 22 05:46:16 PM PDT 24
Peak memory 213308 kb
Host smart-8f4f6dd4-e78e-4584-930e-7152ac2cc389
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1967649131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1967649131
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2224360745
Short name T262
Test name
Test status
Simulation time 2912080078 ps
CPU time 9.41 seconds
Started Jul 22 05:46:12 PM PDT 24
Finished Jul 22 05:46:22 PM PDT 24
Peak memory 213288 kb
Host smart-58a372bd-7621-4817-b58a-dee907729e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224360745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2224360745
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.3212338561
Short name T132
Test name
Test status
Simulation time 4605213900 ps
CPU time 5.73 seconds
Started Jul 22 05:46:11 PM PDT 24
Finished Jul 22 05:46:18 PM PDT 24
Peak memory 213116 kb
Host smart-c3b774c5-776a-4b07-b544-89cd8f680726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212338561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3212338561
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.4026346056
Short name T171
Test name
Test status
Simulation time 94546127 ps
CPU time 0.73 seconds
Started Jul 22 05:46:10 PM PDT 24
Finished Jul 22 05:46:12 PM PDT 24
Peak memory 204636 kb
Host smart-83b76b90-4209-42c6-b9ea-f07ec9d71342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026346056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.4026346056
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2174282210
Short name T216
Test name
Test status
Simulation time 6829506884 ps
CPU time 17.67 seconds
Started Jul 22 05:46:08 PM PDT 24
Finished Jul 22 05:46:26 PM PDT 24
Peak memory 215232 kb
Host smart-bcf97f17-357c-4ba9-93fd-4d5beddf511f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174282210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2174282210
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1609444391
Short name T231
Test name
Test status
Simulation time 3887380701 ps
CPU time 4.13 seconds
Started Jul 22 05:46:10 PM PDT 24
Finished Jul 22 05:46:16 PM PDT 24
Peak memory 213324 kb
Host smart-d0159c43-bd4b-4e7d-8f78-f6a4a6a51791
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1609444391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1609444391
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1120626266
Short name T273
Test name
Test status
Simulation time 624515112 ps
CPU time 1.32 seconds
Started Jul 22 05:46:11 PM PDT 24
Finished Jul 22 05:46:13 PM PDT 24
Peak memory 205148 kb
Host smart-a453f284-1845-43fc-a285-e4214891e7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120626266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1120626266
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3216597008
Short name T251
Test name
Test status
Simulation time 64522027 ps
CPU time 0.71 seconds
Started Jul 22 05:46:10 PM PDT 24
Finished Jul 22 05:46:12 PM PDT 24
Peak memory 204700 kb
Host smart-02bf60e7-edff-4fab-96bc-86e9a7bc0f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216597008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3216597008
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3562169295
Short name T26
Test name
Test status
Simulation time 2539230043 ps
CPU time 2.96 seconds
Started Jul 22 05:46:11 PM PDT 24
Finished Jul 22 05:46:15 PM PDT 24
Peak memory 213404 kb
Host smart-cb933d00-c494-46c6-85a3-1b2bdffb4568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562169295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3562169295
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.581358682
Short name T195
Test name
Test status
Simulation time 1006135588 ps
CPU time 1.83 seconds
Started Jul 22 05:46:10 PM PDT 24
Finished Jul 22 05:46:13 PM PDT 24
Peak memory 205140 kb
Host smart-3ea295ed-41a2-464d-9b1d-8e2e15dfb30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581358682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.581358682
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.18191018
Short name T257
Test name
Test status
Simulation time 2138903198 ps
CPU time 1.46 seconds
Started Jul 22 05:46:09 PM PDT 24
Finished Jul 22 05:46:11 PM PDT 24
Peak memory 205016 kb
Host smart-c0402d35-4c4a-4fff-ade1-3085f2341fcd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18191018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl
_access.18191018
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.531328849
Short name T271
Test name
Test status
Simulation time 4735117930 ps
CPU time 13.96 seconds
Started Jul 22 05:46:10 PM PDT 24
Finished Jul 22 05:46:25 PM PDT 24
Peak memory 205256 kb
Host smart-da4ac6a4-80cc-4dd1-b95a-04170d2cb17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531328849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.531328849
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1943900051
Short name T34
Test name
Test status
Simulation time 14829874140 ps
CPU time 10.84 seconds
Started Jul 22 05:46:07 PM PDT 24
Finished Jul 22 05:46:19 PM PDT 24
Peak memory 213172 kb
Host smart-0a9546db-3c5d-4283-9646-1054db8d859d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943900051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1943900051
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3201355012
Short name T219
Test name
Test status
Simulation time 164197416 ps
CPU time 1.08 seconds
Started Jul 22 05:46:21 PM PDT 24
Finished Jul 22 05:46:23 PM PDT 24
Peak memory 204724 kb
Host smart-1dd2845e-244c-4c07-80a2-e87d113b8c07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201355012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3201355012
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.184375938
Short name T18
Test name
Test status
Simulation time 23332536282 ps
CPU time 8.12 seconds
Started Jul 22 05:46:11 PM PDT 24
Finished Jul 22 05:46:20 PM PDT 24
Peak memory 213400 kb
Host smart-4c4b3cec-3c8f-43ee-b7e4-417734250901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184375938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.184375938
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3937833844
Short name T260
Test name
Test status
Simulation time 2420934046 ps
CPU time 6.92 seconds
Started Jul 22 05:47:04 PM PDT 24
Finished Jul 22 05:47:11 PM PDT 24
Peak memory 213396 kb
Host smart-dd3564e2-1e13-4d9a-99a2-61a7766fddcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937833844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3937833844
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.266540130
Short name T255
Test name
Test status
Simulation time 1397775597 ps
CPU time 2.07 seconds
Started Jul 22 05:46:16 PM PDT 24
Finished Jul 22 05:46:19 PM PDT 24
Peak memory 205228 kb
Host smart-559e26a0-19d0-44b2-9c3d-e59c811af9a8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=266540130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.266540130
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2155354774
Short name T62
Test name
Test status
Simulation time 6739078114 ps
CPU time 10.49 seconds
Started Jul 22 05:46:09 PM PDT 24
Finished Jul 22 05:46:20 PM PDT 24
Peak memory 213348 kb
Host smart-38bbcd19-66db-4593-a6db-cafe76e7ac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155354774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2155354774
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.274483236
Short name T170
Test name
Test status
Simulation time 91867818 ps
CPU time 0.83 seconds
Started Jul 22 05:46:19 PM PDT 24
Finished Jul 22 05:46:20 PM PDT 24
Peak memory 204668 kb
Host smart-ccbcb7d5-2910-4e1e-a4f9-6c8c10a0c49a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274483236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.274483236
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3074839580
Short name T204
Test name
Test status
Simulation time 1208420133 ps
CPU time 2.46 seconds
Started Jul 22 05:46:19 PM PDT 24
Finished Jul 22 05:46:23 PM PDT 24
Peak memory 205168 kb
Host smart-16267e96-9f4e-4748-ab3c-9d42e4846207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074839580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3074839580
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3342750992
Short name T247
Test name
Test status
Simulation time 2877460403 ps
CPU time 2.93 seconds
Started Jul 22 05:46:21 PM PDT 24
Finished Jul 22 05:46:25 PM PDT 24
Peak memory 205196 kb
Host smart-0e5114dd-f0c7-4476-8203-b02cad87ab16
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3342750992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3342750992
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.2242056157
Short name T253
Test name
Test status
Simulation time 12994694637 ps
CPU time 11.3 seconds
Started Jul 22 05:46:20 PM PDT 24
Finished Jul 22 05:46:32 PM PDT 24
Peak memory 213440 kb
Host smart-9762b520-b902-4567-87c3-6cc91dd19221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242056157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2242056157
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1758149207
Short name T211
Test name
Test status
Simulation time 104039837 ps
CPU time 0.75 seconds
Started Jul 22 05:46:20 PM PDT 24
Finished Jul 22 05:46:21 PM PDT 24
Peak memory 204732 kb
Host smart-0f02ac45-c65f-47d3-96de-a4f747f5a235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758149207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1758149207
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.4204702922
Short name T207
Test name
Test status
Simulation time 2645207660 ps
CPU time 4.69 seconds
Started Jul 22 05:46:22 PM PDT 24
Finished Jul 22 05:46:28 PM PDT 24
Peak memory 205124 kb
Host smart-4e7bc0f6-3321-4340-98be-d9c1fafdbe89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204702922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.4204702922
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.121341060
Short name T227
Test name
Test status
Simulation time 9900319032 ps
CPU time 15.46 seconds
Started Jul 22 05:46:18 PM PDT 24
Finished Jul 22 05:46:34 PM PDT 24
Peak memory 213372 kb
Host smart-a305c1e9-8ead-4ac3-ac91-9cb53e7a4a28
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=121341060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.121341060
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.679066896
Short name T184
Test name
Test status
Simulation time 1488976641 ps
CPU time 3.91 seconds
Started Jul 22 05:46:23 PM PDT 24
Finished Jul 22 05:46:28 PM PDT 24
Peak memory 205140 kb
Host smart-fae64156-d2db-4c17-8bc4-780379149e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679066896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.679066896
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2174338874
Short name T177
Test name
Test status
Simulation time 5286771445 ps
CPU time 16.21 seconds
Started Jul 22 05:46:22 PM PDT 24
Finished Jul 22 05:46:39 PM PDT 24
Peak memory 213328 kb
Host smart-b169a1a3-05d0-4672-bc6d-afed1be6df15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174338874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2174338874
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1506687077
Short name T183
Test name
Test status
Simulation time 1701881749 ps
CPU time 5.61 seconds
Started Jul 22 05:48:34 PM PDT 24
Finished Jul 22 05:48:41 PM PDT 24
Peak memory 213332 kb
Host smart-9117ec0f-e511-4b76-b5a3-f28e4f978b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506687077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1506687077
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.882508481
Short name T278
Test name
Test status
Simulation time 1274273542 ps
CPU time 3.79 seconds
Started Jul 22 05:46:19 PM PDT 24
Finished Jul 22 05:46:24 PM PDT 24
Peak memory 205168 kb
Host smart-82975c9e-8cb5-4810-8083-9f758476c98a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=882508481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.882508481
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.791330465
Short name T280
Test name
Test status
Simulation time 2554228461 ps
CPU time 1.52 seconds
Started Jul 22 05:46:19 PM PDT 24
Finished Jul 22 05:46:22 PM PDT 24
Peak memory 205212 kb
Host smart-2ea87257-4e58-4b11-b13f-9d80502407f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791330465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.791330465
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.46107082
Short name T123
Test name
Test status
Simulation time 6673500814 ps
CPU time 12.6 seconds
Started Jul 22 05:46:21 PM PDT 24
Finished Jul 22 05:46:34 PM PDT 24
Peak memory 213168 kb
Host smart-87ff627d-58ec-49e8-97f7-7b4d1e8c324f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46107082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.46107082
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3365865284
Short name T235
Test name
Test status
Simulation time 29749479 ps
CPU time 0.72 seconds
Started Jul 22 05:45:51 PM PDT 24
Finished Jul 22 05:45:53 PM PDT 24
Peak memory 204716 kb
Host smart-29402329-af7c-445d-b367-81aee67c082a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365865284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3365865284
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1658147889
Short name T276
Test name
Test status
Simulation time 7288312973 ps
CPU time 6.57 seconds
Started Jul 22 05:45:54 PM PDT 24
Finished Jul 22 05:46:01 PM PDT 24
Peak memory 221556 kb
Host smart-2b3c5560-d318-40a9-9a80-e2cfaec2c958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658147889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1658147889
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3389955712
Short name T189
Test name
Test status
Simulation time 3401871983 ps
CPU time 10.17 seconds
Started Jul 22 05:45:55 PM PDT 24
Finished Jul 22 05:46:05 PM PDT 24
Peak memory 205260 kb
Host smart-3ed071aa-b66a-442f-b30c-d918b66578c8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3389955712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3389955712
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3401128074
Short name T126
Test name
Test status
Simulation time 376773691 ps
CPU time 0.99 seconds
Started Jul 22 05:45:51 PM PDT 24
Finished Jul 22 05:45:53 PM PDT 24
Peak memory 204708 kb
Host smart-e64cf244-380d-4b86-b426-8f2710adb108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401128074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3401128074
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3397715561
Short name T128
Test name
Test status
Simulation time 4713523102 ps
CPU time 8.51 seconds
Started Jul 22 05:45:52 PM PDT 24
Finished Jul 22 05:46:01 PM PDT 24
Peak memory 205180 kb
Host smart-ebf0367d-9591-4983-92ec-92b151bf9b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397715561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3397715561
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.767919756
Short name T45
Test name
Test status
Simulation time 487928312 ps
CPU time 1.69 seconds
Started Jul 22 05:45:50 PM PDT 24
Finished Jul 22 05:45:53 PM PDT 24
Peak memory 229140 kb
Host smart-f512057e-d24a-481e-bab2-2e6011af27c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767919756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.767919756
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.3861818947
Short name T15
Test name
Test status
Simulation time 7063630753 ps
CPU time 7.3 seconds
Started Jul 22 05:45:58 PM PDT 24
Finished Jul 22 05:46:06 PM PDT 24
Peak memory 205028 kb
Host smart-c67dee24-9e48-499a-af86-faad82959f4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861818947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3861818947
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2152248276
Short name T194
Test name
Test status
Simulation time 36276485 ps
CPU time 0.69 seconds
Started Jul 22 05:46:20 PM PDT 24
Finished Jul 22 05:46:21 PM PDT 24
Peak memory 204792 kb
Host smart-1ebc627c-5eb8-4c5b-9852-7763881bc8dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152248276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2152248276
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2965381404
Short name T175
Test name
Test status
Simulation time 3344219863 ps
CPU time 4.86 seconds
Started Jul 22 05:46:17 PM PDT 24
Finished Jul 22 05:46:23 PM PDT 24
Peak memory 204724 kb
Host smart-ff070567-4ecf-4599-9565-82a2df83d3cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965381404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2965381404
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3784237244
Short name T168
Test name
Test status
Simulation time 48169219 ps
CPU time 0.79 seconds
Started Jul 22 05:46:29 PM PDT 24
Finished Jul 22 05:46:30 PM PDT 24
Peak memory 204796 kb
Host smart-7c82980a-ef89-46f6-8223-418b2830de43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784237244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3784237244
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3279280364
Short name T214
Test name
Test status
Simulation time 107123784 ps
CPU time 0.71 seconds
Started Jul 22 05:46:26 PM PDT 24
Finished Jul 22 05:46:27 PM PDT 24
Peak memory 204716 kb
Host smart-dd5c3a24-f54d-4b3b-b6d2-1db7097c0162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279280364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3279280364
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.3599682719
Short name T54
Test name
Test status
Simulation time 4201889388 ps
CPU time 4.28 seconds
Started Jul 22 05:46:28 PM PDT 24
Finished Jul 22 05:46:33 PM PDT 24
Peak memory 213252 kb
Host smart-052615cd-11d8-40d3-ae0d-9cdf6029ced3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599682719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3599682719
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1310021053
Short name T243
Test name
Test status
Simulation time 213443068 ps
CPU time 0.88 seconds
Started Jul 22 05:48:23 PM PDT 24
Finished Jul 22 05:48:25 PM PDT 24
Peak memory 204716 kb
Host smart-36cba9c4-8a39-4a0a-97dd-09699ddd9b63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310021053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1310021053
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2645031302
Short name T61
Test name
Test status
Simulation time 40828779 ps
CPU time 0.73 seconds
Started Jul 22 05:46:18 PM PDT 24
Finished Jul 22 05:46:20 PM PDT 24
Peak memory 205012 kb
Host smart-f9251025-fbdc-49f9-86de-a449b6b3b416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645031302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2645031302
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3566005877
Short name T181
Test name
Test status
Simulation time 63079405 ps
CPU time 0.72 seconds
Started Jul 22 05:46:21 PM PDT 24
Finished Jul 22 05:46:23 PM PDT 24
Peak memory 204728 kb
Host smart-e038f166-3aa1-42ed-bb5c-49ddff4d0cff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566005877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3566005877
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2849835393
Short name T162
Test name
Test status
Simulation time 3710773439 ps
CPU time 3.43 seconds
Started Jul 22 05:46:29 PM PDT 24
Finished Jul 22 05:46:33 PM PDT 24
Peak memory 213196 kb
Host smart-a8e56587-025b-440b-b75b-1ae5b748be90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849835393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2849835393
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3126758549
Short name T270
Test name
Test status
Simulation time 31386874 ps
CPU time 0.73 seconds
Started Jul 22 05:46:21 PM PDT 24
Finished Jul 22 05:46:23 PM PDT 24
Peak memory 204784 kb
Host smart-9321080a-2ba9-48dd-b752-2485ae4f459a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126758549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3126758549
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.936754316
Short name T163
Test name
Test status
Simulation time 171444824 ps
CPU time 0.76 seconds
Started Jul 22 05:46:20 PM PDT 24
Finished Jul 22 05:46:21 PM PDT 24
Peak memory 204752 kb
Host smart-fa032be0-a32e-4833-a53b-3ccb776b7167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936754316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.936754316
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1835742664
Short name T191
Test name
Test status
Simulation time 45061013 ps
CPU time 0.75 seconds
Started Jul 22 05:46:26 PM PDT 24
Finished Jul 22 05:46:27 PM PDT 24
Peak memory 204744 kb
Host smart-112e7da2-e875-4a76-801e-2c6e2d9d60ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835742664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1835742664
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3924571337
Short name T118
Test name
Test status
Simulation time 53532584 ps
CPU time 0.71 seconds
Started Jul 22 05:46:23 PM PDT 24
Finished Jul 22 05:46:24 PM PDT 24
Peak memory 204772 kb
Host smart-d362d395-1ce4-487f-98aa-0fd80e4684db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924571337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3924571337
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.584081434
Short name T42
Test name
Test status
Simulation time 95489825 ps
CPU time 0.73 seconds
Started Jul 22 05:45:53 PM PDT 24
Finished Jul 22 05:45:54 PM PDT 24
Peak memory 204796 kb
Host smart-8896fa95-8542-4d85-9cfe-16d49df5578d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584081434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.584081434
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2498150893
Short name T228
Test name
Test status
Simulation time 5102556708 ps
CPU time 11.83 seconds
Started Jul 22 05:45:50 PM PDT 24
Finished Jul 22 05:46:03 PM PDT 24
Peak memory 213440 kb
Host smart-f27d175d-fc4c-4d42-a67e-ee25a09e3b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498150893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2498150893
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2162077102
Short name T233
Test name
Test status
Simulation time 2474632057 ps
CPU time 5 seconds
Started Jul 22 05:45:51 PM PDT 24
Finished Jul 22 05:45:57 PM PDT 24
Peak memory 205224 kb
Host smart-20e21ce1-5aa4-46d7-a6c9-fe0508f047e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162077102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2162077102
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2141701183
Short name T135
Test name
Test status
Simulation time 3154602296 ps
CPU time 3.18 seconds
Started Jul 22 05:45:51 PM PDT 24
Finished Jul 22 05:45:55 PM PDT 24
Peak memory 205148 kb
Host smart-b956532c-cc81-482c-b84d-ff26b98aa021
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141701183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2141701183
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2323061298
Short name T205
Test name
Test status
Simulation time 722832560 ps
CPU time 1.08 seconds
Started Jul 22 05:47:49 PM PDT 24
Finished Jul 22 05:47:51 PM PDT 24
Peak memory 204604 kb
Host smart-18a3bbcb-718d-4f0a-a96f-0751be28c51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323061298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2323061298
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.275570998
Short name T236
Test name
Test status
Simulation time 2557389939 ps
CPU time 8.08 seconds
Started Jul 22 05:45:52 PM PDT 24
Finished Jul 22 05:46:01 PM PDT 24
Peak memory 205248 kb
Host smart-642a973f-9133-4d17-8211-475bd3d4a5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275570998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.275570998
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3634823730
Short name T59
Test name
Test status
Simulation time 2524317357 ps
CPU time 4.24 seconds
Started Jul 22 05:45:55 PM PDT 24
Finished Jul 22 05:46:00 PM PDT 24
Peak memory 229340 kb
Host smart-5a99ca52-bd83-4235-b775-88538466e278
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634823730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3634823730
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.443153209
Short name T154
Test name
Test status
Simulation time 7486541478 ps
CPU time 11.85 seconds
Started Jul 22 05:45:52 PM PDT 24
Finished Jul 22 05:46:05 PM PDT 24
Peak memory 213164 kb
Host smart-265365ed-a27b-4eba-bf05-2bd2cda17569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443153209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.443153209
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.477708392
Short name T263
Test name
Test status
Simulation time 113012839 ps
CPU time 0.94 seconds
Started Jul 22 05:46:21 PM PDT 24
Finished Jul 22 05:46:23 PM PDT 24
Peak memory 204768 kb
Host smart-4640bb71-5c9c-4403-91d4-14358456e2d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477708392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.477708392
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.277107331
Short name T179
Test name
Test status
Simulation time 109217255 ps
CPU time 0.69 seconds
Started Jul 22 05:46:20 PM PDT 24
Finished Jul 22 05:46:21 PM PDT 24
Peak memory 204696 kb
Host smart-586145ad-32ae-4c4b-bee3-1dd4b49113ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277107331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.277107331
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2779025333
Short name T167
Test name
Test status
Simulation time 100409418 ps
CPU time 0.75 seconds
Started Jul 22 05:46:18 PM PDT 24
Finished Jul 22 05:46:19 PM PDT 24
Peak memory 204780 kb
Host smart-5ae034fc-86b9-4d5d-a734-bcef4d24f8b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779025333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2779025333
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3456768033
Short name T187
Test name
Test status
Simulation time 78759598 ps
CPU time 0.71 seconds
Started Jul 22 05:46:23 PM PDT 24
Finished Jul 22 05:46:24 PM PDT 24
Peak memory 204784 kb
Host smart-d1b45ad8-c507-453e-ad5a-6ad9c604d436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456768033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3456768033
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.2894378462
Short name T158
Test name
Test status
Simulation time 1718950784 ps
CPU time 2.26 seconds
Started Jul 22 05:46:23 PM PDT 24
Finished Jul 22 05:46:26 PM PDT 24
Peak memory 204892 kb
Host smart-81f02168-4e8f-4d21-aa71-a16ca7f8a703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894378462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2894378462
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2137779189
Short name T241
Test name
Test status
Simulation time 48869748 ps
CPU time 0.74 seconds
Started Jul 22 05:46:21 PM PDT 24
Finished Jul 22 05:46:23 PM PDT 24
Peak memory 204788 kb
Host smart-d81346a0-8171-4fc7-a1b8-e455e8138911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137779189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2137779189
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3252764329
Short name T169
Test name
Test status
Simulation time 79554931 ps
CPU time 0.71 seconds
Started Jul 22 05:46:21 PM PDT 24
Finished Jul 22 05:46:23 PM PDT 24
Peak memory 204772 kb
Host smart-2d134ecd-9b7e-45b3-8f6e-0d1b89356ca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252764329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3252764329
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2337640957
Short name T172
Test name
Test status
Simulation time 126322901 ps
CPU time 0.72 seconds
Started Jul 22 05:46:21 PM PDT 24
Finished Jul 22 05:46:22 PM PDT 24
Peak memory 204708 kb
Host smart-27becf63-cc25-4364-ad50-5e2cfbea0129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337640957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2337640957
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.2166330977
Short name T31
Test name
Test status
Simulation time 5077233711 ps
CPU time 15.88 seconds
Started Jul 22 05:46:24 PM PDT 24
Finished Jul 22 05:46:41 PM PDT 24
Peak memory 213112 kb
Host smart-673d6c5c-db98-477e-9704-2d5d15395fef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166330977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2166330977
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2175005425
Short name T174
Test name
Test status
Simulation time 62851410 ps
CPU time 0.68 seconds
Started Jul 22 05:46:20 PM PDT 24
Finished Jul 22 05:46:21 PM PDT 24
Peak memory 204688 kb
Host smart-7343d418-b256-4999-8d19-9018190ec55c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175005425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2175005425
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3486203312
Short name T196
Test name
Test status
Simulation time 83526877 ps
CPU time 0.74 seconds
Started Jul 22 05:46:19 PM PDT 24
Finished Jul 22 05:46:20 PM PDT 24
Peak memory 204792 kb
Host smart-0a7d1257-e3a1-4a5e-ac40-bbb5875b760a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486203312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3486203312
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.2842145958
Short name T138
Test name
Test status
Simulation time 3815077918 ps
CPU time 11.06 seconds
Started Jul 22 05:46:23 PM PDT 24
Finished Jul 22 05:46:35 PM PDT 24
Peak memory 213060 kb
Host smart-5e93312a-b4f5-4aca-a9d2-4c59038f77ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842145958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2842145958
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1174861540
Short name T249
Test name
Test status
Simulation time 59307668 ps
CPU time 0.73 seconds
Started Jul 22 05:46:22 PM PDT 24
Finished Jul 22 05:46:24 PM PDT 24
Peak memory 204768 kb
Host smart-a5ab83e2-6afb-4b62-8544-ea0db3705dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174861540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1174861540
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1803400035
Short name T265
Test name
Test status
Simulation time 52603763 ps
CPU time 0.74 seconds
Started Jul 22 05:45:58 PM PDT 24
Finished Jul 22 05:45:59 PM PDT 24
Peak memory 204768 kb
Host smart-08a6b4a9-e0ba-4d23-a150-a6c0d3a4d843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803400035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1803400035
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3946293867
Short name T30
Test name
Test status
Simulation time 26755276670 ps
CPU time 33.87 seconds
Started Jul 22 05:47:49 PM PDT 24
Finished Jul 22 05:48:24 PM PDT 24
Peak memory 213384 kb
Host smart-a5225856-a465-4ea5-9299-2690070b85e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946293867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3946293867
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3696617191
Short name T267
Test name
Test status
Simulation time 4181369008 ps
CPU time 4.02 seconds
Started Jul 22 05:45:54 PM PDT 24
Finished Jul 22 05:45:59 PM PDT 24
Peak memory 213464 kb
Host smart-bdf44f0a-bd7c-4212-be40-0ff5e222da16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696617191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3696617191
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1772453110
Short name T11
Test name
Test status
Simulation time 1573280335 ps
CPU time 3.48 seconds
Started Jul 22 05:45:58 PM PDT 24
Finished Jul 22 05:46:02 PM PDT 24
Peak memory 205184 kb
Host smart-a6f12e1c-8ce9-4ecf-b7d2-3241279c9c92
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772453110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1772453110
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.559360885
Short name T137
Test name
Test status
Simulation time 75088315 ps
CPU time 0.76 seconds
Started Jul 22 05:45:52 PM PDT 24
Finished Jul 22 05:45:54 PM PDT 24
Peak memory 204644 kb
Host smart-fbc1241f-9f06-407d-8945-739d3c8d2f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559360885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.559360885
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.4283883935
Short name T252
Test name
Test status
Simulation time 1603427339 ps
CPU time 4.33 seconds
Started Jul 22 05:45:53 PM PDT 24
Finished Jul 22 05:45:58 PM PDT 24
Peak memory 205088 kb
Host smart-d6bbc4e6-a9e6-42e0-9c80-e506c17e9db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283883935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.4283883935
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3141383215
Short name T44
Test name
Test status
Simulation time 725675671 ps
CPU time 1.41 seconds
Started Jul 22 05:45:52 PM PDT 24
Finished Jul 22 05:45:55 PM PDT 24
Peak memory 229640 kb
Host smart-caa5c0b5-8783-4e5e-a7c8-321596700b10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141383215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3141383215
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3297601429
Short name T188
Test name
Test status
Simulation time 123192272 ps
CPU time 1 seconds
Started Jul 22 05:46:21 PM PDT 24
Finished Jul 22 05:46:23 PM PDT 24
Peak memory 204768 kb
Host smart-930b1191-2a8d-44cb-980f-65878814f5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297601429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3297601429
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.4284669341
Short name T215
Test name
Test status
Simulation time 74408848 ps
CPU time 0.74 seconds
Started Jul 22 05:46:28 PM PDT 24
Finished Jul 22 05:46:29 PM PDT 24
Peak memory 204736 kb
Host smart-19485e36-33a1-456c-be8c-4fcd0cb19b26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284669341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.4284669341
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.234355141
Short name T131
Test name
Test status
Simulation time 3538309976 ps
CPU time 5.69 seconds
Started Jul 22 05:46:33 PM PDT 24
Finished Jul 22 05:46:39 PM PDT 24
Peak memory 213244 kb
Host smart-3ec3fe4a-6059-4d6d-8208-7133fd9eb17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234355141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.234355141
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3982946973
Short name T119
Test name
Test status
Simulation time 38886032 ps
CPU time 0.68 seconds
Started Jul 22 05:46:28 PM PDT 24
Finished Jul 22 05:46:30 PM PDT 24
Peak memory 204740 kb
Host smart-cf55c0d4-3e77-4f3b-abba-68af65d2d42a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982946973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3982946973
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3049848149
Short name T50
Test name
Test status
Simulation time 75183321 ps
CPU time 0.8 seconds
Started Jul 22 05:46:31 PM PDT 24
Finished Jul 22 05:46:32 PM PDT 24
Peak memory 204764 kb
Host smart-ecb61d80-4445-47c2-966a-3f2d2f04ae4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049848149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3049848149
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.742852970
Short name T182
Test name
Test status
Simulation time 57769457 ps
CPU time 0.72 seconds
Started Jul 22 05:46:26 PM PDT 24
Finished Jul 22 05:46:27 PM PDT 24
Peak memory 204772 kb
Host smart-8a26d0d7-2c98-4871-ba86-4cc1a66d1803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742852970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.742852970
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.2923599785
Short name T245
Test name
Test status
Simulation time 2715534844 ps
CPU time 3.17 seconds
Started Jul 22 05:46:30 PM PDT 24
Finished Jul 22 05:46:34 PM PDT 24
Peak memory 204932 kb
Host smart-7c275fa2-9eac-4486-a6b3-22ffcac740b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923599785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2923599785
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1639920821
Short name T232
Test name
Test status
Simulation time 74593224 ps
CPU time 0.69 seconds
Started Jul 22 05:46:33 PM PDT 24
Finished Jul 22 05:46:34 PM PDT 24
Peak memory 204768 kb
Host smart-7ea50993-2c37-4d13-a9af-354e46b124ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639920821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1639920821
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1498526562
Short name T136
Test name
Test status
Simulation time 3814013480 ps
CPU time 6.8 seconds
Started Jul 22 05:48:00 PM PDT 24
Finished Jul 22 05:48:07 PM PDT 24
Peak memory 213080 kb
Host smart-bb8c2e04-6bd2-47bd-b662-4538890b290a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498526562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1498526562
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.48978943
Short name T193
Test name
Test status
Simulation time 102738530 ps
CPU time 0.99 seconds
Started Jul 22 05:46:32 PM PDT 24
Finished Jul 22 05:46:34 PM PDT 24
Peak memory 204772 kb
Host smart-565100f6-dcf1-4ac5-bc17-5069b219cb10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48978943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.48978943
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3101739195
Short name T173
Test name
Test status
Simulation time 85079311 ps
CPU time 0.77 seconds
Started Jul 22 05:46:29 PM PDT 24
Finished Jul 22 05:46:30 PM PDT 24
Peak memory 204752 kb
Host smart-95e71ddb-a044-48b7-9ca0-be13ea26d89e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101739195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3101739195
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1304826035
Short name T190
Test name
Test status
Simulation time 50905243 ps
CPU time 0.72 seconds
Started Jul 22 05:46:30 PM PDT 24
Finished Jul 22 05:46:32 PM PDT 24
Peak memory 204780 kb
Host smart-0330bc60-3cca-410a-9c3a-8549a98f7b47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304826035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1304826035
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.2448126289
Short name T139
Test name
Test status
Simulation time 4837076631 ps
CPU time 12.6 seconds
Started Jul 22 05:46:28 PM PDT 24
Finished Jul 22 05:46:41 PM PDT 24
Peak memory 213208 kb
Host smart-60b84597-3a27-4b4a-8a75-5d3e5d6cbeea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448126289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2448126289
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.202988566
Short name T198
Test name
Test status
Simulation time 64375444 ps
CPU time 0.74 seconds
Started Jul 22 05:46:30 PM PDT 24
Finished Jul 22 05:46:31 PM PDT 24
Peak memory 204780 kb
Host smart-92414158-7dc3-400d-9470-4bb27ffedb97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202988566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.202988566
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3517059892
Short name T180
Test name
Test status
Simulation time 50207402 ps
CPU time 0.71 seconds
Started Jul 22 05:45:59 PM PDT 24
Finished Jul 22 05:46:00 PM PDT 24
Peak memory 204644 kb
Host smart-553c141e-30c9-4af0-89ad-510d419a55d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517059892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3517059892
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3313809505
Short name T272
Test name
Test status
Simulation time 5527121019 ps
CPU time 5.01 seconds
Started Jul 22 05:45:59 PM PDT 24
Finished Jul 22 05:46:05 PM PDT 24
Peak memory 205260 kb
Host smart-f9c901ef-2c36-46d3-afb8-e7b1366f79f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313809505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3313809505
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.4194322752
Short name T230
Test name
Test status
Simulation time 5492973925 ps
CPU time 13.83 seconds
Started Jul 22 05:46:00 PM PDT 24
Finished Jul 22 05:46:14 PM PDT 24
Peak memory 213472 kb
Host smart-90360af4-fc59-463c-94ee-4b4221d85ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194322752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.4194322752
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.616863706
Short name T41
Test name
Test status
Simulation time 1896404079 ps
CPU time 4.75 seconds
Started Jul 22 05:46:01 PM PDT 24
Finished Jul 22 05:46:06 PM PDT 24
Peak memory 205112 kb
Host smart-1f47ac14-8f2c-469f-96c1-d9cc52959b1e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616863706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.616863706
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2682792506
Short name T258
Test name
Test status
Simulation time 4303080291 ps
CPU time 9.12 seconds
Started Jul 22 05:45:58 PM PDT 24
Finished Jul 22 05:46:08 PM PDT 24
Peak memory 213456 kb
Host smart-ef499e5b-0bd5-4248-b53b-42b8b2dc32ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682792506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2682792506
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.161203099
Short name T164
Test name
Test status
Simulation time 69411870 ps
CPU time 0.71 seconds
Started Jul 22 05:46:03 PM PDT 24
Finished Jul 22 05:46:04 PM PDT 24
Peak memory 204904 kb
Host smart-6094bac2-ef94-4aa2-b77d-c718bc5660c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161203099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.161203099
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1540386302
Short name T210
Test name
Test status
Simulation time 3246920407 ps
CPU time 9.34 seconds
Started Jul 22 05:45:59 PM PDT 24
Finished Jul 22 05:46:09 PM PDT 24
Peak memory 213404 kb
Host smart-2c636d3e-d1a2-4b5a-9470-bc924be3ef43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540386302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1540386302
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.166323688
Short name T199
Test name
Test status
Simulation time 2888608134 ps
CPU time 8.58 seconds
Started Jul 22 05:46:00 PM PDT 24
Finished Jul 22 05:46:10 PM PDT 24
Peak memory 221548 kb
Host smart-1e9b3160-80e3-45f3-af70-0583794d6209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166323688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.166323688
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3011832449
Short name T240
Test name
Test status
Simulation time 3254433675 ps
CPU time 3.09 seconds
Started Jul 22 05:46:00 PM PDT 24
Finished Jul 22 05:46:04 PM PDT 24
Peak memory 213604 kb
Host smart-07868bb9-c653-43a8-a005-efdf2b2845cf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3011832449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3011832449
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1659403790
Short name T213
Test name
Test status
Simulation time 1119118477 ps
CPU time 1.37 seconds
Started Jul 22 05:48:38 PM PDT 24
Finished Jul 22 05:48:40 PM PDT 24
Peak memory 213140 kb
Host smart-d04379c9-812c-4cdc-9105-1499f2e21869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659403790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1659403790
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.3208797098
Short name T125
Test name
Test status
Simulation time 3919333766 ps
CPU time 8.33 seconds
Started Jul 22 05:46:00 PM PDT 24
Finished Jul 22 05:46:09 PM PDT 24
Peak memory 213228 kb
Host smart-83192e1f-1276-4624-b134-ffa0be5c3dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208797098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3208797098
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.505602439
Short name T239
Test name
Test status
Simulation time 42234729 ps
CPU time 0.76 seconds
Started Jul 22 05:46:00 PM PDT 24
Finished Jul 22 05:46:02 PM PDT 24
Peak memory 204728 kb
Host smart-25e2c83c-6925-458f-b10f-7838d9bf79de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505602439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.505602439
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1222817104
Short name T266
Test name
Test status
Simulation time 5658368040 ps
CPU time 13.98 seconds
Started Jul 22 05:46:01 PM PDT 24
Finished Jul 22 05:46:16 PM PDT 24
Peak memory 213436 kb
Host smart-18fc2a6b-9dc9-4627-a288-3cecbcb15d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222817104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1222817104
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.883431274
Short name T226
Test name
Test status
Simulation time 5297214773 ps
CPU time 2.89 seconds
Started Jul 22 05:46:07 PM PDT 24
Finished Jul 22 05:46:11 PM PDT 24
Peak memory 213472 kb
Host smart-28294862-bb90-4afa-8938-66a73c797296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883431274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.883431274
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2145120262
Short name T51
Test name
Test status
Simulation time 3548200621 ps
CPU time 3.86 seconds
Started Jul 22 05:45:59 PM PDT 24
Finished Jul 22 05:46:04 PM PDT 24
Peak memory 205192 kb
Host smart-f4c4ad34-95e6-4051-897b-7f6eabb4c0e5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145120262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2145120262
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2133902501
Short name T269
Test name
Test status
Simulation time 715955588 ps
CPU time 1.98 seconds
Started Jul 22 05:46:01 PM PDT 24
Finished Jul 22 05:46:04 PM PDT 24
Peak memory 205192 kb
Host smart-ccddcd4f-1177-4a93-926b-3ea4ac665cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133902501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2133902501
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.682187233
Short name T140
Test name
Test status
Simulation time 2590911954 ps
CPU time 4.35 seconds
Started Jul 22 05:46:00 PM PDT 24
Finished Jul 22 05:46:05 PM PDT 24
Peak memory 204952 kb
Host smart-7fb80dc1-c301-4227-8289-f5b19a763cc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682187233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.682187233
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2177073046
Short name T192
Test name
Test status
Simulation time 62457080 ps
CPU time 0.72 seconds
Started Jul 22 05:45:59 PM PDT 24
Finished Jul 22 05:46:00 PM PDT 24
Peak memory 204748 kb
Host smart-bdbda5f6-71d2-4a0c-8182-2c40da7e91d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177073046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2177073046
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.341734143
Short name T166
Test name
Test status
Simulation time 15571524685 ps
CPU time 12.64 seconds
Started Jul 22 05:45:58 PM PDT 24
Finished Jul 22 05:46:11 PM PDT 24
Peak memory 213392 kb
Host smart-b91a1585-91b3-4ce4-b08f-edc40bd9ac89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341734143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.341734143
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2143600142
Short name T254
Test name
Test status
Simulation time 2072322004 ps
CPU time 3.81 seconds
Started Jul 22 05:46:00 PM PDT 24
Finished Jul 22 05:46:05 PM PDT 24
Peak memory 213308 kb
Host smart-9010446c-e29c-4a92-b03f-3177b69a7114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143600142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2143600142
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1410059239
Short name T229
Test name
Test status
Simulation time 11358551040 ps
CPU time 30.38 seconds
Started Jul 22 05:46:00 PM PDT 24
Finished Jul 22 05:46:31 PM PDT 24
Peak memory 213368 kb
Host smart-b61fb046-10f7-4cb9-8b04-ab2605704d09
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1410059239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.1410059239
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1541097976
Short name T130
Test name
Test status
Simulation time 1480666700 ps
CPU time 1.08 seconds
Started Jul 22 05:46:00 PM PDT 24
Finished Jul 22 05:46:01 PM PDT 24
Peak memory 205072 kb
Host smart-0ed99310-3fd2-4fdf-942e-55f710999654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541097976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1541097976
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3064685143
Short name T3
Test name
Test status
Simulation time 79598600 ps
CPU time 0.85 seconds
Started Jul 22 05:46:08 PM PDT 24
Finished Jul 22 05:46:10 PM PDT 24
Peak memory 204776 kb
Host smart-63b3faa8-b800-402c-87b4-425dfbfd53a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064685143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3064685143
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1372742352
Short name T225
Test name
Test status
Simulation time 13490520686 ps
CPU time 8.71 seconds
Started Jul 22 05:47:10 PM PDT 24
Finished Jul 22 05:47:19 PM PDT 24
Peak memory 213292 kb
Host smart-fc308c5e-4b8a-4186-addc-d61a9ad269c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372742352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1372742352
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2127660529
Short name T178
Test name
Test status
Simulation time 1090867117 ps
CPU time 1.96 seconds
Started Jul 22 05:46:08 PM PDT 24
Finished Jul 22 05:46:11 PM PDT 24
Peak memory 205180 kb
Host smart-df8aee45-19b1-4090-acef-09abc8d1f0c8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2127660529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2127660529
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1514841614
Short name T256
Test name
Test status
Simulation time 3960309183 ps
CPU time 7.01 seconds
Started Jul 22 05:46:01 PM PDT 24
Finished Jul 22 05:46:09 PM PDT 24
Peak memory 205192 kb
Host smart-6e75888f-41be-4653-a28c-6e4a1a9fb3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514841614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1514841614
Directory /workspace/9.rv_dm_sba_tl_access/latest
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