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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.96 95.77 81.52 89.91 75.00 86.50 98.42 53.62


Total test records in report: 437
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T303 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1739889363 Jul 24 05:00:20 PM PDT 24 Jul 24 05:00:21 PM PDT 24 486171171 ps
T304 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3025656096 Jul 24 05:00:35 PM PDT 24 Jul 24 05:00:36 PM PDT 24 168283341 ps
T305 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1129809508 Jul 24 05:00:24 PM PDT 24 Jul 24 05:00:47 PM PDT 24 8055103147 ps
T95 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3448345566 Jul 24 05:00:35 PM PDT 24 Jul 24 05:00:42 PM PDT 24 602938135 ps
T96 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1125204766 Jul 24 05:00:24 PM PDT 24 Jul 24 05:00:32 PM PDT 24 3642369347 ps
T82 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3350135786 Jul 24 05:00:27 PM PDT 24 Jul 24 05:00:30 PM PDT 24 353212952 ps
T306 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2185278719 Jul 24 05:00:23 PM PDT 24 Jul 24 05:00:24 PM PDT 24 252620824 ps
T83 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.14647865 Jul 24 05:00:23 PM PDT 24 Jul 24 05:00:25 PM PDT 24 58297463 ps
T84 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3716816187 Jul 24 05:00:28 PM PDT 24 Jul 24 05:01:11 PM PDT 24 41857369171 ps
T85 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.158963468 Jul 24 05:00:39 PM PDT 24 Jul 24 05:00:49 PM PDT 24 614715969 ps
T307 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3536680369 Jul 24 05:00:10 PM PDT 24 Jul 24 05:00:17 PM PDT 24 157328092 ps
T86 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2885634120 Jul 24 05:00:48 PM PDT 24 Jul 24 05:00:51 PM PDT 24 126158423 ps
T104 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.976098591 Jul 24 05:00:24 PM PDT 24 Jul 24 05:00:26 PM PDT 24 195011784 ps
T308 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2150632143 Jul 24 05:00:10 PM PDT 24 Jul 24 05:01:46 PM PDT 24 118218034988 ps
T309 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1614038780 Jul 24 05:00:20 PM PDT 24 Jul 24 05:00:29 PM PDT 24 10586162754 ps
T310 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.522062293 Jul 24 05:00:21 PM PDT 24 Jul 24 05:00:28 PM PDT 24 11587330680 ps
T105 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.4163331297 Jul 24 05:00:17 PM PDT 24 Jul 24 05:00:20 PM PDT 24 108994869 ps
T97 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2281097293 Jul 24 05:00:56 PM PDT 24 Jul 24 05:00:58 PM PDT 24 101872766 ps
T152 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.166026862 Jul 24 05:00:45 PM PDT 24 Jul 24 05:01:00 PM PDT 24 3145190330 ps
T106 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.415474082 Jul 24 05:00:22 PM PDT 24 Jul 24 05:01:44 PM PDT 24 16672463398 ps
T107 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1369947091 Jul 24 05:00:35 PM PDT 24 Jul 24 05:00:36 PM PDT 24 61053916 ps
T311 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1760579366 Jul 24 05:00:14 PM PDT 24 Jul 24 05:00:18 PM PDT 24 268562240 ps
T125 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.501152381 Jul 24 05:00:32 PM PDT 24 Jul 24 05:00:36 PM PDT 24 261833201 ps
T312 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1209575223 Jul 24 05:00:06 PM PDT 24 Jul 24 05:00:16 PM PDT 24 48856725 ps
T313 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3499465806 Jul 24 05:00:27 PM PDT 24 Jul 24 05:00:29 PM PDT 24 226684496 ps
T108 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.428202012 Jul 24 05:00:16 PM PDT 24 Jul 24 05:00:19 PM PDT 24 47718148 ps
T130 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3087727149 Jul 24 05:00:46 PM PDT 24 Jul 24 05:00:57 PM PDT 24 2986785955 ps
T314 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.137445301 Jul 24 05:00:25 PM PDT 24 Jul 24 05:00:28 PM PDT 24 892333174 ps
T315 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2281883423 Jul 24 05:00:39 PM PDT 24 Jul 24 05:00:44 PM PDT 24 276401638 ps
T316 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3259669426 Jul 24 05:00:27 PM PDT 24 Jul 24 05:01:27 PM PDT 24 23453191634 ps
T317 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.232801285 Jul 24 05:00:26 PM PDT 24 Jul 24 05:00:29 PM PDT 24 781354925 ps
T318 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2937248636 Jul 24 05:00:34 PM PDT 24 Jul 24 05:00:37 PM PDT 24 309947775 ps
T319 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1769231570 Jul 24 05:00:26 PM PDT 24 Jul 24 05:00:42 PM PDT 24 8750883476 ps
T162 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1929168779 Jul 24 05:00:07 PM PDT 24 Jul 24 05:01:06 PM PDT 24 26687927902 ps
T320 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2849534591 Jul 24 05:00:30 PM PDT 24 Jul 24 05:00:31 PM PDT 24 82518578 ps
T321 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2094736236 Jul 24 05:00:09 PM PDT 24 Jul 24 05:00:17 PM PDT 24 112168957 ps
T150 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1378377938 Jul 24 05:00:21 PM PDT 24 Jul 24 05:00:37 PM PDT 24 2009945871 ps
T109 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1791564194 Jul 24 05:00:16 PM PDT 24 Jul 24 05:01:28 PM PDT 24 20464134746 ps
T99 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3566765863 Jul 24 05:00:30 PM PDT 24 Jul 24 05:00:41 PM PDT 24 6010361358 ps
T322 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2944404838 Jul 24 05:00:41 PM PDT 24 Jul 24 05:00:44 PM PDT 24 150301896 ps
T323 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3768878459 Jul 24 05:00:15 PM PDT 24 Jul 24 05:00:28 PM PDT 24 3650385011 ps
T116 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.877464959 Jul 24 05:00:02 PM PDT 24 Jul 24 05:00:18 PM PDT 24 124133185 ps
T324 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.98557461 Jul 24 05:00:33 PM PDT 24 Jul 24 05:00:44 PM PDT 24 4124412693 ps
T126 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.813802808 Jul 24 05:00:19 PM PDT 24 Jul 24 05:00:26 PM PDT 24 870425527 ps
T325 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2678315378 Jul 24 05:00:11 PM PDT 24 Jul 24 05:00:36 PM PDT 24 27879206407 ps
T326 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3442472854 Jul 24 05:00:36 PM PDT 24 Jul 24 05:00:40 PM PDT 24 700499419 ps
T327 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3595329328 Jul 24 05:00:34 PM PDT 24 Jul 24 05:00:43 PM PDT 24 6005884656 ps
T328 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3949016261 Jul 24 05:00:24 PM PDT 24 Jul 24 05:00:46 PM PDT 24 25436821909 ps
T329 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1439350717 Jul 24 05:00:18 PM PDT 24 Jul 24 05:00:25 PM PDT 24 9035703234 ps
T330 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.71848125 Jul 24 05:00:22 PM PDT 24 Jul 24 05:00:27 PM PDT 24 305369809 ps
T331 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3162914220 Jul 24 05:00:34 PM PDT 24 Jul 24 05:03:21 PM PDT 24 35880769623 ps
T160 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1594076334 Jul 24 05:00:17 PM PDT 24 Jul 24 05:00:39 PM PDT 24 2731632367 ps
T332 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.293306455 Jul 24 05:00:33 PM PDT 24 Jul 24 05:00:36 PM PDT 24 357469299 ps
T110 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.747854607 Jul 24 05:00:13 PM PDT 24 Jul 24 05:00:23 PM PDT 24 404499422 ps
T100 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4282971785 Jul 24 05:00:17 PM PDT 24 Jul 24 05:00:30 PM PDT 24 4839780655 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.135675630 Jul 24 05:00:14 PM PDT 24 Jul 24 05:00:18 PM PDT 24 265282718 ps
T334 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4053647401 Jul 24 05:00:19 PM PDT 24 Jul 24 05:00:20 PM PDT 24 1061027272 ps
T335 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1829554824 Jul 24 05:00:07 PM PDT 24 Jul 24 05:00:21 PM PDT 24 2766483677 ps
T336 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.175400452 Jul 24 05:00:22 PM PDT 24 Jul 24 05:00:24 PM PDT 24 476874587 ps
T337 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.814006399 Jul 24 05:00:21 PM PDT 24 Jul 24 05:00:24 PM PDT 24 323007622 ps
T117 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2692084883 Jul 24 05:00:04 PM PDT 24 Jul 24 05:00:17 PM PDT 24 572549828 ps
T338 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1697533353 Jul 24 05:00:19 PM PDT 24 Jul 24 05:00:20 PM PDT 24 231827111 ps
T339 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2082709371 Jul 24 05:00:25 PM PDT 24 Jul 24 05:00:28 PM PDT 24 2074138282 ps
T340 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3854951459 Jul 24 05:00:41 PM PDT 24 Jul 24 05:00:43 PM PDT 24 133701675 ps
T341 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3005087135 Jul 24 05:00:44 PM PDT 24 Jul 24 05:00:48 PM PDT 24 245190817 ps
T342 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.82377392 Jul 24 05:00:38 PM PDT 24 Jul 24 05:00:42 PM PDT 24 595270390 ps
T153 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2146326365 Jul 24 05:00:36 PM PDT 24 Jul 24 05:00:49 PM PDT 24 3804681071 ps
T118 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3022708139 Jul 24 05:00:23 PM PDT 24 Jul 24 05:00:26 PM PDT 24 274580340 ps
T343 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.246978885 Jul 24 05:00:20 PM PDT 24 Jul 24 05:00:21 PM PDT 24 117760874 ps
T344 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2428289543 Jul 24 05:00:38 PM PDT 24 Jul 24 05:00:44 PM PDT 24 3580860571 ps
T345 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.4087808493 Jul 24 05:00:38 PM PDT 24 Jul 24 05:02:03 PM PDT 24 62880031087 ps
T346 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3833726645 Jul 24 05:00:19 PM PDT 24 Jul 24 05:00:26 PM PDT 24 9290138791 ps
T347 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3993689242 Jul 24 05:00:19 PM PDT 24 Jul 24 05:00:52 PM PDT 24 4998700139 ps
T348 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2254400699 Jul 24 05:00:22 PM PDT 24 Jul 24 05:00:23 PM PDT 24 334713193 ps
T349 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1785708949 Jul 24 05:00:34 PM PDT 24 Jul 24 05:01:15 PM PDT 24 69144282661 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.382461501 Jul 24 05:00:05 PM PDT 24 Jul 24 05:00:17 PM PDT 24 219272941 ps
T351 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.893294781 Jul 24 05:00:25 PM PDT 24 Jul 24 05:01:58 PM PDT 24 59297805034 ps
T352 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1047229209 Jul 24 05:00:37 PM PDT 24 Jul 24 05:00:40 PM PDT 24 922636891 ps
T119 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3493851523 Jul 24 05:00:45 PM PDT 24 Jul 24 05:00:47 PM PDT 24 423637656 ps
T353 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3065541209 Jul 24 05:00:24 PM PDT 24 Jul 24 05:00:25 PM PDT 24 142265239 ps
T354 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4188570740 Jul 24 05:00:20 PM PDT 24 Jul 24 05:00:27 PM PDT 24 15361949729 ps
T161 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1430428288 Jul 24 05:00:43 PM PDT 24 Jul 24 05:00:53 PM PDT 24 1244099808 ps
T121 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2345877439 Jul 24 05:00:25 PM PDT 24 Jul 24 05:00:27 PM PDT 24 102244345 ps
T355 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.50112396 Jul 24 05:00:26 PM PDT 24 Jul 24 05:00:29 PM PDT 24 207045090 ps
T356 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.753651879 Jul 24 05:00:37 PM PDT 24 Jul 24 05:00:39 PM PDT 24 761510185 ps
T357 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1704137718 Jul 24 05:00:27 PM PDT 24 Jul 24 05:00:36 PM PDT 24 6989405399 ps
T358 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1689367543 Jul 24 05:00:38 PM PDT 24 Jul 24 05:00:41 PM PDT 24 177211553 ps
T101 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.31212108 Jul 24 05:00:26 PM PDT 24 Jul 24 05:00:31 PM PDT 24 4260847874 ps
T359 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.809415543 Jul 24 05:00:20 PM PDT 24 Jul 24 05:00:26 PM PDT 24 4237077389 ps
T360 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3939115924 Jul 24 05:00:46 PM PDT 24 Jul 24 05:00:47 PM PDT 24 91899555 ps
T361 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3121906176 Jul 24 05:00:43 PM PDT 24 Jul 24 05:00:46 PM PDT 24 220903626 ps
T362 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.755653394 Jul 24 05:00:17 PM PDT 24 Jul 24 05:00:34 PM PDT 24 6673683995 ps
T363 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2721787652 Jul 24 05:00:12 PM PDT 24 Jul 24 05:00:20 PM PDT 24 880404905 ps
T364 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1456047366 Jul 24 05:00:20 PM PDT 24 Jul 24 05:01:51 PM PDT 24 64333042448 ps
T127 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.140566875 Jul 24 05:00:29 PM PDT 24 Jul 24 05:00:33 PM PDT 24 536877771 ps
T365 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3798440063 Jul 24 05:00:22 PM PDT 24 Jul 24 05:01:52 PM PDT 24 28648999392 ps
T366 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1066450391 Jul 24 05:00:23 PM PDT 24 Jul 24 05:00:29 PM PDT 24 297555483 ps
T102 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3730961736 Jul 24 05:00:17 PM PDT 24 Jul 24 05:00:20 PM PDT 24 2299137849 ps
T367 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3083364499 Jul 24 05:00:43 PM PDT 24 Jul 24 05:00:47 PM PDT 24 98838561 ps
T122 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2759838370 Jul 24 05:00:13 PM PDT 24 Jul 24 05:01:26 PM PDT 24 2338370106 ps
T368 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2500061322 Jul 24 05:00:36 PM PDT 24 Jul 24 05:00:50 PM PDT 24 14185235714 ps
T369 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.753302953 Jul 24 05:00:38 PM PDT 24 Jul 24 05:00:42 PM PDT 24 2619435662 ps
T370 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.340359526 Jul 24 05:00:11 PM PDT 24 Jul 24 05:00:17 PM PDT 24 414027610 ps
T371 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.19062481 Jul 24 05:00:11 PM PDT 24 Jul 24 05:00:17 PM PDT 24 152684281 ps
T372 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1609893148 Jul 24 05:00:15 PM PDT 24 Jul 24 05:00:50 PM PDT 24 2573703246 ps
T373 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3871703899 Jul 24 05:00:42 PM PDT 24 Jul 24 05:00:49 PM PDT 24 161735999 ps
T374 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3310935808 Jul 24 05:00:31 PM PDT 24 Jul 24 05:00:52 PM PDT 24 23999856379 ps
T375 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1539721282 Jul 24 05:00:25 PM PDT 24 Jul 24 05:00:28 PM PDT 24 219445493 ps
T376 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.691479057 Jul 24 05:00:33 PM PDT 24 Jul 24 05:00:35 PM PDT 24 63099035 ps
T377 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2071468963 Jul 24 05:00:25 PM PDT 24 Jul 24 05:00:26 PM PDT 24 880507412 ps
T378 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3431651285 Jul 24 05:00:36 PM PDT 24 Jul 24 05:00:39 PM PDT 24 327743524 ps
T379 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3035793245 Jul 24 05:00:38 PM PDT 24 Jul 24 05:00:41 PM PDT 24 4908764772 ps
T380 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.453029246 Jul 24 05:00:22 PM PDT 24 Jul 24 05:00:31 PM PDT 24 2896724337 ps
T381 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2270120484 Jul 24 05:00:45 PM PDT 24 Jul 24 05:00:51 PM PDT 24 221187163 ps
T382 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3576716182 Jul 24 05:00:42 PM PDT 24 Jul 24 05:00:47 PM PDT 24 183155585 ps
T383 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2648005322 Jul 24 05:00:33 PM PDT 24 Jul 24 05:00:35 PM PDT 24 1031105770 ps
T384 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2349033657 Jul 24 05:00:26 PM PDT 24 Jul 24 05:00:30 PM PDT 24 201341176 ps
T385 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3188309260 Jul 24 05:00:33 PM PDT 24 Jul 24 05:00:48 PM PDT 24 4504640701 ps
T386 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3039104912 Jul 24 05:00:21 PM PDT 24 Jul 24 05:00:26 PM PDT 24 659952255 ps
T387 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2836574522 Jul 24 05:00:26 PM PDT 24 Jul 24 05:00:33 PM PDT 24 11104037736 ps
T388 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1702569623 Jul 24 05:00:33 PM PDT 24 Jul 24 05:00:36 PM PDT 24 729412001 ps
T389 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2814349095 Jul 24 05:00:35 PM PDT 24 Jul 24 05:00:40 PM PDT 24 1656568167 ps
T390 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2709994099 Jul 24 05:00:19 PM PDT 24 Jul 24 05:00:24 PM PDT 24 181957018 ps
T391 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2635338953 Jul 24 05:00:26 PM PDT 24 Jul 24 05:00:27 PM PDT 24 136516332 ps
T111 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3978700708 Jul 24 05:00:30 PM PDT 24 Jul 24 05:00:37 PM PDT 24 1744650918 ps
T392 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.318514425 Jul 24 05:00:24 PM PDT 24 Jul 24 05:00:27 PM PDT 24 192149976 ps
T393 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3027294909 Jul 24 05:00:22 PM PDT 24 Jul 24 05:00:31 PM PDT 24 12409276503 ps
T394 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3552897477 Jul 24 05:00:38 PM PDT 24 Jul 24 05:00:39 PM PDT 24 99100044 ps
T156 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2533391296 Jul 24 05:00:40 PM PDT 24 Jul 24 05:00:52 PM PDT 24 1108449514 ps
T123 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1031100640 Jul 24 05:00:16 PM PDT 24 Jul 24 05:01:34 PM PDT 24 3484681964 ps
T395 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2045483532 Jul 24 05:00:23 PM PDT 24 Jul 24 05:00:25 PM PDT 24 457056490 ps
T396 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3797547020 Jul 24 05:00:24 PM PDT 24 Jul 24 05:00:27 PM PDT 24 308598642 ps
T397 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3394106070 Jul 24 05:00:44 PM PDT 24 Jul 24 05:00:46 PM PDT 24 224830903 ps
T398 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3646597637 Jul 24 05:00:40 PM PDT 24 Jul 24 05:01:06 PM PDT 24 4519409503 ps
T399 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.791600463 Jul 24 05:00:07 PM PDT 24 Jul 24 05:00:22 PM PDT 24 5388040285 ps
T400 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4071575884 Jul 24 05:00:28 PM PDT 24 Jul 24 05:00:31 PM PDT 24 4306314601 ps
T401 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3076312878 Jul 24 05:00:25 PM PDT 24 Jul 24 05:00:27 PM PDT 24 300453341 ps
T402 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3570648905 Jul 24 05:00:35 PM PDT 24 Jul 24 05:00:43 PM PDT 24 1420150233 ps
T103 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2801329576 Jul 24 05:00:31 PM PDT 24 Jul 24 05:00:45 PM PDT 24 9113575599 ps
T403 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.4123692194 Jul 24 05:00:40 PM PDT 24 Jul 24 05:00:41 PM PDT 24 81125614 ps
T154 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.720014997 Jul 24 05:00:26 PM PDT 24 Jul 24 05:00:35 PM PDT 24 1761422336 ps
T112 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.149992538 Jul 24 05:00:25 PM PDT 24 Jul 24 05:00:32 PM PDT 24 804048070 ps
T404 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2311723957 Jul 24 05:00:38 PM PDT 24 Jul 24 05:00:40 PM PDT 24 244600373 ps
T113 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2695077198 Jul 24 05:00:24 PM PDT 24 Jul 24 05:00:31 PM PDT 24 420876013 ps
T405 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.54762914 Jul 24 05:00:29 PM PDT 24 Jul 24 05:00:32 PM PDT 24 96086242 ps
T159 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3362828467 Jul 24 05:00:41 PM PDT 24 Jul 24 05:00:51 PM PDT 24 1250036199 ps
T406 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4234411043 Jul 24 05:00:21 PM PDT 24 Jul 24 05:00:33 PM PDT 24 1629142905 ps
T155 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2628397819 Jul 24 05:00:19 PM PDT 24 Jul 24 05:00:40 PM PDT 24 4902867518 ps
T407 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.618537986 Jul 24 05:00:23 PM PDT 24 Jul 24 05:00:26 PM PDT 24 328965819 ps
T408 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3891057432 Jul 24 05:00:01 PM PDT 24 Jul 24 05:00:18 PM PDT 24 148950848 ps
T409 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1045747182 Jul 24 05:00:38 PM PDT 24 Jul 24 05:00:43 PM PDT 24 111948384 ps
T114 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1224023608 Jul 24 05:00:22 PM PDT 24 Jul 24 05:00:25 PM PDT 24 311991945 ps
T410 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.119216599 Jul 24 05:00:39 PM PDT 24 Jul 24 05:00:44 PM PDT 24 609526523 ps
T411 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1135403078 Jul 24 05:00:25 PM PDT 24 Jul 24 05:00:28 PM PDT 24 148631657 ps
T412 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1284060741 Jul 24 05:00:37 PM PDT 24 Jul 24 05:00:38 PM PDT 24 175657593 ps
T413 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2002061451 Jul 24 05:00:34 PM PDT 24 Jul 24 05:00:37 PM PDT 24 544829342 ps
T124 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2886879237 Jul 24 05:00:28 PM PDT 24 Jul 24 05:00:30 PM PDT 24 80396760 ps
T414 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.765618260 Jul 24 05:00:23 PM PDT 24 Jul 24 05:01:02 PM PDT 24 12121417345 ps
T415 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1642516683 Jul 24 05:00:26 PM PDT 24 Jul 24 05:00:51 PM PDT 24 35975391405 ps
T115 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1501846381 Jul 24 05:00:44 PM PDT 24 Jul 24 05:00:53 PM PDT 24 5087292805 ps
T416 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.968591287 Jul 24 05:00:12 PM PDT 24 Jul 24 05:00:18 PM PDT 24 222794158 ps
T417 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3178685376 Jul 24 05:00:23 PM PDT 24 Jul 24 05:00:25 PM PDT 24 279487372 ps
T418 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3644702356 Jul 24 05:00:24 PM PDT 24 Jul 24 05:00:26 PM PDT 24 178610982 ps
T419 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.466815224 Jul 24 05:00:21 PM PDT 24 Jul 24 05:00:48 PM PDT 24 2865349491 ps
T420 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1716320717 Jul 24 05:00:33 PM PDT 24 Jul 24 05:00:35 PM PDT 24 146289425 ps
T421 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.190382339 Jul 24 05:00:27 PM PDT 24 Jul 24 05:00:46 PM PDT 24 31874143113 ps
T120 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1052549267 Jul 24 04:59:53 PM PDT 24 Jul 24 05:01:10 PM PDT 24 7173162802 ps
T422 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1163013402 Jul 24 05:00:26 PM PDT 24 Jul 24 05:00:27 PM PDT 24 68962723 ps
T423 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2027480039 Jul 24 05:00:35 PM PDT 24 Jul 24 05:00:37 PM PDT 24 461209805 ps
T424 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3268951285 Jul 24 05:00:25 PM PDT 24 Jul 24 05:00:28 PM PDT 24 219208205 ps
T425 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.954752197 Jul 24 05:00:24 PM PDT 24 Jul 24 05:00:25 PM PDT 24 123211432 ps
T151 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1921382407 Jul 24 05:00:36 PM PDT 24 Jul 24 05:01:02 PM PDT 24 11225468729 ps
T426 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1594031914 Jul 24 05:00:17 PM PDT 24 Jul 24 05:00:19 PM PDT 24 309423695 ps
T427 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1277045277 Jul 24 05:00:40 PM PDT 24 Jul 24 05:00:43 PM PDT 24 923599427 ps
T428 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.88573981 Jul 24 05:00:19 PM PDT 24 Jul 24 05:00:22 PM PDT 24 173414868 ps
T429 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3066045003 Jul 24 05:00:41 PM PDT 24 Jul 24 05:00:53 PM PDT 24 14306713026 ps
T430 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.334169270 Jul 24 05:00:21 PM PDT 24 Jul 24 05:00:28 PM PDT 24 2251696209 ps
T431 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3573530998 Jul 24 05:00:23 PM PDT 24 Jul 24 05:00:26 PM PDT 24 266265690 ps
T432 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4232609040 Jul 24 05:00:32 PM PDT 24 Jul 24 05:00:36 PM PDT 24 238423674 ps
T433 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.620148986 Jul 24 05:00:52 PM PDT 24 Jul 24 05:01:10 PM PDT 24 6007557539 ps
T434 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2265887808 Jul 24 05:00:39 PM PDT 24 Jul 24 05:00:41 PM PDT 24 98454386 ps
T435 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3717871035 Jul 24 05:00:22 PM PDT 24 Jul 24 05:00:26 PM PDT 24 226104182 ps
T436 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1295627951 Jul 24 05:00:05 PM PDT 24 Jul 24 05:00:17 PM PDT 24 180482870 ps
T437 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3177363728 Jul 24 05:00:25 PM PDT 24 Jul 24 05:00:42 PM PDT 24 2286592492 ps
T157 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2513297947 Jul 24 05:00:17 PM PDT 24 Jul 24 05:00:27 PM PDT 24 885300521 ps
T158 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.808669818 Jul 24 05:00:23 PM PDT 24 Jul 24 05:00:40 PM PDT 24 3548147776 ps
T55 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1412723773 Jul 24 05:00:43 PM PDT 24 Jul 24 05:01:07 PM PDT 24 70047100622 ps

Test location /workspace/coverage/default/25.rv_dm_stress_all.855915975
Short name T3
Test name
Test status
Simulation time 1935449399 ps
CPU time 6.15 seconds
Started Jul 24 05:04:09 PM PDT 24
Finished Jul 24 05:04:15 PM PDT 24
Peak memory 204980 kb
Host smart-bdd10bc6-9657-4546-beb9-2ccc3df41bbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855915975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.855915975
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3693611828
Short name T30
Test name
Test status
Simulation time 7963432043 ps
CPU time 20.71 seconds
Started Jul 24 05:04:33 PM PDT 24
Finished Jul 24 05:04:54 PM PDT 24
Peak memory 213464 kb
Host smart-e6ba993c-0561-4b6f-a8aa-217322ffbde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693611828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3693611828
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2978507100
Short name T63
Test name
Test status
Simulation time 22180120084 ps
CPU time 77.6 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:01:43 PM PDT 24
Peak memory 221472 kb
Host smart-163efb95-b645-4a5f-94f5-4e74ecc886ce
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978507100 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2978507100
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.3093329399
Short name T4
Test name
Test status
Simulation time 2231057278 ps
CPU time 7.42 seconds
Started Jul 24 05:04:41 PM PDT 24
Finished Jul 24 05:04:49 PM PDT 24
Peak memory 213404 kb
Host smart-36fc502b-4d73-4c19-b109-1bf8bb4d7030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093329399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3093329399
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1600232128
Short name T5
Test name
Test status
Simulation time 4461617399 ps
CPU time 11.53 seconds
Started Jul 24 05:05:38 PM PDT 24
Finished Jul 24 05:05:50 PM PDT 24
Peak memory 204952 kb
Host smart-e2326c82-f17e-4749-be4f-d9ca38f75ccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600232128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1600232128
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1409333602
Short name T49
Test name
Test status
Simulation time 36200384 ps
CPU time 0.77 seconds
Started Jul 24 05:04:18 PM PDT 24
Finished Jul 24 05:04:19 PM PDT 24
Peak memory 204980 kb
Host smart-439c48a8-1a83-4bc9-b3b0-cf1652e4dd3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409333602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1409333602
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3219886591
Short name T61
Test name
Test status
Simulation time 737712354 ps
CPU time 8.94 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:31 PM PDT 24
Peak memory 213196 kb
Host smart-b7bf118b-48e7-446a-b09b-e4e217f11bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219886591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3219886591
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3884426402
Short name T31
Test name
Test status
Simulation time 4219587949 ps
CPU time 11.62 seconds
Started Jul 24 05:04:26 PM PDT 24
Finished Jul 24 05:04:38 PM PDT 24
Peak memory 205244 kb
Host smart-2c1a5cc3-400e-4ed5-abc8-cc845a2e40af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884426402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3884426402
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.415474082
Short name T106
Test name
Test status
Simulation time 16672463398 ps
CPU time 81.55 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:01:44 PM PDT 24
Peak memory 213208 kb
Host smart-20996267-b287-4dd6-ac5d-b6403866e361
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415474082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.415474082
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2887865934
Short name T18
Test name
Test status
Simulation time 970486318 ps
CPU time 3.32 seconds
Started Jul 24 05:04:03 PM PDT 24
Finished Jul 24 05:04:07 PM PDT 24
Peak memory 204896 kb
Host smart-00ebb7b8-425f-403d-a44b-f9de6584ba50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887865934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2887865934
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3211111600
Short name T255
Test name
Test status
Simulation time 28837123741 ps
CPU time 13.56 seconds
Started Jul 24 05:04:59 PM PDT 24
Finished Jul 24 05:05:13 PM PDT 24
Peak memory 205372 kb
Host smart-09e27d3b-ed91-4534-8a7c-31556ea987c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211111600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3211111600
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.2986028918
Short name T75
Test name
Test status
Simulation time 123234666 ps
CPU time 1.08 seconds
Started Jul 24 05:04:09 PM PDT 24
Finished Jul 24 05:04:11 PM PDT 24
Peak memory 215036 kb
Host smart-29f12aea-b7e2-4d4b-a798-b3bd12d44f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986028918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2986028918
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1378377938
Short name T150
Test name
Test status
Simulation time 2009945871 ps
CPU time 15.73 seconds
Started Jul 24 05:00:21 PM PDT 24
Finished Jul 24 05:00:37 PM PDT 24
Peak memory 213032 kb
Host smart-f7c53073-68ab-48ef-b41d-8e3914e81282
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378377938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1378377938
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.1539855401
Short name T14
Test name
Test status
Simulation time 2637558216 ps
CPU time 4.95 seconds
Started Jul 24 05:04:26 PM PDT 24
Finished Jul 24 05:04:31 PM PDT 24
Peak memory 205344 kb
Host smart-1434dbd9-5a03-41b2-8c6f-a59d71854fc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539855401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1539855401
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1436161536
Short name T76
Test name
Test status
Simulation time 4347586151 ps
CPU time 11.8 seconds
Started Jul 24 05:03:59 PM PDT 24
Finished Jul 24 05:04:11 PM PDT 24
Peak memory 205164 kb
Host smart-74aecbc1-a596-4b0f-878f-4dada09b5849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436161536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1436161536
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.307407826
Short name T52
Test name
Test status
Simulation time 1429232081 ps
CPU time 1.86 seconds
Started Jul 24 05:04:35 PM PDT 24
Finished Jul 24 05:04:37 PM PDT 24
Peak memory 229248 kb
Host smart-7ab00283-03f1-47cf-b32b-9d692fd677d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307407826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.307407826
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.2400340947
Short name T10
Test name
Test status
Simulation time 5396324530 ps
CPU time 13.62 seconds
Started Jul 24 05:05:39 PM PDT 24
Finished Jul 24 05:05:53 PM PDT 24
Peak memory 213080 kb
Host smart-9887a89a-d333-49a7-aafb-eda5a4866a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400340947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2400340947
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1796960747
Short name T39
Test name
Test status
Simulation time 112393106 ps
CPU time 0.78 seconds
Started Jul 24 05:04:01 PM PDT 24
Finished Jul 24 05:04:06 PM PDT 24
Peak memory 213148 kb
Host smart-5fdc510a-d601-4b49-af18-24e58cebdc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796960747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1796960747
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1044054649
Short name T1
Test name
Test status
Simulation time 3291766887 ps
CPU time 10.74 seconds
Started Jul 24 05:04:19 PM PDT 24
Finished Jul 24 05:04:30 PM PDT 24
Peak memory 205428 kb
Host smart-f8cccc01-3540-4eaa-970e-ba011c8f9a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044054649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1044054649
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.2997101364
Short name T40
Test name
Test status
Simulation time 99746180 ps
CPU time 0.75 seconds
Started Jul 24 05:04:06 PM PDT 24
Finished Jul 24 05:04:07 PM PDT 24
Peak memory 204860 kb
Host smart-7bfab884-10c6-4adc-8b21-ddcbfd534268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997101364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2997101364
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1412723773
Short name T55
Test name
Test status
Simulation time 70047100622 ps
CPU time 23.73 seconds
Started Jul 24 05:00:43 PM PDT 24
Finished Jul 24 05:01:07 PM PDT 24
Peak memory 223536 kb
Host smart-ed7954f0-74bc-4c85-8fbc-bd87e0bb73cf
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412723773 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1412723773
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.4180859833
Short name T27
Test name
Test status
Simulation time 7368816219 ps
CPU time 5.29 seconds
Started Jul 24 05:04:08 PM PDT 24
Finished Jul 24 05:04:29 PM PDT 24
Peak memory 205456 kb
Host smart-1d59134e-5325-47c1-84d6-6cabca12819f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180859833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.4180859833
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.1398112994
Short name T11
Test name
Test status
Simulation time 8501921993 ps
CPU time 22.62 seconds
Started Jul 24 05:05:27 PM PDT 24
Finished Jul 24 05:05:50 PM PDT 24
Peak memory 213088 kb
Host smart-41af0b64-d904-435a-8d87-1df214c0336b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398112994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.1398112994
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1125204766
Short name T96
Test name
Test status
Simulation time 3642369347 ps
CPU time 8.21 seconds
Started Jul 24 05:00:24 PM PDT 24
Finished Jul 24 05:00:32 PM PDT 24
Peak memory 205112 kb
Host smart-77bb6091-2718-461d-b926-afcd01e31544
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125204766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1125204766
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3257810353
Short name T17
Test name
Test status
Simulation time 1456071600 ps
CPU time 2.71 seconds
Started Jul 24 05:04:07 PM PDT 24
Finished Jul 24 05:04:10 PM PDT 24
Peak memory 205068 kb
Host smart-9da2d236-6c56-4b2f-9753-45ffa556c255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257810353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3257810353
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1052549267
Short name T120
Test name
Test status
Simulation time 7173162802 ps
CPU time 76.74 seconds
Started Jul 24 04:59:53 PM PDT 24
Finished Jul 24 05:01:10 PM PDT 24
Peak memory 205088 kb
Host smart-7f36ed71-0b06-4ee8-8ad9-7a5a6ed667d6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052549267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1052549267
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.1247189764
Short name T43
Test name
Test status
Simulation time 12064926038 ps
CPU time 32.51 seconds
Started Jul 24 05:04:19 PM PDT 24
Finished Jul 24 05:04:52 PM PDT 24
Peak memory 205408 kb
Host smart-7e3d5bed-67e1-4aad-af8e-5df83e74021a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247189764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1247189764
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.315892766
Short name T44
Test name
Test status
Simulation time 346059277 ps
CPU time 1.65 seconds
Started Jul 24 05:04:07 PM PDT 24
Finished Jul 24 05:04:09 PM PDT 24
Peak memory 204804 kb
Host smart-a58c527e-7684-47ee-8f23-262fb854a1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315892766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.315892766
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.808669818
Short name T158
Test name
Test status
Simulation time 3548147776 ps
CPU time 16.22 seconds
Started Jul 24 05:00:23 PM PDT 24
Finished Jul 24 05:00:40 PM PDT 24
Peak memory 213348 kb
Host smart-1e5971ff-1d33-46e2-b19c-edf13fc04527
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808669818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.808669818
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.38345413
Short name T20
Test name
Test status
Simulation time 657009641 ps
CPU time 1.58 seconds
Started Jul 24 05:04:13 PM PDT 24
Finished Jul 24 05:04:15 PM PDT 24
Peak memory 204876 kb
Host smart-ab8ff6ea-1d9c-4c5c-bcf5-3e2a92ab114f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38345413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.38345413
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.1477450887
Short name T28
Test name
Test status
Simulation time 99417901 ps
CPU time 0.68 seconds
Started Jul 24 05:04:10 PM PDT 24
Finished Jul 24 05:04:10 PM PDT 24
Peak memory 204912 kb
Host smart-916a3429-e5a6-470b-b5dc-6bff32763fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477450887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.1477450887
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2695792181
Short name T135
Test name
Test status
Simulation time 5206288815 ps
CPU time 5.07 seconds
Started Jul 24 05:05:37 PM PDT 24
Finished Jul 24 05:05:42 PM PDT 24
Peak memory 213372 kb
Host smart-54a001a6-90b5-49bb-9241-d23d5267e005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695792181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2695792181
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3087727149
Short name T130
Test name
Test status
Simulation time 2986785955 ps
CPU time 10.43 seconds
Started Jul 24 05:00:46 PM PDT 24
Finished Jul 24 05:00:57 PM PDT 24
Peak memory 213308 kb
Host smart-c0b9cd37-9f43-46b6-af99-0ec3209e18f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087727149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
087727149
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2286718480
Short name T131
Test name
Test status
Simulation time 24103580199 ps
CPU time 59.03 seconds
Started Jul 24 05:04:22 PM PDT 24
Finished Jul 24 05:05:21 PM PDT 24
Peak memory 213576 kb
Host smart-e4396c55-5b8e-4555-9c71-f3fdd443525f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286718480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2286718480
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.232801285
Short name T317
Test name
Test status
Simulation time 781354925 ps
CPU time 2.56 seconds
Started Jul 24 05:00:26 PM PDT 24
Finished Jul 24 05:00:29 PM PDT 24
Peak memory 204816 kb
Host smart-002b4d94-83a2-4987-998d-38f6c05be12d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232801285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.232801285
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3566765863
Short name T99
Test name
Test status
Simulation time 6010361358 ps
CPU time 10.99 seconds
Started Jul 24 05:00:30 PM PDT 24
Finished Jul 24 05:00:41 PM PDT 24
Peak memory 205128 kb
Host smart-8c3b31b4-f13f-42f2-8d74-4e7f1e5ac789
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566765863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3566765863
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3646597637
Short name T398
Test name
Test status
Simulation time 4519409503 ps
CPU time 26.47 seconds
Started Jul 24 05:00:40 PM PDT 24
Finished Jul 24 05:01:06 PM PDT 24
Peak memory 213232 kb
Host smart-8449ffef-0608-4c58-8ab9-2c7dcdcc7bdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646597637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
646597637
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1635006099
Short name T36
Test name
Test status
Simulation time 303578856 ps
CPU time 1.09 seconds
Started Jul 24 05:03:54 PM PDT 24
Finished Jul 24 05:03:55 PM PDT 24
Peak memory 204960 kb
Host smart-8b3ffbc5-24ed-4c4a-bf9f-fefa0857bfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635006099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1635006099
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2938547650
Short name T146
Test name
Test status
Simulation time 737282560 ps
CPU time 2.42 seconds
Started Jul 24 05:03:57 PM PDT 24
Finished Jul 24 05:03:59 PM PDT 24
Peak memory 204856 kb
Host smart-d7e1ad7d-6dcc-4d24-9c69-4b460fbea165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938547650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2938547650
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.2824656003
Short name T24
Test name
Test status
Simulation time 6487068802 ps
CPU time 11.52 seconds
Started Jul 24 05:04:16 PM PDT 24
Finished Jul 24 05:04:28 PM PDT 24
Peak memory 205232 kb
Host smart-4595de54-19ab-41e4-93d2-955a05ceed1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824656003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2824656003
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2533391296
Short name T156
Test name
Test status
Simulation time 1108449514 ps
CPU time 11.31 seconds
Started Jul 24 05:00:40 PM PDT 24
Finished Jul 24 05:00:52 PM PDT 24
Peak memory 213136 kb
Host smart-ff03b70f-0a68-4c21-b96a-c5896243b039
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533391296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
533391296
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.1108832078
Short name T167
Test name
Test status
Simulation time 3367393335 ps
CPU time 9.77 seconds
Started Jul 24 05:04:11 PM PDT 24
Finished Jul 24 05:04:21 PM PDT 24
Peak memory 213176 kb
Host smart-ccec4205-f8bd-4481-8412-2363b0a69a40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108832078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.1108832078
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.466815224
Short name T419
Test name
Test status
Simulation time 2865349491 ps
CPU time 26.85 seconds
Started Jul 24 05:00:21 PM PDT 24
Finished Jul 24 05:00:48 PM PDT 24
Peak memory 213328 kb
Host smart-8b428dab-0930-4038-bb7b-52069760a553
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466815224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.466815224
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2692084883
Short name T117
Test name
Test status
Simulation time 572549828 ps
CPU time 1.69 seconds
Started Jul 24 05:00:04 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 213160 kb
Host smart-133c0546-bc75-48bd-bead-8f9d7ff9ea65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692084883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2692084883
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2721787652
Short name T363
Test name
Test status
Simulation time 880404905 ps
CPU time 4.16 seconds
Started Jul 24 05:00:12 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 219224 kb
Host smart-48a5538a-d9f2-4a86-8517-4ece7c91b7d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721787652 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2721787652
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.4163331297
Short name T105
Test name
Test status
Simulation time 108994869 ps
CPU time 2.24 seconds
Started Jul 24 05:00:17 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 213300 kb
Host smart-8ac95c79-bbcd-4ce5-a69a-505f4f139c56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163331297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.4163331297
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3949016261
Short name T328
Test name
Test status
Simulation time 25436821909 ps
CPU time 22.25 seconds
Started Jul 24 05:00:24 PM PDT 24
Finished Jul 24 05:00:46 PM PDT 24
Peak memory 205104 kb
Host smart-0c776c30-7617-4810-8262-a3bdc5ab58cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949016261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3949016261
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4188570740
Short name T354
Test name
Test status
Simulation time 15361949729 ps
CPU time 6.95 seconds
Started Jul 24 05:00:20 PM PDT 24
Finished Jul 24 05:00:27 PM PDT 24
Peak memory 204948 kb
Host smart-1a3564f5-fc61-4a73-909c-69ade8c6112b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188570740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.4188570740
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1829554824
Short name T335
Test name
Test status
Simulation time 2766483677 ps
CPU time 5.84 seconds
Started Jul 24 05:00:07 PM PDT 24
Finished Jul 24 05:00:21 PM PDT 24
Peak memory 204988 kb
Host smart-0e8232d3-b45c-45ef-b03b-252c242d2a12
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829554824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
829554824
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.340359526
Short name T370
Test name
Test status
Simulation time 414027610 ps
CPU time 1.17 seconds
Started Jul 24 05:00:11 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204784 kb
Host smart-df339ba4-39a4-4777-9b6d-9ae96e6cdb04
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340359526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.340359526
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.791600463
Short name T399
Test name
Test status
Simulation time 5388040285 ps
CPU time 6.43 seconds
Started Jul 24 05:00:07 PM PDT 24
Finished Jul 24 05:00:22 PM PDT 24
Peak memory 204928 kb
Host smart-d22a6993-09a2-4998-8e59-74f787e9aa67
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791600463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.791600463
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.382461501
Short name T350
Test name
Test status
Simulation time 219272941 ps
CPU time 1.06 seconds
Started Jul 24 05:00:05 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204772 kb
Host smart-a24df00e-b7dc-49b5-8256-f223a88bf3bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382461501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_hw_reset.382461501
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4053647401
Short name T334
Test name
Test status
Simulation time 1061027272 ps
CPU time 1.48 seconds
Started Jul 24 05:00:19 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 204824 kb
Host smart-3ebc75cb-2355-4c7b-9418-c39ba48786e6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053647401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.4
053647401
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2094736236
Short name T321
Test name
Test status
Simulation time 112168957 ps
CPU time 0.79 seconds
Started Jul 24 05:00:09 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204720 kb
Host smart-9da3c9eb-5e8a-46f5-9f50-2a8cbd2d40e8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094736236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2094736236
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1154363134
Short name T290
Test name
Test status
Simulation time 59789063 ps
CPU time 0.66 seconds
Started Jul 24 05:00:11 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204720 kb
Host smart-caf44fed-dd89-4162-8aca-fcbccc19ea42
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154363134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1154363134
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.747854607
Short name T110
Test name
Test status
Simulation time 404499422 ps
CPU time 7.01 seconds
Started Jul 24 05:00:13 PM PDT 24
Finished Jul 24 05:00:23 PM PDT 24
Peak memory 204924 kb
Host smart-6e3ef233-e971-4615-8b70-3faeee076316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747854607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.747854607
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3442669
Short name T71
Test name
Test status
Simulation time 27009174309 ps
CPU time 23.74 seconds
Started Jul 24 05:00:19 PM PDT 24
Finished Jul 24 05:00:43 PM PDT 24
Peak memory 221380 kb
Host smart-dd054725-3571-4cf8-bca4-ce45be5ef72f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442669 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3442669
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2709994099
Short name T390
Test name
Test status
Simulation time 181957018 ps
CPU time 4.64 seconds
Started Jul 24 05:00:19 PM PDT 24
Finished Jul 24 05:00:24 PM PDT 24
Peak memory 213268 kb
Host smart-24b65464-667f-465e-9390-e7243c0de058
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709994099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2709994099
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2628397819
Short name T155
Test name
Test status
Simulation time 4902867518 ps
CPU time 20.7 seconds
Started Jul 24 05:00:19 PM PDT 24
Finished Jul 24 05:00:40 PM PDT 24
Peak memory 213196 kb
Host smart-26b16b08-ba31-4ec6-9374-bbf3e16bf39b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628397819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2628397819
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1031100640
Short name T123
Test name
Test status
Simulation time 3484681964 ps
CPU time 76.87 seconds
Started Jul 24 05:00:16 PM PDT 24
Finished Jul 24 05:01:34 PM PDT 24
Peak memory 213256 kb
Host smart-b5fce8bb-7dd8-4b9c-aef8-d5d8ead9d2eb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031100640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1031100640
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.715686436
Short name T88
Test name
Test status
Simulation time 9833376049 ps
CPU time 64.26 seconds
Started Jul 24 05:00:26 PM PDT 24
Finished Jul 24 05:01:30 PM PDT 24
Peak memory 213288 kb
Host smart-85559d10-4999-4c59-9776-8e3dfb840231
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715686436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.715686436
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.968591287
Short name T416
Test name
Test status
Simulation time 222794158 ps
CPU time 1.61 seconds
Started Jul 24 05:00:12 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 213104 kb
Host smart-3292778c-989e-4f38-a01c-9fe26ffe2f1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968591287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.968591287
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3644702356
Short name T418
Test name
Test status
Simulation time 178610982 ps
CPU time 2.36 seconds
Started Jul 24 05:00:24 PM PDT 24
Finished Jul 24 05:00:26 PM PDT 24
Peak memory 221480 kb
Host smart-b027cd68-a917-485f-a3fe-7b418e5e0365
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644702356 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3644702356
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3891057432
Short name T408
Test name
Test status
Simulation time 148950848 ps
CPU time 1.54 seconds
Started Jul 24 05:00:01 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 213132 kb
Host smart-fb8f88fd-dba6-4f73-91e5-640fa772f56a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891057432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3891057432
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.325717878
Short name T295
Test name
Test status
Simulation time 211844075284 ps
CPU time 289.25 seconds
Started Jul 24 05:00:29 PM PDT 24
Finished Jul 24 05:05:18 PM PDT 24
Peak memory 210012 kb
Host smart-568c9e4c-c752-4f3f-8179-465ad7f5b9e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325717878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.325717878
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2287307531
Short name T296
Test name
Test status
Simulation time 3335958313 ps
CPU time 10.64 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:33 PM PDT 24
Peak memory 205028 kb
Host smart-1098ee18-991d-45f4-b1a8-778858bd72e7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287307531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.2287307531
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.31212108
Short name T101
Test name
Test status
Simulation time 4260847874 ps
CPU time 4.74 seconds
Started Jul 24 05:00:26 PM PDT 24
Finished Jul 24 05:00:31 PM PDT 24
Peak memory 205136 kb
Host smart-f7e0d623-5495-41ec-8aaa-d3aafdf88b7d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31212108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_
hw_reset.31212108
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1614038780
Short name T309
Test name
Test status
Simulation time 10586162754 ps
CPU time 8.35 seconds
Started Jul 24 05:00:20 PM PDT 24
Finished Jul 24 05:00:29 PM PDT 24
Peak memory 204992 kb
Host smart-3d50cca0-b603-47ee-96e8-b2fa60300bd4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614038780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
614038780
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3833726645
Short name T346
Test name
Test status
Simulation time 9290138791 ps
CPU time 7.25 seconds
Started Jul 24 05:00:19 PM PDT 24
Finished Jul 24 05:00:26 PM PDT 24
Peak memory 204972 kb
Host smart-b69a5e37-aac6-4010-8bf7-7c9a826601f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833726645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3833726645
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.135675630
Short name T333
Test name
Test status
Simulation time 265282718 ps
CPU time 1.06 seconds
Started Jul 24 05:00:14 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 204728 kb
Host smart-7a03d4f8-fcae-4381-b073-f257402e8e17
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135675630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.135675630
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2254400699
Short name T348
Test name
Test status
Simulation time 334713193 ps
CPU time 0.93 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:23 PM PDT 24
Peak memory 204796 kb
Host smart-54d3bf4d-eaef-48f6-8c3e-372d3af81fff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254400699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
254400699
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1163013402
Short name T422
Test name
Test status
Simulation time 68962723 ps
CPU time 0.69 seconds
Started Jul 24 05:00:26 PM PDT 24
Finished Jul 24 05:00:27 PM PDT 24
Peak memory 204760 kb
Host smart-0576140f-4445-4681-aadb-e55b81e2373d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163013402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1163013402
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3065541209
Short name T353
Test name
Test status
Simulation time 142265239 ps
CPU time 0.75 seconds
Started Jul 24 05:00:24 PM PDT 24
Finished Jul 24 05:00:25 PM PDT 24
Peak memory 204880 kb
Host smart-0735fa28-4a7a-4a58-a5f0-ccd6d6a2861c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065541209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3065541209
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.813802808
Short name T126
Test name
Test status
Simulation time 870425527 ps
CPU time 7.43 seconds
Started Jul 24 05:00:19 PM PDT 24
Finished Jul 24 05:00:26 PM PDT 24
Peak memory 204948 kb
Host smart-e915fc29-ebb6-448e-b5ef-a662ed0e7636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813802808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.813802808
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1929168779
Short name T162
Test name
Test status
Simulation time 26687927902 ps
CPU time 50.93 seconds
Started Jul 24 05:00:07 PM PDT 24
Finished Jul 24 05:01:06 PM PDT 24
Peak memory 221420 kb
Host smart-e8d25d02-4335-4180-b8c3-9234b6f8f260
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929168779 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1929168779
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.54762914
Short name T405
Test name
Test status
Simulation time 96086242 ps
CPU time 2.44 seconds
Started Jul 24 05:00:29 PM PDT 24
Finished Jul 24 05:00:32 PM PDT 24
Peak memory 213344 kb
Host smart-2a315d5b-4416-4f94-b8ef-678a72a21e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54762914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.54762914
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2513297947
Short name T157
Test name
Test status
Simulation time 885300521 ps
CPU time 9.11 seconds
Started Jul 24 05:00:17 PM PDT 24
Finished Jul 24 05:00:27 PM PDT 24
Peak memory 213216 kb
Host smart-b6c845bd-1abf-44bd-ae9b-0dc13d14c253
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513297947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2513297947
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3076312878
Short name T401
Test name
Test status
Simulation time 300453341 ps
CPU time 2.1 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:00:27 PM PDT 24
Peak memory 216016 kb
Host smart-3d562e5a-944f-4272-8f89-c11f4291ef28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076312878 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3076312878
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2002061451
Short name T413
Test name
Test status
Simulation time 544829342 ps
CPU time 2.37 seconds
Started Jul 24 05:00:34 PM PDT 24
Finished Jul 24 05:00:37 PM PDT 24
Peak memory 213236 kb
Host smart-13d695bb-de59-4d3c-b689-e2c0507ac1fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002061451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2002061451
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3066045003
Short name T429
Test name
Test status
Simulation time 14306713026 ps
CPU time 12.04 seconds
Started Jul 24 05:00:41 PM PDT 24
Finished Jul 24 05:00:53 PM PDT 24
Peak memory 204956 kb
Host smart-95598170-4e04-4c57-ad8e-7d3a02cb8c2b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066045003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.3066045003
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2082709371
Short name T339
Test name
Test status
Simulation time 2074138282 ps
CPU time 2.2 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:00:28 PM PDT 24
Peak memory 204860 kb
Host smart-582d109d-a6b5-4ee8-adee-dc5fe709996b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082709371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2082709371
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2027480039
Short name T423
Test name
Test status
Simulation time 461209805 ps
CPU time 1.24 seconds
Started Jul 24 05:00:35 PM PDT 24
Finished Jul 24 05:00:37 PM PDT 24
Peak memory 204716 kb
Host smart-a73f3f84-0e5c-4149-9cb2-af0f24d78599
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027480039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2027480039
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3727367071
Short name T65
Test name
Test status
Simulation time 620245771 ps
CPU time 4.15 seconds
Started Jul 24 05:00:33 PM PDT 24
Finished Jul 24 05:00:37 PM PDT 24
Peak memory 204892 kb
Host smart-e11f4b54-8978-49c7-ae88-72275c17cc86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727367071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3727367071
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4232609040
Short name T432
Test name
Test status
Simulation time 238423674 ps
CPU time 3.44 seconds
Started Jul 24 05:00:32 PM PDT 24
Finished Jul 24 05:00:36 PM PDT 24
Peak memory 213160 kb
Host smart-e5dcc2ee-85a3-4f5b-bd93-a001fe5d156d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232609040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.4232609040
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1430428288
Short name T161
Test name
Test status
Simulation time 1244099808 ps
CPU time 10.36 seconds
Started Jul 24 05:00:43 PM PDT 24
Finished Jul 24 05:00:53 PM PDT 24
Peak memory 213012 kb
Host smart-4c75d643-84ac-4375-ae47-83e70e738db3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430428288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
430428288
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3005087135
Short name T341
Test name
Test status
Simulation time 245190817 ps
CPU time 3.98 seconds
Started Jul 24 05:00:44 PM PDT 24
Finished Jul 24 05:00:48 PM PDT 24
Peak memory 219640 kb
Host smart-a0c87b56-5495-4b8b-9776-cf22b5840dcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005087135 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3005087135
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2849534591
Short name T320
Test name
Test status
Simulation time 82518578 ps
CPU time 1.62 seconds
Started Jul 24 05:00:30 PM PDT 24
Finished Jul 24 05:00:31 PM PDT 24
Peak memory 213196 kb
Host smart-50536959-399a-4b54-8f40-3b8f2e90e5e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849534591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2849534591
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2500061322
Short name T368
Test name
Test status
Simulation time 14185235714 ps
CPU time 13.3 seconds
Started Jul 24 05:00:36 PM PDT 24
Finished Jul 24 05:00:50 PM PDT 24
Peak memory 204992 kb
Host smart-39c2b726-1a37-4047-94a6-d141ec489571
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500061322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.2500061322
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1674796089
Short name T291
Test name
Test status
Simulation time 1683401738 ps
CPU time 2.64 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:24 PM PDT 24
Peak memory 205004 kb
Host smart-e0f0e213-b164-49ff-bd4d-9b9b0ce001bf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674796089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1674796089
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3552897477
Short name T394
Test name
Test status
Simulation time 99100044 ps
CPU time 0.75 seconds
Started Jul 24 05:00:38 PM PDT 24
Finished Jul 24 05:00:39 PM PDT 24
Peak memory 204664 kb
Host smart-3599c2d5-5868-4ce2-baf3-1328015910b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552897477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3552897477
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.140566875
Short name T127
Test name
Test status
Simulation time 536877771 ps
CPU time 4.28 seconds
Started Jul 24 05:00:29 PM PDT 24
Finished Jul 24 05:00:33 PM PDT 24
Peak memory 204900 kb
Host smart-761beec1-7453-4137-8843-acbe2a29e88f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140566875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.140566875
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3350135786
Short name T82
Test name
Test status
Simulation time 353212952 ps
CPU time 3.02 seconds
Started Jul 24 05:00:27 PM PDT 24
Finished Jul 24 05:00:30 PM PDT 24
Peak memory 213228 kb
Host smart-342abd03-f18d-436b-9669-ed6dc5cb0cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350135786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3350135786
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4234411043
Short name T406
Test name
Test status
Simulation time 1629142905 ps
CPU time 11.2 seconds
Started Jul 24 05:00:21 PM PDT 24
Finished Jul 24 05:00:33 PM PDT 24
Peak memory 213068 kb
Host smart-75afbe3a-1d3c-4861-9952-fde460cae13f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234411043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.4
234411043
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.293306455
Short name T332
Test name
Test status
Simulation time 357469299 ps
CPU time 2.51 seconds
Started Jul 24 05:00:33 PM PDT 24
Finished Jul 24 05:00:36 PM PDT 24
Peak memory 217832 kb
Host smart-ae5ea416-a58f-4321-90e0-6622cb1553b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293306455 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.293306455
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1689367543
Short name T358
Test name
Test status
Simulation time 177211553 ps
CPU time 2.17 seconds
Started Jul 24 05:00:38 PM PDT 24
Finished Jul 24 05:00:41 PM PDT 24
Peak memory 213188 kb
Host smart-cc68b6c9-c374-45cd-b3cc-ff79caab464a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689367543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1689367543
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.765618260
Short name T414
Test name
Test status
Simulation time 12121417345 ps
CPU time 38.55 seconds
Started Jul 24 05:00:23 PM PDT 24
Finished Jul 24 05:01:02 PM PDT 24
Peak memory 204872 kb
Host smart-a3b48561-46f0-4d07-aadd-166e60100dea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765618260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rv_dm_jtag_dmi_csr_bit_bash.765618260
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2071468963
Short name T377
Test name
Test status
Simulation time 880507412 ps
CPU time 1.48 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:00:26 PM PDT 24
Peak memory 204796 kb
Host smart-486f19ab-2a0d-4353-8e3c-3bc269d9c1e3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071468963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2071468963
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1284060741
Short name T412
Test name
Test status
Simulation time 175657593 ps
CPU time 0.94 seconds
Started Jul 24 05:00:37 PM PDT 24
Finished Jul 24 05:00:38 PM PDT 24
Peak memory 204976 kb
Host smart-d241c6d0-87c3-44b8-a2ff-3faab8738ae5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284060741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1284060741
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.149992538
Short name T112
Test name
Test status
Simulation time 804048070 ps
CPU time 7.32 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:00:32 PM PDT 24
Peak memory 204996 kb
Host smart-ed3f7e45-6f2d-4d8c-9eef-d79b4cb27d35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149992538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.149992538
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3797547020
Short name T396
Test name
Test status
Simulation time 308598642 ps
CPU time 2.85 seconds
Started Jul 24 05:00:24 PM PDT 24
Finished Jul 24 05:00:27 PM PDT 24
Peak memory 213376 kb
Host smart-39ad9b28-90a7-40db-aacb-5db43cee6424
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797547020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3797547020
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1921382407
Short name T151
Test name
Test status
Simulation time 11225468729 ps
CPU time 20.8 seconds
Started Jul 24 05:00:36 PM PDT 24
Finished Jul 24 05:01:02 PM PDT 24
Peak memory 213180 kb
Host smart-f2a765bc-1d16-4c4a-9c50-a0913b69c3da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921382407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
921382407
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3573530998
Short name T431
Test name
Test status
Simulation time 266265690 ps
CPU time 2.21 seconds
Started Jul 24 05:00:23 PM PDT 24
Finished Jul 24 05:00:26 PM PDT 24
Peak memory 216728 kb
Host smart-10387c03-3000-49de-afb7-f66e772186ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573530998 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3573530998
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.691479057
Short name T376
Test name
Test status
Simulation time 63099035 ps
CPU time 1.6 seconds
Started Jul 24 05:00:33 PM PDT 24
Finished Jul 24 05:00:35 PM PDT 24
Peak memory 213164 kb
Host smart-19f85878-15d6-4928-9dae-9823f90cacc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691479057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.691479057
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2995240376
Short name T293
Test name
Test status
Simulation time 8828649260 ps
CPU time 24.26 seconds
Started Jul 24 05:00:24 PM PDT 24
Finished Jul 24 05:00:48 PM PDT 24
Peak memory 204968 kb
Host smart-e4ef12f2-2051-4159-8279-335cc33fccb5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995240376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2995240376
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1704137718
Short name T357
Test name
Test status
Simulation time 6989405399 ps
CPU time 9.29 seconds
Started Jul 24 05:00:27 PM PDT 24
Finished Jul 24 05:00:36 PM PDT 24
Peak memory 204972 kb
Host smart-a58633cf-0c5a-46ff-b692-ad7ae7f363eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704137718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1704137718
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3939115924
Short name T360
Test name
Test status
Simulation time 91899555 ps
CPU time 0.83 seconds
Started Jul 24 05:00:46 PM PDT 24
Finished Jul 24 05:00:47 PM PDT 24
Peak memory 204784 kb
Host smart-e2409e17-dd9d-4784-88b4-0b6c71c55544
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939115924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3939115924
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3642454224
Short name T94
Test name
Test status
Simulation time 587571400 ps
CPU time 4.33 seconds
Started Jul 24 05:00:42 PM PDT 24
Finished Jul 24 05:00:47 PM PDT 24
Peak memory 204976 kb
Host smart-84158147-91ff-463b-adff-ce65b659862c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642454224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3642454224
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.318514425
Short name T392
Test name
Test status
Simulation time 192149976 ps
CPU time 3.31 seconds
Started Jul 24 05:00:24 PM PDT 24
Finished Jul 24 05:00:27 PM PDT 24
Peak memory 213228 kb
Host smart-f4c1e8e4-0c93-4b24-ba21-7682b3ecee94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318514425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.318514425
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3362828467
Short name T159
Test name
Test status
Simulation time 1250036199 ps
CPU time 10.32 seconds
Started Jul 24 05:00:41 PM PDT 24
Finished Jul 24 05:00:51 PM PDT 24
Peak memory 213220 kb
Host smart-bc6cf031-a7fb-4703-9790-37c49f714791
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362828467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
362828467
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3576716182
Short name T382
Test name
Test status
Simulation time 183155585 ps
CPU time 4.06 seconds
Started Jul 24 05:00:42 PM PDT 24
Finished Jul 24 05:00:47 PM PDT 24
Peak memory 219364 kb
Host smart-fc53d26e-dfa0-458e-acf7-3726c9d4ad42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576716182 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3576716182
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3394106070
Short name T397
Test name
Test status
Simulation time 224830903 ps
CPU time 2.01 seconds
Started Jul 24 05:00:44 PM PDT 24
Finished Jul 24 05:00:46 PM PDT 24
Peak memory 213252 kb
Host smart-9c31f7e1-9138-4b71-a064-7df0e9f52832
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394106070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3394106070
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4071575884
Short name T400
Test name
Test status
Simulation time 4306314601 ps
CPU time 3.16 seconds
Started Jul 24 05:00:28 PM PDT 24
Finished Jul 24 05:00:31 PM PDT 24
Peak memory 204916 kb
Host smart-fc25c378-5242-4b2b-890b-5c12353046f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071575884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.4071575884
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.753302953
Short name T369
Test name
Test status
Simulation time 2619435662 ps
CPU time 3.26 seconds
Started Jul 24 05:00:38 PM PDT 24
Finished Jul 24 05:00:42 PM PDT 24
Peak memory 205008 kb
Host smart-52b3c209-0025-4737-8c36-4853a3fd6fed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753302953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.753302953
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.954752197
Short name T425
Test name
Test status
Simulation time 123211432 ps
CPU time 0.96 seconds
Started Jul 24 05:00:24 PM PDT 24
Finished Jul 24 05:00:25 PM PDT 24
Peak memory 204732 kb
Host smart-d790bc92-938d-49ae-9ea5-9201893ceb57
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954752197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.954752197
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3978700708
Short name T111
Test name
Test status
Simulation time 1744650918 ps
CPU time 7.33 seconds
Started Jul 24 05:00:30 PM PDT 24
Finished Jul 24 05:00:37 PM PDT 24
Peak memory 204984 kb
Host smart-bd50f053-5bab-4fe8-b374-f81fcc63bc95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978700708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3978700708
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3121906176
Short name T361
Test name
Test status
Simulation time 220903626 ps
CPU time 2.76 seconds
Started Jul 24 05:00:43 PM PDT 24
Finished Jul 24 05:00:46 PM PDT 24
Peak memory 213356 kb
Host smart-8b1f55bd-6f75-4a34-9868-412577edb6fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121906176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3121906176
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3268951285
Short name T424
Test name
Test status
Simulation time 219208205 ps
CPU time 2.53 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:00:28 PM PDT 24
Peak memory 221456 kb
Host smart-81bd78fc-4284-4879-9476-338d6d108900
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268951285 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3268951285
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3493851523
Short name T119
Test name
Test status
Simulation time 423637656 ps
CPU time 1.62 seconds
Started Jul 24 05:00:45 PM PDT 24
Finished Jul 24 05:00:47 PM PDT 24
Peak memory 213200 kb
Host smart-e5ef4a69-84b0-476d-8cf4-fa00d5b6b128
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493851523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3493851523
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.665012276
Short name T300
Test name
Test status
Simulation time 36633445979 ps
CPU time 89.18 seconds
Started Jul 24 05:00:34 PM PDT 24
Finished Jul 24 05:02:04 PM PDT 24
Peak memory 204820 kb
Host smart-0e490a5b-f158-48e9-8fc3-4ace8ba9da4a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665012276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rv_dm_jtag_dmi_csr_bit_bash.665012276
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2428289543
Short name T344
Test name
Test status
Simulation time 3580860571 ps
CPU time 5.92 seconds
Started Jul 24 05:00:38 PM PDT 24
Finished Jul 24 05:00:44 PM PDT 24
Peak memory 204752 kb
Host smart-5fedd742-69a9-460d-9194-c19a04f344e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428289543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2428289543
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3025656096
Short name T304
Test name
Test status
Simulation time 168283341 ps
CPU time 0.75 seconds
Started Jul 24 05:00:35 PM PDT 24
Finished Jul 24 05:00:36 PM PDT 24
Peak memory 204800 kb
Host smart-59bfc616-a7f1-4fe4-bb99-8a5cd1ae90bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025656096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3025656096
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3887425680
Short name T91
Test name
Test status
Simulation time 236970274 ps
CPU time 4.05 seconds
Started Jul 24 05:00:39 PM PDT 24
Finished Jul 24 05:00:43 PM PDT 24
Peak memory 204976 kb
Host smart-8b8967a2-bebb-446d-919a-e15339d285d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887425680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3887425680
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2944404838
Short name T322
Test name
Test status
Simulation time 150301896 ps
CPU time 2.35 seconds
Started Jul 24 05:00:41 PM PDT 24
Finished Jul 24 05:00:44 PM PDT 24
Peak memory 213180 kb
Host smart-e953d76e-2ea4-4187-afc8-d55c6352b3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944404838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2944404838
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.720014997
Short name T154
Test name
Test status
Simulation time 1761422336 ps
CPU time 8.74 seconds
Started Jul 24 05:00:26 PM PDT 24
Finished Jul 24 05:00:35 PM PDT 24
Peak memory 212360 kb
Host smart-00641d7b-06dd-439c-b216-3ab589736813
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720014997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.720014997
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.82377392
Short name T342
Test name
Test status
Simulation time 595270390 ps
CPU time 3.69 seconds
Started Jul 24 05:00:38 PM PDT 24
Finished Jul 24 05:00:42 PM PDT 24
Peak memory 218276 kb
Host smart-a0eb7ecf-eae4-4994-9d0e-82f394168418
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82377392 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.82377392
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2345877439
Short name T121
Test name
Test status
Simulation time 102244345 ps
CPU time 1.44 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:00:27 PM PDT 24
Peak memory 213144 kb
Host smart-8255effc-ee11-41ae-8bb8-3c8ca7e6dfca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345877439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2345877439
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3067866773
Short name T298
Test name
Test status
Simulation time 13457054934 ps
CPU time 35.71 seconds
Started Jul 24 05:00:40 PM PDT 24
Finished Jul 24 05:01:16 PM PDT 24
Peak memory 204960 kb
Host smart-4649bb27-f9b1-4d46-8c9a-61b1e04163f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067866773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.3067866773
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2836574522
Short name T387
Test name
Test status
Simulation time 11104037736 ps
CPU time 6.66 seconds
Started Jul 24 05:00:26 PM PDT 24
Finished Jul 24 05:00:33 PM PDT 24
Peak memory 205068 kb
Host smart-b5909e99-fc8c-45ef-ba15-ed67cfdb38b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836574522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2836574522
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2648005322
Short name T383
Test name
Test status
Simulation time 1031105770 ps
CPU time 1.94 seconds
Started Jul 24 05:00:33 PM PDT 24
Finished Jul 24 05:00:35 PM PDT 24
Peak memory 204744 kb
Host smart-13a2d5fb-4b69-4427-b88b-279418003ab3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648005322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2648005322
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3871703899
Short name T373
Test name
Test status
Simulation time 161735999 ps
CPU time 6.18 seconds
Started Jul 24 05:00:42 PM PDT 24
Finished Jul 24 05:00:49 PM PDT 24
Peak memory 205020 kb
Host smart-76b6fa66-c460-4633-9d9f-2934cd9e4836
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871703899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3871703899
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2478259598
Short name T64
Test name
Test status
Simulation time 556918711 ps
CPU time 6.57 seconds
Started Jul 24 05:00:28 PM PDT 24
Finished Jul 24 05:00:40 PM PDT 24
Peak memory 213256 kb
Host smart-5677f6dc-6779-4203-bd46-a2570a8bda9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478259598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2478259598
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.158963468
Short name T85
Test name
Test status
Simulation time 614715969 ps
CPU time 9.56 seconds
Started Jul 24 05:00:39 PM PDT 24
Finished Jul 24 05:00:49 PM PDT 24
Peak memory 213136 kb
Host smart-0d11fbac-36d8-4054-9742-81d990a3a223
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158963468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.158963468
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3442472854
Short name T326
Test name
Test status
Simulation time 700499419 ps
CPU time 3.64 seconds
Started Jul 24 05:00:36 PM PDT 24
Finished Jul 24 05:00:40 PM PDT 24
Peak memory 217504 kb
Host smart-45b418a5-1172-406d-acb0-a1efa39797ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442472854 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3442472854
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.196748038
Short name T89
Test name
Test status
Simulation time 140935094 ps
CPU time 2.15 seconds
Started Jul 24 05:00:41 PM PDT 24
Finished Jul 24 05:00:44 PM PDT 24
Peak memory 213260 kb
Host smart-dcd2d719-ced1-475e-8cb8-0a4a7234d771
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196748038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.196748038
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3728365638
Short name T294
Test name
Test status
Simulation time 36743670353 ps
CPU time 15.39 seconds
Started Jul 24 05:00:33 PM PDT 24
Finished Jul 24 05:00:48 PM PDT 24
Peak memory 205004 kb
Host smart-a3f20726-69a6-491c-af89-05684a37d6f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728365638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.3728365638
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.620148986
Short name T433
Test name
Test status
Simulation time 6007557539 ps
CPU time 18.07 seconds
Started Jul 24 05:00:52 PM PDT 24
Finished Jul 24 05:01:10 PM PDT 24
Peak memory 205028 kb
Host smart-afa680d1-dd97-49e0-a36e-27ad8140ee07
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620148986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.620148986
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2185278719
Short name T306
Test name
Test status
Simulation time 252620824 ps
CPU time 0.75 seconds
Started Jul 24 05:00:23 PM PDT 24
Finished Jul 24 05:00:24 PM PDT 24
Peak memory 204704 kb
Host smart-7b592712-d41f-4b9a-b150-0af172d2e274
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185278719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2185278719
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3448345566
Short name T95
Test name
Test status
Simulation time 602938135 ps
CPU time 6.48 seconds
Started Jul 24 05:00:35 PM PDT 24
Finished Jul 24 05:00:42 PM PDT 24
Peak memory 204936 kb
Host smart-877ad176-78a2-46e9-b6c2-313c8c5ba436
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448345566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3448345566
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.618537986
Short name T407
Test name
Test status
Simulation time 328965819 ps
CPU time 2.24 seconds
Started Jul 24 05:00:23 PM PDT 24
Finished Jul 24 05:00:26 PM PDT 24
Peak memory 213276 kb
Host smart-ee33415d-9aac-4d36-923d-8b9facf96101
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618537986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.618537986
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3177363728
Short name T437
Test name
Test status
Simulation time 2286592492 ps
CPU time 16.6 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:00:42 PM PDT 24
Peak memory 213304 kb
Host smart-f5296d88-ae22-422c-b634-d2909e3a2093
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177363728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
177363728
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3841083179
Short name T78
Test name
Test status
Simulation time 272827616 ps
CPU time 2.08 seconds
Started Jul 24 05:00:39 PM PDT 24
Finished Jul 24 05:00:41 PM PDT 24
Peak memory 218032 kb
Host smart-a6c304d4-fc9f-4ba1-8182-2514fdbd4952
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841083179 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3841083179
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1369947091
Short name T107
Test name
Test status
Simulation time 61053916 ps
CPU time 1.52 seconds
Started Jul 24 05:00:35 PM PDT 24
Finished Jul 24 05:00:36 PM PDT 24
Peak memory 213236 kb
Host smart-4271540c-7008-4147-925d-4e4cb9a45acc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369947091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1369947091
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.190382339
Short name T421
Test name
Test status
Simulation time 31874143113 ps
CPU time 18.62 seconds
Started Jul 24 05:00:27 PM PDT 24
Finished Jul 24 05:00:46 PM PDT 24
Peak memory 205064 kb
Host smart-47b52638-4194-427e-a190-47eaae446353
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190382339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rv_dm_jtag_dmi_csr_bit_bash.190382339
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1047229209
Short name T352
Test name
Test status
Simulation time 922636891 ps
CPU time 2.21 seconds
Started Jul 24 05:00:37 PM PDT 24
Finished Jul 24 05:00:40 PM PDT 24
Peak memory 204896 kb
Host smart-ed1c50a5-72b0-4f88-80c6-554dde7e1edd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047229209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1047229209
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2326382684
Short name T73
Test name
Test status
Simulation time 257505787 ps
CPU time 1.05 seconds
Started Jul 24 05:00:42 PM PDT 24
Finished Jul 24 05:00:43 PM PDT 24
Peak memory 204800 kb
Host smart-20c985c2-bcb7-4656-9c83-0957ef1d83e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326382684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2326382684
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3570648905
Short name T402
Test name
Test status
Simulation time 1420150233 ps
CPU time 7.69 seconds
Started Jul 24 05:00:35 PM PDT 24
Finished Jul 24 05:00:43 PM PDT 24
Peak memory 204908 kb
Host smart-307c0e11-e756-4f35-ad7d-bdfec1dd3fb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570648905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3570648905
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2281097293
Short name T97
Test name
Test status
Simulation time 101872766 ps
CPU time 2.32 seconds
Started Jul 24 05:00:56 PM PDT 24
Finished Jul 24 05:00:58 PM PDT 24
Peak memory 213356 kb
Host smart-e3256af0-0247-465b-be7f-55f3d54f0057
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281097293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2281097293
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1045747182
Short name T409
Test name
Test status
Simulation time 111948384 ps
CPU time 4.78 seconds
Started Jul 24 05:00:38 PM PDT 24
Finished Jul 24 05:00:43 PM PDT 24
Peak memory 219448 kb
Host smart-823daa97-5bbb-4b8e-8822-dda9fff3105b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045747182 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1045747182
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3854951459
Short name T340
Test name
Test status
Simulation time 133701675 ps
CPU time 1.38 seconds
Started Jul 24 05:00:41 PM PDT 24
Finished Jul 24 05:00:43 PM PDT 24
Peak memory 213088 kb
Host smart-49b173b2-c03f-4894-8145-d53da7139af7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854951459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3854951459
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1282583609
Short name T302
Test name
Test status
Simulation time 27650006960 ps
CPU time 44.34 seconds
Started Jul 24 05:00:43 PM PDT 24
Finished Jul 24 05:01:28 PM PDT 24
Peak memory 205012 kb
Host smart-c2819c7a-0a22-4eb5-b66d-5c2c54cfa880
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282583609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.1282583609
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3595329328
Short name T327
Test name
Test status
Simulation time 6005884656 ps
CPU time 9.77 seconds
Started Jul 24 05:00:34 PM PDT 24
Finished Jul 24 05:00:43 PM PDT 24
Peak memory 204956 kb
Host smart-d603a62b-63a1-4eb9-8d1a-b5a375faed1b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595329328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3595329328
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2635338953
Short name T391
Test name
Test status
Simulation time 136516332 ps
CPU time 0.74 seconds
Started Jul 24 05:00:26 PM PDT 24
Finished Jul 24 05:00:27 PM PDT 24
Peak memory 204784 kb
Host smart-70272f15-a7d8-45d8-b277-4f595a659fdc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635338953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2635338953
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2070118530
Short name T92
Test name
Test status
Simulation time 1075727346 ps
CPU time 7.88 seconds
Started Jul 24 05:00:40 PM PDT 24
Finished Jul 24 05:00:48 PM PDT 24
Peak memory 204896 kb
Host smart-1d33e25b-eef7-4cf6-9004-310b95eb6619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070118530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2070118530
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2270120484
Short name T381
Test name
Test status
Simulation time 221187163 ps
CPU time 5.6 seconds
Started Jul 24 05:00:45 PM PDT 24
Finished Jul 24 05:00:51 PM PDT 24
Peak memory 213228 kb
Host smart-13d216b1-464c-45bd-bc09-f4021206105d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270120484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2270120484
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1471527501
Short name T90
Test name
Test status
Simulation time 12505593471 ps
CPU time 33.69 seconds
Started Jul 24 05:00:12 PM PDT 24
Finished Jul 24 05:00:50 PM PDT 24
Peak memory 205068 kb
Host smart-21b49ce7-2156-4680-8a31-2cd8c70c6c65
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471527501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1471527501
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1791564194
Short name T109
Test name
Test status
Simulation time 20464134746 ps
CPU time 70.63 seconds
Started Jul 24 05:00:16 PM PDT 24
Finished Jul 24 05:01:28 PM PDT 24
Peak memory 213192 kb
Host smart-d6f2fc8c-30ac-468d-99a6-f049eb856792
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791564194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1791564194
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3318190961
Short name T93
Test name
Test status
Simulation time 771815779 ps
CPU time 2.76 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:25 PM PDT 24
Peak memory 213236 kb
Host smart-64dbe818-bee8-41b2-8bcc-d492561e68fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318190961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3318190961
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.71848125
Short name T330
Test name
Test status
Simulation time 305369809 ps
CPU time 4.11 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:27 PM PDT 24
Peak memory 219436 kb
Host smart-6f56a76d-40c1-454f-a823-8c2996b88ac2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71848125 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.71848125
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.428202012
Short name T108
Test name
Test status
Simulation time 47718148 ps
CPU time 1.51 seconds
Started Jul 24 05:00:16 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 213104 kb
Host smart-1ee848f6-9955-49b3-9b48-f9742896ce60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428202012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.428202012
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1456047366
Short name T364
Test name
Test status
Simulation time 64333042448 ps
CPU time 91.02 seconds
Started Jul 24 05:00:20 PM PDT 24
Finished Jul 24 05:01:51 PM PDT 24
Peak memory 204944 kb
Host smart-a595f8bf-70b6-4ac8-90a0-9de4d3d737f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456047366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1456047366
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1439350717
Short name T329
Test name
Test status
Simulation time 9035703234 ps
CPU time 7.31 seconds
Started Jul 24 05:00:18 PM PDT 24
Finished Jul 24 05:00:25 PM PDT 24
Peak memory 205060 kb
Host smart-b42bb4fe-97a9-4367-a749-63ed75e50481
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439350717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1439350717
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3730961736
Short name T102
Test name
Test status
Simulation time 2299137849 ps
CPU time 2.71 seconds
Started Jul 24 05:00:17 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 204988 kb
Host smart-528a4241-bb7f-41f7-84f9-4bb25deb22ab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730961736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3730961736
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.453029246
Short name T380
Test name
Test status
Simulation time 2896724337 ps
CPU time 8.46 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:31 PM PDT 24
Peak memory 205020 kb
Host smart-f5bef937-228a-4b9c-881f-56d26734d0fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453029246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.453029246
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1295627951
Short name T436
Test name
Test status
Simulation time 180482870 ps
CPU time 1.15 seconds
Started Jul 24 05:00:05 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204688 kb
Host smart-8e332ea0-6115-4a06-aede-9eac964192d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295627951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.1295627951
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1916377003
Short name T72
Test name
Test status
Simulation time 15167638384 ps
CPU time 21.73 seconds
Started Jul 24 05:00:20 PM PDT 24
Finished Jul 24 05:00:42 PM PDT 24
Peak memory 204936 kb
Host smart-31ad1183-83df-46c0-a409-980fc645d5c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916377003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1916377003
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1760579366
Short name T311
Test name
Test status
Simulation time 268562240 ps
CPU time 1 seconds
Started Jul 24 05:00:14 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 204848 kb
Host smart-43c91085-600d-4454-b892-bfcc7bbd23e7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760579366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1760579366
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3536680369
Short name T307
Test name
Test status
Simulation time 157328092 ps
CPU time 0.83 seconds
Started Jul 24 05:00:10 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204736 kb
Host smart-66e4e1e0-6e11-4405-8056-9b2f83ad9ca9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536680369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
536680369
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2721165707
Short name T299
Test name
Test status
Simulation time 148623255 ps
CPU time 0.74 seconds
Started Jul 24 05:00:29 PM PDT 24
Finished Jul 24 05:00:30 PM PDT 24
Peak memory 204760 kb
Host smart-92609b9c-be4d-4567-a958-32c5ea0c219a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721165707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2721165707
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.19062481
Short name T371
Test name
Test status
Simulation time 152684281 ps
CPU time 1.06 seconds
Started Jul 24 05:00:11 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204772 kb
Host smart-a7621427-67b6-40d1-b8e4-2bb58a500931
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19062481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.19062481
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.88573981
Short name T428
Test name
Test status
Simulation time 173414868 ps
CPU time 3.23 seconds
Started Jul 24 05:00:19 PM PDT 24
Finished Jul 24 05:00:22 PM PDT 24
Peak memory 213296 kb
Host smart-11902e0a-d79c-4833-a77c-1d17955dcdd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88573981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.88573981
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2759838370
Short name T122
Test name
Test status
Simulation time 2338370106 ps
CPU time 65.87 seconds
Started Jul 24 05:00:13 PM PDT 24
Finished Jul 24 05:01:26 PM PDT 24
Peak memory 213312 kb
Host smart-6c308a46-a19a-4522-98f8-52f520f6b8cf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759838370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2759838370
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1609893148
Short name T372
Test name
Test status
Simulation time 2573703246 ps
CPU time 33.09 seconds
Started Jul 24 05:00:15 PM PDT 24
Finished Jul 24 05:00:50 PM PDT 24
Peak memory 205060 kb
Host smart-36a7a288-23b8-4bf1-a8db-0eaeabd48e3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609893148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1609893148
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1224023608
Short name T114
Test name
Test status
Simulation time 311991945 ps
CPU time 2.41 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:25 PM PDT 24
Peak memory 213180 kb
Host smart-bdf296d6-13b1-44a6-80ac-1e36d2f90669
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224023608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1224023608
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.814006399
Short name T337
Test name
Test status
Simulation time 323007622 ps
CPU time 2.31 seconds
Started Jul 24 05:00:21 PM PDT 24
Finished Jul 24 05:00:24 PM PDT 24
Peak memory 221188 kb
Host smart-55010ce4-40d7-4ccf-bfe2-bcc168259265
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814006399 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.814006399
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3022708139
Short name T118
Test name
Test status
Simulation time 274580340 ps
CPU time 2.13 seconds
Started Jul 24 05:00:23 PM PDT 24
Finished Jul 24 05:00:26 PM PDT 24
Peak memory 213392 kb
Host smart-0ac8686d-aac3-4488-810b-986825a39489
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022708139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3022708139
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.893294781
Short name T351
Test name
Test status
Simulation time 59297805034 ps
CPU time 92.99 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:01:58 PM PDT 24
Peak memory 204852 kb
Host smart-29012196-c7d8-4646-9174-492267e36db3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893294781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.893294781
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3259669426
Short name T316
Test name
Test status
Simulation time 23453191634 ps
CPU time 59.31 seconds
Started Jul 24 05:00:27 PM PDT 24
Finished Jul 24 05:01:27 PM PDT 24
Peak memory 204936 kb
Host smart-841512a3-021b-40d3-9fa1-3c8ff5a2f12e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259669426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.3259669426
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4282971785
Short name T100
Test name
Test status
Simulation time 4839780655 ps
CPU time 8.07 seconds
Started Jul 24 05:00:17 PM PDT 24
Finished Jul 24 05:00:30 PM PDT 24
Peak memory 205252 kb
Host smart-b19536cd-9d16-41d2-b5c4-a7e426568cba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282971785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.4282971785
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.809415543
Short name T359
Test name
Test status
Simulation time 4237077389 ps
CPU time 5.63 seconds
Started Jul 24 05:00:20 PM PDT 24
Finished Jul 24 05:00:26 PM PDT 24
Peak memory 205012 kb
Host smart-0ca4d12e-def2-4ec6-92f7-845dbcfd1037
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809415543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.809415543
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1739889363
Short name T303
Test name
Test status
Simulation time 486171171 ps
CPU time 1.49 seconds
Started Jul 24 05:00:20 PM PDT 24
Finished Jul 24 05:00:21 PM PDT 24
Peak memory 204800 kb
Host smart-2a8b6259-050e-43a8-b523-f6b3656482ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739889363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1739889363
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3768878459
Short name T323
Test name
Test status
Simulation time 3650385011 ps
CPU time 11.35 seconds
Started Jul 24 05:00:15 PM PDT 24
Finished Jul 24 05:00:28 PM PDT 24
Peak memory 204896 kb
Host smart-753b0f5a-9777-46fe-8de0-5d14a5d5fe30
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768878459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3768878459
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1697533353
Short name T338
Test name
Test status
Simulation time 231827111 ps
CPU time 0.91 seconds
Started Jul 24 05:00:19 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 204800 kb
Host smart-36af4acf-7d03-4493-8864-2ad9fbecf4e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697533353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1697533353
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1702569623
Short name T388
Test name
Test status
Simulation time 729412001 ps
CPU time 2.5 seconds
Started Jul 24 05:00:33 PM PDT 24
Finished Jul 24 05:00:36 PM PDT 24
Peak memory 204768 kb
Host smart-eeb23244-e4a1-456d-8507-882e0c8ba862
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702569623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
702569623
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.498312790
Short name T292
Test name
Test status
Simulation time 68801322 ps
CPU time 0.76 seconds
Started Jul 24 05:00:16 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 204736 kb
Host smart-5d1efaa0-7455-4678-9ee1-ecd6fbc04387
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498312790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.498312790
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1209575223
Short name T312
Test name
Test status
Simulation time 48856725 ps
CPU time 0.73 seconds
Started Jul 24 05:00:06 PM PDT 24
Finished Jul 24 05:00:16 PM PDT 24
Peak memory 204780 kb
Host smart-f8a99138-1744-4567-80fd-2fa30855dd4b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209575223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1209575223
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2695077198
Short name T113
Test name
Test status
Simulation time 420876013 ps
CPU time 7.36 seconds
Started Jul 24 05:00:24 PM PDT 24
Finished Jul 24 05:00:31 PM PDT 24
Peak memory 204964 kb
Host smart-7764ad83-5cc3-43c4-a111-394d89c643e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695077198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2695077198
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3716816187
Short name T84
Test name
Test status
Simulation time 41857369171 ps
CPU time 42.22 seconds
Started Jul 24 05:00:28 PM PDT 24
Finished Jul 24 05:01:11 PM PDT 24
Peak memory 221564 kb
Host smart-37b0f283-94b2-494c-b9d1-ad969d5d7638
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716816187 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3716816187
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3039104912
Short name T386
Test name
Test status
Simulation time 659952255 ps
CPU time 4.89 seconds
Started Jul 24 05:00:21 PM PDT 24
Finished Jul 24 05:00:26 PM PDT 24
Peak memory 213352 kb
Host smart-1c08a740-283f-421e-a6f5-d151a4162074
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039104912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3039104912
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3993689242
Short name T347
Test name
Test status
Simulation time 4998700139 ps
CPU time 32.15 seconds
Started Jul 24 05:00:19 PM PDT 24
Finished Jul 24 05:00:52 PM PDT 24
Peak memory 205016 kb
Host smart-11e972ae-b2ac-4e22-a1c0-74455b703500
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993689242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3993689242
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3178685376
Short name T417
Test name
Test status
Simulation time 279487372 ps
CPU time 1.54 seconds
Started Jul 24 05:00:23 PM PDT 24
Finished Jul 24 05:00:25 PM PDT 24
Peak memory 213144 kb
Host smart-cb8ee5da-7c84-48a0-a920-318030e8b880
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178685376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3178685376
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2349033657
Short name T384
Test name
Test status
Simulation time 201341176 ps
CPU time 4.22 seconds
Started Jul 24 05:00:26 PM PDT 24
Finished Jul 24 05:00:30 PM PDT 24
Peak memory 218344 kb
Host smart-62ea39df-d674-448a-b3be-66d99d218f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349033657 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2349033657
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.877464959
Short name T116
Test name
Test status
Simulation time 124133185 ps
CPU time 2.17 seconds
Started Jul 24 05:00:02 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 213164 kb
Host smart-1a6cc4e5-c06d-42e1-8c58-71fa85c12427
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877464959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.877464959
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2150632143
Short name T308
Test name
Test status
Simulation time 118218034988 ps
CPU time 89.56 seconds
Started Jul 24 05:00:10 PM PDT 24
Finished Jul 24 05:01:46 PM PDT 24
Peak memory 204888 kb
Host smart-a36e5c14-57cc-48a1-8577-33561af99075
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150632143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2150632143
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.755653394
Short name T362
Test name
Test status
Simulation time 6673683995 ps
CPU time 16.45 seconds
Started Jul 24 05:00:17 PM PDT 24
Finished Jul 24 05:00:34 PM PDT 24
Peak memory 204984 kb
Host smart-e9aea696-afed-4b87-9bb2-6668e75e5488
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755653394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.755653394
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2801329576
Short name T103
Test name
Test status
Simulation time 9113575599 ps
CPU time 13.27 seconds
Started Jul 24 05:00:31 PM PDT 24
Finished Jul 24 05:00:45 PM PDT 24
Peak memory 205012 kb
Host smart-734c62ac-c037-476c-8ee8-20a8a1863df0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801329576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2801329576
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.522062293
Short name T310
Test name
Test status
Simulation time 11587330680 ps
CPU time 6.68 seconds
Started Jul 24 05:00:21 PM PDT 24
Finished Jul 24 05:00:28 PM PDT 24
Peak memory 205016 kb
Host smart-5725368f-9950-43c0-809c-48be4f7653e7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522062293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.522062293
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.334169270
Short name T430
Test name
Test status
Simulation time 2251696209 ps
CPU time 6.67 seconds
Started Jul 24 05:00:21 PM PDT 24
Finished Jul 24 05:00:28 PM PDT 24
Peak memory 204836 kb
Host smart-41dcc298-0c73-4702-ab7e-a85590e0e89d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334169270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.334169270
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3188309260
Short name T385
Test name
Test status
Simulation time 4504640701 ps
CPU time 14.48 seconds
Started Jul 24 05:00:33 PM PDT 24
Finished Jul 24 05:00:48 PM PDT 24
Peak memory 204872 kb
Host smart-23da576f-fe18-474d-886d-43877af9e551
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188309260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3188309260
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1594031914
Short name T426
Test name
Test status
Simulation time 309423695 ps
CPU time 1.46 seconds
Started Jul 24 05:00:17 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 204684 kb
Host smart-9e2e7ed5-1ea6-4eff-8aad-32bf3dfec1c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594031914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1594031914
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.260977288
Short name T74
Test name
Test status
Simulation time 725980896 ps
CPU time 2.54 seconds
Started Jul 24 05:00:24 PM PDT 24
Finished Jul 24 05:00:27 PM PDT 24
Peak memory 204812 kb
Host smart-cbb5e30a-2c91-46db-b35b-a4f0bfe70dcb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260977288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.260977288
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.246978885
Short name T343
Test name
Test status
Simulation time 117760874 ps
CPU time 0.72 seconds
Started Jul 24 05:00:20 PM PDT 24
Finished Jul 24 05:00:21 PM PDT 24
Peak memory 204572 kb
Host smart-27fae67a-b99a-482e-980c-f66d2eadedf8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246978885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.246978885
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1218006660
Short name T288
Test name
Test status
Simulation time 48144952 ps
CPU time 0.75 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:23 PM PDT 24
Peak memory 204688 kb
Host smart-e738d6a5-2197-42cb-95ce-68e74ff19119
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218006660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1218006660
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3717871035
Short name T435
Test name
Test status
Simulation time 226104182 ps
CPU time 4.05 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:26 PM PDT 24
Peak memory 204948 kb
Host smart-4961b7f8-2470-423a-9b78-350705454a87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717871035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3717871035
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2678315378
Short name T325
Test name
Test status
Simulation time 27879206407 ps
CPU time 19.61 seconds
Started Jul 24 05:00:11 PM PDT 24
Finished Jul 24 05:00:36 PM PDT 24
Peak memory 221152 kb
Host smart-b5ec1a85-e0f2-48ea-84c3-bdbe89dba531
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678315378 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2678315378
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2814349095
Short name T389
Test name
Test status
Simulation time 1656568167 ps
CPU time 5.08 seconds
Started Jul 24 05:00:35 PM PDT 24
Finished Jul 24 05:00:40 PM PDT 24
Peak memory 213240 kb
Host smart-98a0e44b-03b8-4a20-8f88-12ab366e261b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814349095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2814349095
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1594076334
Short name T160
Test name
Test status
Simulation time 2731632367 ps
CPU time 20.81 seconds
Started Jul 24 05:00:17 PM PDT 24
Finished Jul 24 05:00:39 PM PDT 24
Peak memory 213332 kb
Host smart-1b7b64ba-f537-4c80-a799-c1ec3ca74ddc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594076334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1594076334
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2937248636
Short name T318
Test name
Test status
Simulation time 309947775 ps
CPU time 2.92 seconds
Started Jul 24 05:00:34 PM PDT 24
Finished Jul 24 05:00:37 PM PDT 24
Peak memory 213200 kb
Host smart-4b4e53be-61b2-4b53-af50-204f6a0e3d8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937248636 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2937248636
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2311723957
Short name T404
Test name
Test status
Simulation time 244600373 ps
CPU time 1.61 seconds
Started Jul 24 05:00:38 PM PDT 24
Finished Jul 24 05:00:40 PM PDT 24
Peak memory 213164 kb
Host smart-1fa4ceb7-7051-4980-8d74-73b8c18d1a40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311723957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2311723957
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1129809508
Short name T305
Test name
Test status
Simulation time 8055103147 ps
CPU time 22.69 seconds
Started Jul 24 05:00:24 PM PDT 24
Finished Jul 24 05:00:47 PM PDT 24
Peak memory 205028 kb
Host smart-b3a8ef79-b720-40be-adc6-e6647656511c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129809508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.1129809508
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3035793245
Short name T379
Test name
Test status
Simulation time 4908764772 ps
CPU time 2.41 seconds
Started Jul 24 05:00:38 PM PDT 24
Finished Jul 24 05:00:41 PM PDT 24
Peak memory 204936 kb
Host smart-d9a3a0cf-f4dd-4db5-846e-852609d198b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035793245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
035793245
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2342215037
Short name T301
Test name
Test status
Simulation time 129066941 ps
CPU time 0.74 seconds
Started Jul 24 05:00:27 PM PDT 24
Finished Jul 24 05:00:28 PM PDT 24
Peak memory 204812 kb
Host smart-c1327467-eb6e-455e-952a-b34c5b6ee221
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342215037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
342215037
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.501152381
Short name T125
Test name
Test status
Simulation time 261833201 ps
CPU time 3.7 seconds
Started Jul 24 05:00:32 PM PDT 24
Finished Jul 24 05:00:36 PM PDT 24
Peak memory 204900 kb
Host smart-a5644a51-a0c9-4dc1-a44f-1ec15927acec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501152381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.501152381
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3798440063
Short name T365
Test name
Test status
Simulation time 28648999392 ps
CPU time 89.77 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:01:52 PM PDT 24
Peak memory 221428 kb
Host smart-dca068d9-6943-4ff0-b7bb-b0606a4c1f83
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798440063 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3798440063
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2885634120
Short name T86
Test name
Test status
Simulation time 126158423 ps
CPU time 3.01 seconds
Started Jul 24 05:00:48 PM PDT 24
Finished Jul 24 05:00:51 PM PDT 24
Peak memory 213204 kb
Host smart-443af8e3-375c-4881-8542-ae458524a78e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885634120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2885634120
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2621818598
Short name T81
Test name
Test status
Simulation time 4421304204 ps
CPU time 11.45 seconds
Started Jul 24 05:00:33 PM PDT 24
Finished Jul 24 05:00:45 PM PDT 24
Peak memory 213140 kb
Host smart-d20fecd9-dee8-4d30-bcd1-8c79a1493032
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621818598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2621818598
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.50112396
Short name T355
Test name
Test status
Simulation time 207045090 ps
CPU time 2.76 seconds
Started Jul 24 05:00:26 PM PDT 24
Finished Jul 24 05:00:29 PM PDT 24
Peak memory 213192 kb
Host smart-7ed25595-d177-4f58-b8c9-b508bb94dead
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50112396 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.50112396
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1716320717
Short name T420
Test name
Test status
Simulation time 146289425 ps
CPU time 2.22 seconds
Started Jul 24 05:00:33 PM PDT 24
Finished Jul 24 05:00:35 PM PDT 24
Peak memory 213124 kb
Host smart-788f721f-931f-4c0a-bdb0-fa73445c41dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716320717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1716320717
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3310935808
Short name T374
Test name
Test status
Simulation time 23999856379 ps
CPU time 21.09 seconds
Started Jul 24 05:00:31 PM PDT 24
Finished Jul 24 05:00:52 PM PDT 24
Peak memory 204980 kb
Host smart-0d2cbe1c-d5d2-4ca0-9ce3-9b91bbd57e6b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310935808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.3310935808
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3211565244
Short name T289
Test name
Test status
Simulation time 6070873314 ps
CPU time 5.46 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:00:31 PM PDT 24
Peak memory 205016 kb
Host smart-4c0a3911-6b97-48ee-b0db-c4d4c9a90b15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211565244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
211565244
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.753651879
Short name T356
Test name
Test status
Simulation time 761510185 ps
CPU time 1.35 seconds
Started Jul 24 05:00:37 PM PDT 24
Finished Jul 24 05:00:39 PM PDT 24
Peak memory 204800 kb
Host smart-c81a7452-a2fb-4ae9-b1b4-7a3bd70d5052
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753651879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.753651879
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.119216599
Short name T410
Test name
Test status
Simulation time 609526523 ps
CPU time 4.63 seconds
Started Jul 24 05:00:39 PM PDT 24
Finished Jul 24 05:00:44 PM PDT 24
Peak memory 205012 kb
Host smart-a7d62451-84ce-43e4-9395-81e38b1dd1a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119216599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c
sr_outstanding.119216599
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3162914220
Short name T331
Test name
Test status
Simulation time 35880769623 ps
CPU time 167.63 seconds
Started Jul 24 05:00:34 PM PDT 24
Finished Jul 24 05:03:21 PM PDT 24
Peak memory 221496 kb
Host smart-fdcd97b5-2dce-4341-aaca-458b69fe4925
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162914220 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3162914220
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.14647865
Short name T83
Test name
Test status
Simulation time 58297463 ps
CPU time 2.14 seconds
Started Jul 24 05:00:23 PM PDT 24
Finished Jul 24 05:00:25 PM PDT 24
Peak memory 221400 kb
Host smart-10114381-7fc6-42e1-82b6-7d1339cc4218
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14647865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.14647865
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1539721282
Short name T375
Test name
Test status
Simulation time 219445493 ps
CPU time 2.49 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:00:28 PM PDT 24
Peak memory 217884 kb
Host smart-51a5d6f1-b572-4e2b-9441-7b5a1ebecefe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539721282 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1539721282
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2886879237
Short name T124
Test name
Test status
Simulation time 80396760 ps
CPU time 1.44 seconds
Started Jul 24 05:00:28 PM PDT 24
Finished Jul 24 05:00:30 PM PDT 24
Peak memory 213104 kb
Host smart-a5faf9a6-090e-416e-a1eb-c4b2a3b425d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886879237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2886879237
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2328151764
Short name T297
Test name
Test status
Simulation time 40249200643 ps
CPU time 80.49 seconds
Started Jul 24 05:00:34 PM PDT 24
Finished Jul 24 05:02:00 PM PDT 24
Peak memory 205028 kb
Host smart-7899959f-294a-4429-82d8-1d70d8ac0932
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328151764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2328151764
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.98557461
Short name T324
Test name
Test status
Simulation time 4124412693 ps
CPU time 11.22 seconds
Started Jul 24 05:00:33 PM PDT 24
Finished Jul 24 05:00:44 PM PDT 24
Peak memory 204928 kb
Host smart-f7ceb27f-f041-4e87-918c-18a2ab9be27a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98557461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.98557461
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.175400452
Short name T336
Test name
Test status
Simulation time 476874587 ps
CPU time 1.35 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:24 PM PDT 24
Peak memory 204752 kb
Host smart-bc4fb8f1-7000-484c-9b32-6a80ba04065b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175400452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.175400452
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1501846381
Short name T115
Test name
Test status
Simulation time 5087292805 ps
CPU time 8.76 seconds
Started Jul 24 05:00:44 PM PDT 24
Finished Jul 24 05:00:53 PM PDT 24
Peak memory 205008 kb
Host smart-be740802-050b-49d9-ac72-b73a9ed03f02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501846381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1501846381
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3431651285
Short name T378
Test name
Test status
Simulation time 327743524 ps
CPU time 2.84 seconds
Started Jul 24 05:00:36 PM PDT 24
Finished Jul 24 05:00:39 PM PDT 24
Peak memory 213492 kb
Host smart-7ea33981-d530-49cf-8cd1-b28b4a220cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431651285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3431651285
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.166026862
Short name T152
Test name
Test status
Simulation time 3145190330 ps
CPU time 14.61 seconds
Started Jul 24 05:00:45 PM PDT 24
Finished Jul 24 05:01:00 PM PDT 24
Peak memory 213092 kb
Host smart-933f9ae6-6807-4b2d-bf9c-3d3264f07e7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166026862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.166026862
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2265887808
Short name T434
Test name
Test status
Simulation time 98454386 ps
CPU time 2.57 seconds
Started Jul 24 05:00:39 PM PDT 24
Finished Jul 24 05:00:41 PM PDT 24
Peak memory 217772 kb
Host smart-4e4a1f90-d089-4413-9142-4ed09cc59a74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265887808 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2265887808
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.976098591
Short name T104
Test name
Test status
Simulation time 195011784 ps
CPU time 1.56 seconds
Started Jul 24 05:00:24 PM PDT 24
Finished Jul 24 05:00:26 PM PDT 24
Peak memory 213216 kb
Host smart-52526b93-013f-48d2-92df-0f561ef43544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976098591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.976098591
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1769231570
Short name T319
Test name
Test status
Simulation time 8750883476 ps
CPU time 15.3 seconds
Started Jul 24 05:00:26 PM PDT 24
Finished Jul 24 05:00:42 PM PDT 24
Peak memory 204148 kb
Host smart-03305551-2160-493f-a572-297b112171a2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769231570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.1769231570
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1277045277
Short name T427
Test name
Test status
Simulation time 923599427 ps
CPU time 3.27 seconds
Started Jul 24 05:00:40 PM PDT 24
Finished Jul 24 05:00:43 PM PDT 24
Peak memory 204888 kb
Host smart-44d0135f-8ca2-43aa-a7d5-0dfcd17bfb7f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277045277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
277045277
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.4123692194
Short name T403
Test name
Test status
Simulation time 81125614 ps
CPU time 0.85 seconds
Started Jul 24 05:00:40 PM PDT 24
Finished Jul 24 05:00:41 PM PDT 24
Peak memory 204684 kb
Host smart-1e3d335f-ab84-4d63-93f9-53ebb60fc115
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123692194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.4
123692194
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1066450391
Short name T366
Test name
Test status
Simulation time 297555483 ps
CPU time 6.47 seconds
Started Jul 24 05:00:23 PM PDT 24
Finished Jul 24 05:00:29 PM PDT 24
Peak memory 204944 kb
Host smart-3b22c7a2-e76b-4644-9c8c-d4075c6128a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066450391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1066450391
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1785708949
Short name T349
Test name
Test status
Simulation time 69144282661 ps
CPU time 40.36 seconds
Started Jul 24 05:00:34 PM PDT 24
Finished Jul 24 05:01:15 PM PDT 24
Peak memory 221892 kb
Host smart-c55925a7-00d3-495f-8294-ce0e1b86ee8a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785708949 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1785708949
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.137445301
Short name T314
Test name
Test status
Simulation time 892333174 ps
CPU time 3.08 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:00:28 PM PDT 24
Peak memory 213180 kb
Host smart-50e1d449-6a5b-49a1-9d41-19406736369b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137445301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.137445301
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1961376480
Short name T62
Test name
Test status
Simulation time 1485188329 ps
CPU time 11.37 seconds
Started Jul 24 05:00:29 PM PDT 24
Finished Jul 24 05:00:40 PM PDT 24
Peak memory 213168 kb
Host smart-5edfa353-e2c9-43ba-b960-2025e39a93e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961376480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1961376480
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2281883423
Short name T315
Test name
Test status
Simulation time 276401638 ps
CPU time 4.82 seconds
Started Jul 24 05:00:39 PM PDT 24
Finished Jul 24 05:00:44 PM PDT 24
Peak memory 213192 kb
Host smart-c98422be-bf3d-4aa6-99a7-6b341d69d64a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281883423 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2281883423
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3499465806
Short name T313
Test name
Test status
Simulation time 226684496 ps
CPU time 2.13 seconds
Started Jul 24 05:00:27 PM PDT 24
Finished Jul 24 05:00:29 PM PDT 24
Peak memory 213232 kb
Host smart-447d120a-f755-4c5a-94d5-b988b4094787
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499465806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3499465806
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.4087808493
Short name T345
Test name
Test status
Simulation time 62880031087 ps
CPU time 84.89 seconds
Started Jul 24 05:00:38 PM PDT 24
Finished Jul 24 05:02:03 PM PDT 24
Peak memory 204984 kb
Host smart-ae1a5fcd-4f0a-43f3-b5c6-f97e1b1817ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087808493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.4087808493
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3027294909
Short name T393
Test name
Test status
Simulation time 12409276503 ps
CPU time 9.35 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:31 PM PDT 24
Peak memory 204940 kb
Host smart-0d9cc2f6-0149-474c-9c6b-a151a9d65491
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027294909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
027294909
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2045483532
Short name T395
Test name
Test status
Simulation time 457056490 ps
CPU time 1.6 seconds
Started Jul 24 05:00:23 PM PDT 24
Finished Jul 24 05:00:25 PM PDT 24
Peak memory 204732 kb
Host smart-e08fc928-35ff-4d63-8808-ac8623427726
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045483532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
045483532
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3083364499
Short name T367
Test name
Test status
Simulation time 98838561 ps
CPU time 3.71 seconds
Started Jul 24 05:00:43 PM PDT 24
Finished Jul 24 05:00:47 PM PDT 24
Peak memory 204956 kb
Host smart-062852e3-3278-400e-a136-46e19eefd40b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083364499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3083364499
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1642516683
Short name T415
Test name
Test status
Simulation time 35975391405 ps
CPU time 25.53 seconds
Started Jul 24 05:00:26 PM PDT 24
Finished Jul 24 05:00:51 PM PDT 24
Peak memory 213180 kb
Host smart-deaa6ee8-037c-40cf-a88a-dc362a57edfe
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642516683 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.1642516683
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1135403078
Short name T411
Test name
Test status
Simulation time 148631657 ps
CPU time 2.39 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:00:28 PM PDT 24
Peak memory 213220 kb
Host smart-cdeccaed-7acc-42a8-9233-3e719e8508a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135403078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1135403078
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2146326365
Short name T153
Test name
Test status
Simulation time 3804681071 ps
CPU time 12.79 seconds
Started Jul 24 05:00:36 PM PDT 24
Finished Jul 24 05:00:49 PM PDT 24
Peak memory 213212 kb
Host smart-3d4cbb34-e43e-4811-9258-eee40e5d757f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146326365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2146326365
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.212999166
Short name T192
Test name
Test status
Simulation time 70435090 ps
CPU time 0.72 seconds
Started Jul 24 05:04:27 PM PDT 24
Finished Jul 24 05:04:28 PM PDT 24
Peak memory 204840 kb
Host smart-59fab065-c74d-42b5-a70d-3c95e8c3aa7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212999166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.212999166
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2691443089
Short name T182
Test name
Test status
Simulation time 3422799769 ps
CPU time 5.49 seconds
Started Jul 24 05:04:00 PM PDT 24
Finished Jul 24 05:04:06 PM PDT 24
Peak memory 213372 kb
Host smart-37bd1b9d-f114-43b1-b4d4-f43a74684612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691443089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2691443089
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2450122416
Short name T239
Test name
Test status
Simulation time 629544983 ps
CPU time 1.17 seconds
Started Jul 24 05:04:25 PM PDT 24
Finished Jul 24 05:04:27 PM PDT 24
Peak memory 204992 kb
Host smart-52a6a752-423a-4ef4-8b21-6c3e112a19b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450122416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2450122416
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3989178885
Short name T66
Test name
Test status
Simulation time 313871709 ps
CPU time 1.44 seconds
Started Jul 24 05:03:59 PM PDT 24
Finished Jul 24 05:04:00 PM PDT 24
Peak memory 204756 kb
Host smart-513accea-ac33-4d87-9e34-9ba898a7cf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989178885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3989178885
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3535406081
Short name T196
Test name
Test status
Simulation time 1989901474 ps
CPU time 2.35 seconds
Started Jul 24 05:03:57 PM PDT 24
Finished Jul 24 05:04:00 PM PDT 24
Peak memory 205272 kb
Host smart-e1a3921b-7628-4c6d-a6ae-f6eb3b232ecb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3535406081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3535406081
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.322938037
Short name T53
Test name
Test status
Simulation time 528333033 ps
CPU time 0.84 seconds
Started Jul 24 05:03:53 PM PDT 24
Finished Jul 24 05:03:54 PM PDT 24
Peak memory 204844 kb
Host smart-e294e904-75c7-49e6-9ec1-7746bb96c6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322938037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.322938037
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1523203846
Short name T87
Test name
Test status
Simulation time 2105437232 ps
CPU time 5.34 seconds
Started Jul 24 05:03:57 PM PDT 24
Finished Jul 24 05:04:02 PM PDT 24
Peak memory 204828 kb
Host smart-95b72c53-a8e1-4a0d-a769-96e7c9a2b174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523203846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1523203846
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2732264138
Short name T225
Test name
Test status
Simulation time 130882356 ps
CPU time 0.74 seconds
Started Jul 24 05:04:09 PM PDT 24
Finished Jul 24 05:04:10 PM PDT 24
Peak memory 204992 kb
Host smart-b323cd08-9113-4ed2-ae6e-e981ff31c06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732264138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2732264138
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2730804737
Short name T253
Test name
Test status
Simulation time 1224442444 ps
CPU time 3.88 seconds
Started Jul 24 05:04:05 PM PDT 24
Finished Jul 24 05:04:09 PM PDT 24
Peak memory 204768 kb
Host smart-099cd632-2e3f-4a93-a0d1-b059a2e68587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730804737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2730804737
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.260428157
Short name T218
Test name
Test status
Simulation time 2141558430 ps
CPU time 3.93 seconds
Started Jul 24 05:04:40 PM PDT 24
Finished Jul 24 05:04:44 PM PDT 24
Peak memory 204932 kb
Host smart-83cdbc75-67ee-440e-bfe0-a8ad9e739f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260428157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.260428157
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2752141496
Short name T284
Test name
Test status
Simulation time 146724919 ps
CPU time 0.9 seconds
Started Jul 24 05:04:11 PM PDT 24
Finished Jul 24 05:04:12 PM PDT 24
Peak memory 204740 kb
Host smart-f77f5222-1461-4c94-ad94-f9ebee2065cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752141496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2752141496
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3389024202
Short name T166
Test name
Test status
Simulation time 912203352 ps
CPU time 1.5 seconds
Started Jul 24 05:04:07 PM PDT 24
Finished Jul 24 05:04:08 PM PDT 24
Peak memory 204940 kb
Host smart-885e8d3d-7762-44e5-a931-d3e973ce9546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389024202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3389024202
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2295564443
Short name T37
Test name
Test status
Simulation time 1792582069 ps
CPU time 2.25 seconds
Started Jul 24 05:03:56 PM PDT 24
Finished Jul 24 05:03:59 PM PDT 24
Peak memory 205128 kb
Host smart-334d0bb2-250e-4c4d-9f4c-7844a2bb30de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295564443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2295564443
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3684482438
Short name T8
Test name
Test status
Simulation time 217154674 ps
CPU time 1.14 seconds
Started Jul 24 05:04:34 PM PDT 24
Finished Jul 24 05:04:35 PM PDT 24
Peak memory 213164 kb
Host smart-1c752a5a-3163-4afc-85dd-8d0fe0dc8de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684482438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3684482438
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3026577025
Short name T19
Test name
Test status
Simulation time 887792109 ps
CPU time 2.75 seconds
Started Jul 24 05:04:03 PM PDT 24
Finished Jul 24 05:04:06 PM PDT 24
Peak memory 205088 kb
Host smart-839c14cd-e0d0-4f53-88a8-5ff63be480cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026577025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3026577025
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2616424309
Short name T38
Test name
Test status
Simulation time 33147353 ps
CPU time 0.83 seconds
Started Jul 24 05:04:03 PM PDT 24
Finished Jul 24 05:04:04 PM PDT 24
Peak memory 213204 kb
Host smart-2a4a9c5a-1969-43e1-a216-80682f9a0acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616424309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2616424309
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2665020546
Short name T268
Test name
Test status
Simulation time 5214121294 ps
CPU time 7.63 seconds
Started Jul 24 05:04:19 PM PDT 24
Finished Jul 24 05:04:26 PM PDT 24
Peak memory 205428 kb
Host smart-3f490abb-6f0b-4ed7-9a20-97b1164deb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665020546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2665020546
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1996704467
Short name T47
Test name
Test status
Simulation time 2089625582 ps
CPU time 3.69 seconds
Started Jul 24 05:04:19 PM PDT 24
Finished Jul 24 05:04:23 PM PDT 24
Peak memory 229292 kb
Host smart-8ff974ef-b0f1-4072-bb82-fc1eb5715eae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996704467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1996704467
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3466717922
Short name T9
Test name
Test status
Simulation time 2175721027 ps
CPU time 1.83 seconds
Started Jul 24 05:04:06 PM PDT 24
Finished Jul 24 05:04:08 PM PDT 24
Peak memory 204984 kb
Host smart-9a0b6ad5-c75a-46e1-8db1-f830b658465d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466717922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3466717922
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.4286968902
Short name T68
Test name
Test status
Simulation time 5622422298 ps
CPU time 5.43 seconds
Started Jul 24 05:04:09 PM PDT 24
Finished Jul 24 05:04:14 PM PDT 24
Peak memory 205224 kb
Host smart-63108909-7c35-43c8-8adf-ce94180e70de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286968902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.4286968902
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1936442462
Short name T41
Test name
Test status
Simulation time 104769235 ps
CPU time 0.78 seconds
Started Jul 24 05:04:11 PM PDT 24
Finished Jul 24 05:04:12 PM PDT 24
Peak memory 204924 kb
Host smart-a4e48131-123e-49f2-b522-d91edd2eadba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936442462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1936442462
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.956489618
Short name T211
Test name
Test status
Simulation time 123807229 ps
CPU time 0.71 seconds
Started Jul 24 05:04:03 PM PDT 24
Finished Jul 24 05:04:04 PM PDT 24
Peak memory 204796 kb
Host smart-45aae1bd-2e6b-47d7-b085-38d0fe6898cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956489618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.956489618
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3429753765
Short name T264
Test name
Test status
Simulation time 63925597935 ps
CPU time 187.1 seconds
Started Jul 24 05:04:21 PM PDT 24
Finished Jul 24 05:07:28 PM PDT 24
Peak memory 213428 kb
Host smart-d0ef9d37-6377-4658-843a-1ea2ff7a2ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429753765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3429753765
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.3323556581
Short name T26
Test name
Test status
Simulation time 6764297089 ps
CPU time 2.93 seconds
Started Jul 24 05:04:00 PM PDT 24
Finished Jul 24 05:04:03 PM PDT 24
Peak memory 213564 kb
Host smart-61efdff0-8a81-4fbe-8158-4aa3471a605d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323556581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3323556581
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3887304451
Short name T15
Test name
Test status
Simulation time 671029394 ps
CPU time 1.06 seconds
Started Jul 24 05:04:20 PM PDT 24
Finished Jul 24 05:04:22 PM PDT 24
Peak memory 204952 kb
Host smart-9f3491fb-c222-4eab-a4a8-9600294c7918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887304451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3887304451
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2801525309
Short name T42
Test name
Test status
Simulation time 2154141094 ps
CPU time 3.9 seconds
Started Jul 24 05:04:05 PM PDT 24
Finished Jul 24 05:04:09 PM PDT 24
Peak memory 205184 kb
Host smart-3aa2403e-a593-46be-aced-5bbd08d9dff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801525309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2801525309
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.79291846
Short name T35
Test name
Test status
Simulation time 2642205726 ps
CPU time 1.44 seconds
Started Jul 24 05:04:18 PM PDT 24
Finished Jul 24 05:04:19 PM PDT 24
Peak memory 205036 kb
Host smart-eb9f0790-0fb7-414b-a480-d46ef12f5b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79291846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.79291846
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.743607381
Short name T263
Test name
Test status
Simulation time 893319806 ps
CPU time 2.35 seconds
Started Jul 24 05:04:08 PM PDT 24
Finished Jul 24 05:04:11 PM PDT 24
Peak memory 204928 kb
Host smart-82207305-0bd8-4aa4-9985-70015a89c841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743607381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.743607381
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2443212959
Short name T2
Test name
Test status
Simulation time 104333737 ps
CPU time 0.93 seconds
Started Jul 24 05:04:07 PM PDT 24
Finished Jul 24 05:04:09 PM PDT 24
Peak memory 204712 kb
Host smart-09edaece-72cd-437f-8d16-835b24c6a880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443212959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2443212959
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.2875769341
Short name T57
Test name
Test status
Simulation time 84674440 ps
CPU time 0.86 seconds
Started Jul 24 05:04:08 PM PDT 24
Finished Jul 24 05:04:09 PM PDT 24
Peak memory 215096 kb
Host smart-29eca84f-3014-4794-a107-ca5a97b5de10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875769341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2875769341
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1373195190
Short name T246
Test name
Test status
Simulation time 2932980878 ps
CPU time 2.94 seconds
Started Jul 24 05:04:16 PM PDT 24
Finished Jul 24 05:04:19 PM PDT 24
Peak memory 205292 kb
Host smart-771b34b5-feb8-4129-bb6e-bc2444bcef28
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373195190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.1373195190
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.3306945561
Short name T54
Test name
Test status
Simulation time 130322943 ps
CPU time 0.84 seconds
Started Jul 24 05:04:25 PM PDT 24
Finished Jul 24 05:04:26 PM PDT 24
Peak memory 204968 kb
Host smart-b26f61b5-a9f0-47c5-bd81-4a3b08a8b3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306945561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3306945561
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3315128227
Short name T6
Test name
Test status
Simulation time 773698801 ps
CPU time 2.92 seconds
Started Jul 24 05:04:08 PM PDT 24
Finished Jul 24 05:04:12 PM PDT 24
Peak memory 204952 kb
Host smart-d7034347-2e39-446a-b69f-0c049c45279f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315128227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3315128227
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2448240847
Short name T252
Test name
Test status
Simulation time 516614259 ps
CPU time 0.88 seconds
Started Jul 24 05:04:25 PM PDT 24
Finished Jul 24 05:04:26 PM PDT 24
Peak memory 204988 kb
Host smart-20ab1f21-2a32-45a8-9874-a4b68f2c79b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448240847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2448240847
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2678222506
Short name T271
Test name
Test status
Simulation time 161821709 ps
CPU time 0.8 seconds
Started Jul 24 05:04:03 PM PDT 24
Finished Jul 24 05:04:04 PM PDT 24
Peak memory 204716 kb
Host smart-9574ffad-5f02-49ec-9084-36e78d4f03b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678222506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2678222506
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1023795179
Short name T29
Test name
Test status
Simulation time 398509323 ps
CPU time 0.92 seconds
Started Jul 24 05:04:08 PM PDT 24
Finished Jul 24 05:04:09 PM PDT 24
Peak memory 204796 kb
Host smart-2ff0a31d-09e0-4193-9aef-4506a0a6e2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023795179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1023795179
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1592878645
Short name T7
Test name
Test status
Simulation time 735673207 ps
CPU time 1.67 seconds
Started Jul 24 05:04:03 PM PDT 24
Finished Jul 24 05:04:05 PM PDT 24
Peak memory 204960 kb
Host smart-4ead24f8-987f-4af7-a50e-9a44e462efc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592878645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1592878645
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2873550394
Short name T228
Test name
Test status
Simulation time 202586953 ps
CPU time 0.78 seconds
Started Jul 24 05:04:11 PM PDT 24
Finished Jul 24 05:04:12 PM PDT 24
Peak memory 204976 kb
Host smart-12063e6f-e2fe-4f33-a7f1-c2471c8aae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873550394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2873550394
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.4211525388
Short name T164
Test name
Test status
Simulation time 550301368 ps
CPU time 1.42 seconds
Started Jul 24 05:04:16 PM PDT 24
Finished Jul 24 05:04:18 PM PDT 24
Peak memory 204988 kb
Host smart-0767e489-b490-405b-b816-bdc23856a1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211525388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.4211525388
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2017401586
Short name T188
Test name
Test status
Simulation time 7069692514 ps
CPU time 10.39 seconds
Started Jul 24 05:04:04 PM PDT 24
Finished Jul 24 05:04:15 PM PDT 24
Peak memory 205252 kb
Host smart-3850703b-4085-4b23-9ac2-969c221bb3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017401586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2017401586
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.354737505
Short name T222
Test name
Test status
Simulation time 317341906 ps
CPU time 1.09 seconds
Started Jul 24 05:04:04 PM PDT 24
Finished Jul 24 05:04:05 PM PDT 24
Peak memory 213036 kb
Host smart-a166d832-41d5-4334-8841-6fb1c9d8f61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354737505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.354737505
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1054101667
Short name T45
Test name
Test status
Simulation time 339614917 ps
CPU time 0.95 seconds
Started Jul 24 05:04:07 PM PDT 24
Finished Jul 24 05:04:09 PM PDT 24
Peak memory 204904 kb
Host smart-a5412b6f-495b-4ad5-ad1a-f00a54ea5e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054101667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1054101667
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2676505140
Short name T77
Test name
Test status
Simulation time 3707480237 ps
CPU time 4.57 seconds
Started Jul 24 05:04:10 PM PDT 24
Finished Jul 24 05:04:14 PM PDT 24
Peak memory 205188 kb
Host smart-065ff860-fae6-4acb-bc0b-1811cd922c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676505140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2676505140
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.4253175038
Short name T245
Test name
Test status
Simulation time 1696381371 ps
CPU time 4.7 seconds
Started Jul 24 05:04:16 PM PDT 24
Finished Jul 24 05:04:21 PM PDT 24
Peak memory 205128 kb
Host smart-dfcc6376-0440-48c9-b161-7b67041e5e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253175038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.4253175038
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2308408099
Short name T274
Test name
Test status
Simulation time 2143547831 ps
CPU time 2.81 seconds
Started Jul 24 05:04:06 PM PDT 24
Finished Jul 24 05:04:09 PM PDT 24
Peak memory 204860 kb
Host smart-29357401-2f19-43d0-b123-2c31c5c392a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308408099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2308408099
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.1559288119
Short name T58
Test name
Test status
Simulation time 7967525847 ps
CPU time 20.55 seconds
Started Jul 24 05:04:04 PM PDT 24
Finished Jul 24 05:04:25 PM PDT 24
Peak memory 213392 kb
Host smart-8919046e-5666-430a-b9cc-7ac3ad53879b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559288119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1559288119
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.740532756
Short name T197
Test name
Test status
Simulation time 75718086 ps
CPU time 0.74 seconds
Started Jul 24 05:04:17 PM PDT 24
Finished Jul 24 05:04:18 PM PDT 24
Peak memory 204940 kb
Host smart-e030dac1-e8ef-4bd6-861d-86c57615a0e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740532756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.740532756
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.814609551
Short name T183
Test name
Test status
Simulation time 1761271876 ps
CPU time 5.84 seconds
Started Jul 24 05:04:35 PM PDT 24
Finished Jul 24 05:04:41 PM PDT 24
Peak memory 213368 kb
Host smart-51e5a18d-130b-490c-a83b-eaaf22ad4d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814609551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.814609551
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1100290699
Short name T98
Test name
Test status
Simulation time 15532962618 ps
CPU time 25.5 seconds
Started Jul 24 05:04:09 PM PDT 24
Finished Jul 24 05:04:34 PM PDT 24
Peak memory 213760 kb
Host smart-e96318ec-8270-47ec-9d1f-e2e66a27abac
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1100290699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1100290699
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.2470313747
Short name T80
Test name
Test status
Simulation time 2922366670 ps
CPU time 7.94 seconds
Started Jul 24 05:04:10 PM PDT 24
Finished Jul 24 05:04:18 PM PDT 24
Peak memory 205568 kb
Host smart-cc61228d-6029-4b84-9640-5b43e1f3efde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470313747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2470313747
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.3301735896
Short name T16
Test name
Test status
Simulation time 2420506048 ps
CPU time 2.06 seconds
Started Jul 24 05:04:16 PM PDT 24
Finished Jul 24 05:04:19 PM PDT 24
Peak memory 213272 kb
Host smart-40228365-968e-45b5-b407-67b482c22257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301735896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3301735896
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1679296573
Short name T207
Test name
Test status
Simulation time 142260963 ps
CPU time 1.01 seconds
Started Jul 24 05:04:22 PM PDT 24
Finished Jul 24 05:04:23 PM PDT 24
Peak memory 204844 kb
Host smart-26bc83ff-9fb0-46bc-aef7-5362fd0b7262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679296573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1679296573
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1536618461
Short name T132
Test name
Test status
Simulation time 81074287521 ps
CPU time 150.09 seconds
Started Jul 24 05:04:19 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 213636 kb
Host smart-f88e090e-1460-44c1-b11b-8653082f6b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536618461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1536618461
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1967537990
Short name T79
Test name
Test status
Simulation time 9795749832 ps
CPU time 15.11 seconds
Started Jul 24 05:04:44 PM PDT 24
Finished Jul 24 05:04:59 PM PDT 24
Peak memory 213620 kb
Host smart-c0810273-a6c9-48f2-b275-c7ecbcd55c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967537990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1967537990
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3074863384
Short name T235
Test name
Test status
Simulation time 5316752947 ps
CPU time 3.87 seconds
Started Jul 24 05:04:14 PM PDT 24
Finished Jul 24 05:04:18 PM PDT 24
Peak memory 205192 kb
Host smart-7e3b17aa-42f8-4b79-89d4-168d2919de94
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3074863384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3074863384
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1015990820
Short name T143
Test name
Test status
Simulation time 1765960159 ps
CPU time 5.97 seconds
Started Jul 24 05:04:44 PM PDT 24
Finished Jul 24 05:04:50 PM PDT 24
Peak memory 205340 kb
Host smart-010fd5b6-04f5-4b1b-9e7a-fe451c8d9a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015990820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1015990820
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.4055773896
Short name T60
Test name
Test status
Simulation time 5640539615 ps
CPU time 7.93 seconds
Started Jul 24 05:04:26 PM PDT 24
Finished Jul 24 05:04:34 PM PDT 24
Peak memory 205252 kb
Host smart-71635310-45e5-4e14-a05b-11df09a0503a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055773896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.4055773896
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1221022220
Short name T257
Test name
Test status
Simulation time 196782405 ps
CPU time 0.86 seconds
Started Jul 24 05:04:07 PM PDT 24
Finished Jul 24 05:04:09 PM PDT 24
Peak memory 205060 kb
Host smart-04213948-cee7-4538-9f2e-92a2165ae4f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221022220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1221022220
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3731745738
Short name T202
Test name
Test status
Simulation time 13045873925 ps
CPU time 31.66 seconds
Started Jul 24 05:04:47 PM PDT 24
Finished Jul 24 05:05:19 PM PDT 24
Peak memory 215992 kb
Host smart-6928a65a-5f61-409a-b616-7e6bc1591d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731745738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3731745738
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3316678210
Short name T242
Test name
Test status
Simulation time 9168375831 ps
CPU time 3.83 seconds
Started Jul 24 05:04:14 PM PDT 24
Finished Jul 24 05:04:18 PM PDT 24
Peak memory 213504 kb
Host smart-9194722e-4e5f-4b7e-a0e3-a48348abf042
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316678210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3316678210
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3009665832
Short name T186
Test name
Test status
Simulation time 4518309975 ps
CPU time 13.06 seconds
Started Jul 24 05:04:09 PM PDT 24
Finished Jul 24 05:04:23 PM PDT 24
Peak memory 213452 kb
Host smart-46d5dc12-46ff-420f-a25e-ee3dc9670ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009665832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3009665832
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3157709536
Short name T278
Test name
Test status
Simulation time 111387023 ps
CPU time 0.87 seconds
Started Jul 24 05:04:20 PM PDT 24
Finished Jul 24 05:04:21 PM PDT 24
Peak memory 204904 kb
Host smart-6709bddd-7756-4cc0-b0f9-1a5323bb611d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157709536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3157709536
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2465593493
Short name T138
Test name
Test status
Simulation time 99415203264 ps
CPU time 112.48 seconds
Started Jul 24 05:04:32 PM PDT 24
Finished Jul 24 05:06:25 PM PDT 24
Peak memory 221652 kb
Host smart-ecfe90c6-755c-48bc-9778-e15b37c8a873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465593493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2465593493
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2702540308
Short name T214
Test name
Test status
Simulation time 4974490705 ps
CPU time 12.47 seconds
Started Jul 24 05:04:22 PM PDT 24
Finished Jul 24 05:04:34 PM PDT 24
Peak memory 213536 kb
Host smart-ee208814-970b-41d0-9597-2f085fce75e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702540308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2702540308
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1834579504
Short name T250
Test name
Test status
Simulation time 807863738 ps
CPU time 1.87 seconds
Started Jul 24 05:04:29 PM PDT 24
Finished Jul 24 05:04:31 PM PDT 24
Peak memory 205336 kb
Host smart-4cd1efdd-eea3-4c2a-86ee-da4d621a3f27
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1834579504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1834579504
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1285154431
Short name T212
Test name
Test status
Simulation time 2580124625 ps
CPU time 4.54 seconds
Started Jul 24 05:04:44 PM PDT 24
Finished Jul 24 05:04:49 PM PDT 24
Peak memory 205404 kb
Host smart-7efa1fa3-db56-47ec-bd8e-d210f2a1903e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285154431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1285154431
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.3032366957
Short name T23
Test name
Test status
Simulation time 6365919399 ps
CPU time 10.96 seconds
Started Jul 24 05:04:30 PM PDT 24
Finished Jul 24 05:04:41 PM PDT 24
Peak memory 213444 kb
Host smart-59bd320b-c7c7-4e99-b0d8-28bd121b1df7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032366957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3032366957
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2062694647
Short name T224
Test name
Test status
Simulation time 132475792 ps
CPU time 1.01 seconds
Started Jul 24 05:05:24 PM PDT 24
Finished Jul 24 05:05:25 PM PDT 24
Peak memory 204764 kb
Host smart-59480602-da9a-4cf9-930b-259e9f1e3461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062694647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2062694647
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3861449582
Short name T203
Test name
Test status
Simulation time 22460779262 ps
CPU time 23.52 seconds
Started Jul 24 05:04:16 PM PDT 24
Finished Jul 24 05:04:39 PM PDT 24
Peak memory 213640 kb
Host smart-770787dc-ab08-4b4b-b3e2-397fc696cf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861449582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3861449582
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4021041365
Short name T206
Test name
Test status
Simulation time 2408535078 ps
CPU time 4.41 seconds
Started Jul 24 05:04:23 PM PDT 24
Finished Jul 24 05:04:28 PM PDT 24
Peak memory 205372 kb
Host smart-cd451575-0eaf-4aae-aba8-3fc26e3eae5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021041365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4021041365
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3205850234
Short name T262
Test name
Test status
Simulation time 1107390155 ps
CPU time 3.72 seconds
Started Jul 24 05:04:40 PM PDT 24
Finished Jul 24 05:04:44 PM PDT 24
Peak memory 205456 kb
Host smart-7c1cc548-498d-4bc8-832e-02c7b2a08f94
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205850234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3205850234
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1685112412
Short name T276
Test name
Test status
Simulation time 1490609737 ps
CPU time 4.92 seconds
Started Jul 24 05:04:33 PM PDT 24
Finished Jul 24 05:04:43 PM PDT 24
Peak memory 205180 kb
Host smart-2f48902d-1f57-43d0-aa4c-733d0f85c7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685112412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1685112412
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.2210523722
Short name T163
Test name
Test status
Simulation time 3091255648 ps
CPU time 2.99 seconds
Started Jul 24 05:04:58 PM PDT 24
Finished Jul 24 05:05:02 PM PDT 24
Peak memory 212408 kb
Host smart-860e11b6-94f5-413d-9865-7fd262d53cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210523722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2210523722
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3739655097
Short name T178
Test name
Test status
Simulation time 145001460 ps
CPU time 1.07 seconds
Started Jul 24 05:05:23 PM PDT 24
Finished Jul 24 05:05:29 PM PDT 24
Peak memory 204764 kb
Host smart-27c7ee06-a769-407b-b272-0a11cbeafcfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739655097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3739655097
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3205490221
Short name T205
Test name
Test status
Simulation time 8779384772 ps
CPU time 6.94 seconds
Started Jul 24 05:04:22 PM PDT 24
Finished Jul 24 05:04:29 PM PDT 24
Peak memory 213572 kb
Host smart-889719aa-a0eb-4e88-810f-c1de3c4f6985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205490221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3205490221
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.4104481629
Short name T251
Test name
Test status
Simulation time 4345737549 ps
CPU time 3.85 seconds
Started Jul 24 05:04:16 PM PDT 24
Finished Jul 24 05:04:25 PM PDT 24
Peak memory 213444 kb
Host smart-69179a6f-3c4b-453f-a5f2-6591a95027a1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104481629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.4104481629
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.4259483416
Short name T254
Test name
Test status
Simulation time 2655305739 ps
CPU time 1.42 seconds
Started Jul 24 05:05:40 PM PDT 24
Finished Jul 24 05:05:42 PM PDT 24
Peak memory 213356 kb
Host smart-fcd72349-a727-42fe-8a23-e9be1d75689c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259483416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.4259483416
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1350477219
Short name T184
Test name
Test status
Simulation time 135707894 ps
CPU time 0.76 seconds
Started Jul 24 05:04:32 PM PDT 24
Finished Jul 24 05:04:33 PM PDT 24
Peak memory 205040 kb
Host smart-054195d6-581a-4463-97ed-a585f80132dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350477219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1350477219
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1680073164
Short name T174
Test name
Test status
Simulation time 30801492105 ps
CPU time 80.38 seconds
Started Jul 24 05:04:44 PM PDT 24
Finished Jul 24 05:06:04 PM PDT 24
Peak memory 213492 kb
Host smart-5fe39269-9659-45e0-a3f6-7c72d61f75a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680073164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1680073164
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3706195587
Short name T270
Test name
Test status
Simulation time 14436545461 ps
CPU time 38.81 seconds
Started Jul 24 05:04:22 PM PDT 24
Finished Jul 24 05:05:01 PM PDT 24
Peak memory 213620 kb
Host smart-c801a404-5690-4d6e-bf66-3c9eb163c6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706195587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3706195587
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.436826077
Short name T141
Test name
Test status
Simulation time 2078169048 ps
CPU time 3.91 seconds
Started Jul 24 05:04:44 PM PDT 24
Finished Jul 24 05:04:49 PM PDT 24
Peak memory 205136 kb
Host smart-9ae7045c-8f30-4987-80c8-1287b13fb1f9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=436826077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.436826077
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.4021298794
Short name T237
Test name
Test status
Simulation time 3353577212 ps
CPU time 2.45 seconds
Started Jul 24 05:04:29 PM PDT 24
Finished Jul 24 05:04:32 PM PDT 24
Peak memory 213640 kb
Host smart-3f40b8f1-15d0-45ba-bcd3-ad45ac50f742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021298794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.4021298794
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3787704633
Short name T191
Test name
Test status
Simulation time 76914269 ps
CPU time 0.81 seconds
Started Jul 24 05:05:33 PM PDT 24
Finished Jul 24 05:05:34 PM PDT 24
Peak memory 204764 kb
Host smart-b357a81d-af25-46ae-a87f-68aa82db33cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787704633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3787704633
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1259240797
Short name T215
Test name
Test status
Simulation time 1732252430 ps
CPU time 1.76 seconds
Started Jul 24 05:04:15 PM PDT 24
Finished Jul 24 05:04:17 PM PDT 24
Peak memory 214492 kb
Host smart-479195c2-1dcd-4a09-bf1e-da4089ec463a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259240797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1259240797
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1117761084
Short name T234
Test name
Test status
Simulation time 6268000386 ps
CPU time 8.49 seconds
Started Jul 24 05:05:40 PM PDT 24
Finished Jul 24 05:05:48 PM PDT 24
Peak memory 213284 kb
Host smart-11d1815b-9ce9-4a6e-9e59-d161aaf4d756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117761084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1117761084
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2322720614
Short name T272
Test name
Test status
Simulation time 1385796295 ps
CPU time 2.17 seconds
Started Jul 24 05:04:26 PM PDT 24
Finished Jul 24 05:04:29 PM PDT 24
Peak memory 205340 kb
Host smart-e168790e-5abb-4d45-b610-d55988bdf83d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322720614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.2322720614
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3542545227
Short name T247
Test name
Test status
Simulation time 12767489837 ps
CPU time 7.52 seconds
Started Jul 24 05:04:28 PM PDT 24
Finished Jul 24 05:04:36 PM PDT 24
Peak memory 213596 kb
Host smart-c3475a25-4456-45dd-a416-9244ed851d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542545227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3542545227
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.3049931766
Short name T136
Test name
Test status
Simulation time 14096606727 ps
CPU time 10.71 seconds
Started Jul 24 05:04:37 PM PDT 24
Finished Jul 24 05:04:47 PM PDT 24
Peak memory 213224 kb
Host smart-3c1cf8f1-ef9a-4e80-96b6-5b092bfe35c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049931766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3049931766
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3994318116
Short name T128
Test name
Test status
Simulation time 85650351 ps
CPU time 0.83 seconds
Started Jul 24 05:04:36 PM PDT 24
Finished Jul 24 05:04:37 PM PDT 24
Peak memory 204844 kb
Host smart-bf02fea8-1fff-4940-abde-ee39a31db6d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994318116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3994318116
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2889393468
Short name T279
Test name
Test status
Simulation time 1555764182 ps
CPU time 2.02 seconds
Started Jul 24 05:04:19 PM PDT 24
Finished Jul 24 05:04:22 PM PDT 24
Peak memory 213312 kb
Host smart-ade255da-4ddf-4926-863f-384d12fb80c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889393468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2889393468
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.460825362
Short name T175
Test name
Test status
Simulation time 681091879 ps
CPU time 2.67 seconds
Started Jul 24 05:05:25 PM PDT 24
Finished Jul 24 05:05:28 PM PDT 24
Peak memory 205028 kb
Host smart-5f7ed2b5-fe35-46dc-a32c-4be6b9b3ebe8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=460825362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.460825362
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3111496662
Short name T286
Test name
Test status
Simulation time 4280358285 ps
CPU time 4.56 seconds
Started Jul 24 05:04:31 PM PDT 24
Finished Jul 24 05:04:36 PM PDT 24
Peak memory 205260 kb
Host smart-291d9a80-98db-459c-be78-977a4487cd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111496662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3111496662
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2070032465
Short name T139
Test name
Test status
Simulation time 4631159068 ps
CPU time 7.98 seconds
Started Jul 24 05:04:21 PM PDT 24
Finished Jul 24 05:04:29 PM PDT 24
Peak memory 213424 kb
Host smart-5c111ef5-424a-4ca9-a13d-9ff4739e9d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070032465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2070032465
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3348961576
Short name T227
Test name
Test status
Simulation time 48490583 ps
CPU time 0.69 seconds
Started Jul 24 05:04:07 PM PDT 24
Finished Jul 24 05:04:08 PM PDT 24
Peak memory 205152 kb
Host smart-2dba153c-7b0d-45a3-956c-4345838e9033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348961576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3348961576
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1652546186
Short name T217
Test name
Test status
Simulation time 7017771323 ps
CPU time 22.47 seconds
Started Jul 24 05:04:25 PM PDT 24
Finished Jul 24 05:04:48 PM PDT 24
Peak memory 213636 kb
Host smart-283f10c8-0a5d-48b1-bb79-b6fa65d91a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652546186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1652546186
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3271749516
Short name T177
Test name
Test status
Simulation time 2417670015 ps
CPU time 2.14 seconds
Started Jul 24 05:04:33 PM PDT 24
Finished Jul 24 05:04:35 PM PDT 24
Peak memory 213672 kb
Host smart-ef1bb1db-495a-4306-8077-bce9c090e514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271749516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3271749516
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1701230687
Short name T198
Test name
Test status
Simulation time 3187625306 ps
CPU time 5.86 seconds
Started Jul 24 05:04:38 PM PDT 24
Finished Jul 24 05:04:44 PM PDT 24
Peak memory 213540 kb
Host smart-ecb67780-6002-40b8-869e-8495b9cc6c37
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1701230687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1701230687
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.1343906509
Short name T220
Test name
Test status
Simulation time 3767086921 ps
CPU time 6.24 seconds
Started Jul 24 05:04:17 PM PDT 24
Finished Jul 24 05:04:23 PM PDT 24
Peak memory 205392 kb
Host smart-5410ccd9-b7c0-4c1a-85c0-854ee9c335b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343906509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1343906509
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.311852007
Short name T172
Test name
Test status
Simulation time 62795068 ps
CPU time 0.73 seconds
Started Jul 24 05:04:35 PM PDT 24
Finished Jul 24 05:04:36 PM PDT 24
Peak memory 205044 kb
Host smart-e81b751b-c3e5-47bb-aa26-0c25c45cceae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311852007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.311852007
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.242072483
Short name T280
Test name
Test status
Simulation time 28304126045 ps
CPU time 71.6 seconds
Started Jul 24 05:04:13 PM PDT 24
Finished Jul 24 05:05:25 PM PDT 24
Peak memory 213408 kb
Host smart-2414186f-67bc-4a2f-bafc-0513725c8c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242072483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.242072483
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.894957707
Short name T244
Test name
Test status
Simulation time 1721348434 ps
CPU time 2.01 seconds
Started Jul 24 05:04:10 PM PDT 24
Finished Jul 24 05:04:12 PM PDT 24
Peak memory 213384 kb
Host smart-26c09893-f00e-498e-a199-6b9a3cb3c955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894957707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.894957707
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3729318606
Short name T219
Test name
Test status
Simulation time 9263788552 ps
CPU time 25.03 seconds
Started Jul 24 05:04:06 PM PDT 24
Finished Jul 24 05:04:31 PM PDT 24
Peak memory 213484 kb
Host smart-588439c1-3974-44d5-9a26-b79d38c7133d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729318606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3729318606
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.531739534
Short name T221
Test name
Test status
Simulation time 135508636 ps
CPU time 0.75 seconds
Started Jul 24 05:04:25 PM PDT 24
Finished Jul 24 05:04:26 PM PDT 24
Peak memory 205120 kb
Host smart-70177a2b-53ba-4042-9451-1a3f67e15836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531739534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.531739534
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.203173904
Short name T144
Test name
Test status
Simulation time 1942394153 ps
CPU time 2.54 seconds
Started Jul 24 05:04:15 PM PDT 24
Finished Jul 24 05:04:18 PM PDT 24
Peak memory 205304 kb
Host smart-7dc2edda-7da7-43c7-944b-0460eaf02821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203173904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.203173904
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.220627567
Short name T70
Test name
Test status
Simulation time 353637430 ps
CPU time 1.13 seconds
Started Jul 24 05:03:59 PM PDT 24
Finished Jul 24 05:04:01 PM PDT 24
Peak memory 228652 kb
Host smart-bac4a7d0-7afd-493d-8f0d-cc6ac2cfdc16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220627567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.220627567
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.4170378861
Short name T142
Test name
Test status
Simulation time 3915857655 ps
CPU time 11.44 seconds
Started Jul 24 05:04:17 PM PDT 24
Finished Jul 24 05:04:28 PM PDT 24
Peak memory 213392 kb
Host smart-e9c773bf-d350-4cd2-9ac8-300433efeb0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170378861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.4170378861
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1296200136
Short name T259
Test name
Test status
Simulation time 116569323 ps
CPU time 0.97 seconds
Started Jul 24 05:04:14 PM PDT 24
Finished Jul 24 05:04:15 PM PDT 24
Peak memory 205032 kb
Host smart-05e90897-11de-49b7-8399-074d4ca07659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296200136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1296200136
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2731671197
Short name T231
Test name
Test status
Simulation time 54923737 ps
CPU time 0.7 seconds
Started Jul 24 05:04:26 PM PDT 24
Finished Jul 24 05:04:27 PM PDT 24
Peak memory 205036 kb
Host smart-0316500b-4693-40f3-8ca8-33bdd447e047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731671197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2731671197
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2310177216
Short name T243
Test name
Test status
Simulation time 85901431 ps
CPU time 0.73 seconds
Started Jul 24 05:04:24 PM PDT 24
Finished Jul 24 05:04:24 PM PDT 24
Peak memory 204944 kb
Host smart-391fdaf3-e250-48b0-aacf-d2b4be81ddcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310177216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2310177216
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.1206466660
Short name T216
Test name
Test status
Simulation time 6818433392 ps
CPU time 19.37 seconds
Started Jul 24 05:04:41 PM PDT 24
Finished Jul 24 05:05:00 PM PDT 24
Peak memory 205164 kb
Host smart-c3775c0c-dc0a-49ae-b644-0773ce1b2b61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206466660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1206466660
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3195480233
Short name T67
Test name
Test status
Simulation time 191579365 ps
CPU time 0.77 seconds
Started Jul 24 05:04:42 PM PDT 24
Finished Jul 24 05:04:48 PM PDT 24
Peak memory 205000 kb
Host smart-f82e6534-9b26-4d38-b4bd-8d5e7a4ba1d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195480233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3195480233
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1326336536
Short name T194
Test name
Test status
Simulation time 101235727 ps
CPU time 0.74 seconds
Started Jul 24 05:04:19 PM PDT 24
Finished Jul 24 05:04:20 PM PDT 24
Peak memory 204980 kb
Host smart-566be632-5aa6-47e8-8a7f-fa2ec94f1d3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326336536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1326336536
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.3440459178
Short name T168
Test name
Test status
Simulation time 3495233228 ps
CPU time 2.88 seconds
Started Jul 24 05:04:59 PM PDT 24
Finished Jul 24 05:05:03 PM PDT 24
Peak memory 212396 kb
Host smart-32e8d4a9-cc5c-42b8-815e-9b097c323b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440459178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.3440459178
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3018177061
Short name T269
Test name
Test status
Simulation time 46394931 ps
CPU time 0.66 seconds
Started Jul 24 05:05:18 PM PDT 24
Finished Jul 24 05:05:24 PM PDT 24
Peak memory 204696 kb
Host smart-ef12f3c1-c420-4e67-866b-ae8fbc3526db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018177061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3018177061
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.482793884
Short name T189
Test name
Test status
Simulation time 160653190 ps
CPU time 0.76 seconds
Started Jul 24 05:04:29 PM PDT 24
Finished Jul 24 05:04:30 PM PDT 24
Peak memory 205044 kb
Host smart-db9ef091-fc21-4d93-b1e5-1e98f12d69d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482793884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.482793884
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2747121321
Short name T226
Test name
Test status
Simulation time 38837768 ps
CPU time 0.75 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:04:53 PM PDT 24
Peak memory 205032 kb
Host smart-2bfcb874-add3-4121-82c5-eca4efb6fc0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747121321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2747121321
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2263471028
Short name T179
Test name
Test status
Simulation time 38606402 ps
CPU time 0.75 seconds
Started Jul 24 05:04:32 PM PDT 24
Finished Jul 24 05:04:33 PM PDT 24
Peak memory 205016 kb
Host smart-4cd0f9b6-81cf-4b4e-aeb4-7685e00d511a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263471028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2263471028
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1591401948
Short name T204
Test name
Test status
Simulation time 167668859 ps
CPU time 0.71 seconds
Started Jul 24 05:04:32 PM PDT 24
Finished Jul 24 05:04:33 PM PDT 24
Peak memory 204840 kb
Host smart-09050206-1dce-4e6f-9074-f206a1dc972f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591401948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1591401948
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.252290108
Short name T165
Test name
Test status
Simulation time 6565668402 ps
CPU time 10.84 seconds
Started Jul 24 05:05:40 PM PDT 24
Finished Jul 24 05:05:51 PM PDT 24
Peak memory 204920 kb
Host smart-fe418e4f-238d-4c9d-844f-cdbe98f9e8a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252290108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.252290108
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3940325391
Short name T181
Test name
Test status
Simulation time 124309146 ps
CPU time 0.86 seconds
Started Jul 24 05:04:30 PM PDT 24
Finished Jul 24 05:04:31 PM PDT 24
Peak memory 205020 kb
Host smart-fce12844-de4c-4c21-98d9-af471e5bd7c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940325391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3940325391
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3523275121
Short name T230
Test name
Test status
Simulation time 8960730771 ps
CPU time 8.23 seconds
Started Jul 24 05:04:41 PM PDT 24
Finished Jul 24 05:04:49 PM PDT 24
Peak memory 213392 kb
Host smart-cb15fcf8-b430-434e-b1de-8872c2670c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523275121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3523275121
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3019082990
Short name T229
Test name
Test status
Simulation time 14962628758 ps
CPU time 6.56 seconds
Started Jul 24 05:04:19 PM PDT 24
Finished Jul 24 05:04:26 PM PDT 24
Peak memory 213372 kb
Host smart-32a7737a-b5bb-4e69-9201-e3ff33c332ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019082990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3019082990
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1713214123
Short name T275
Test name
Test status
Simulation time 6843549016 ps
CPU time 6.4 seconds
Started Jul 24 05:04:32 PM PDT 24
Finished Jul 24 05:04:39 PM PDT 24
Peak memory 213548 kb
Host smart-edece08f-8efd-4fb3-a363-64061e34ff0c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713214123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1713214123
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1944913939
Short name T273
Test name
Test status
Simulation time 149242964 ps
CPU time 0.83 seconds
Started Jul 24 05:04:11 PM PDT 24
Finished Jul 24 05:04:17 PM PDT 24
Peak memory 204936 kb
Host smart-69926230-33a2-4cd1-a707-2a06b6b1e278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944913939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1944913939
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3549854547
Short name T287
Test name
Test status
Simulation time 823382209 ps
CPU time 3.13 seconds
Started Jul 24 05:04:10 PM PDT 24
Finished Jul 24 05:04:14 PM PDT 24
Peak memory 205268 kb
Host smart-ea8aa716-c7c0-4f90-97dc-5cb782c30460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549854547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3549854547
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3280724816
Short name T51
Test name
Test status
Simulation time 2001885035 ps
CPU time 2.49 seconds
Started Jul 24 05:04:16 PM PDT 24
Finished Jul 24 05:04:19 PM PDT 24
Peak memory 229044 kb
Host smart-e9ad0c41-bb5c-47fc-bc47-9e1147af1142
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280724816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3280724816
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.1344623800
Short name T25
Test name
Test status
Simulation time 4070911064 ps
CPU time 6.47 seconds
Started Jul 24 05:04:14 PM PDT 24
Finished Jul 24 05:04:21 PM PDT 24
Peak memory 204608 kb
Host smart-f1524389-8bf1-440f-a9dd-b4e93bb94c00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344623800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1344623800
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3936303023
Short name T170
Test name
Test status
Simulation time 59144948 ps
CPU time 0.78 seconds
Started Jul 24 05:05:16 PM PDT 24
Finished Jul 24 05:05:17 PM PDT 24
Peak memory 204764 kb
Host smart-064bbf82-68b6-44f9-8b08-836be2c54d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936303023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3936303023
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3960828254
Short name T281
Test name
Test status
Simulation time 49120441 ps
CPU time 0.78 seconds
Started Jul 24 05:04:16 PM PDT 24
Finished Jul 24 05:04:16 PM PDT 24
Peak memory 204988 kb
Host smart-4bcf2e8d-311c-4e8c-8f91-733ed3964cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960828254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3960828254
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.78385770
Short name T145
Test name
Test status
Simulation time 5919179000 ps
CPU time 2.7 seconds
Started Jul 24 05:04:30 PM PDT 24
Finished Jul 24 05:04:33 PM PDT 24
Peak memory 213372 kb
Host smart-95d44b0d-20d5-4bdc-a524-bc8c09fdc3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78385770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.78385770
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3107185432
Short name T48
Test name
Test status
Simulation time 30634849 ps
CPU time 0.74 seconds
Started Jul 24 05:04:30 PM PDT 24
Finished Jul 24 05:04:31 PM PDT 24
Peak memory 205004 kb
Host smart-98108b98-2cc4-4ed2-8532-37e7aea9b5a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107185432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3107185432
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.1664039085
Short name T134
Test name
Test status
Simulation time 4734540664 ps
CPU time 2.54 seconds
Started Jul 24 05:04:23 PM PDT 24
Finished Jul 24 05:04:26 PM PDT 24
Peak memory 213304 kb
Host smart-ff3bf763-42f4-460d-ac60-c35f83331b88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664039085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1664039085
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1834775126
Short name T190
Test name
Test status
Simulation time 35696348 ps
CPU time 0.79 seconds
Started Jul 24 05:04:42 PM PDT 24
Finished Jul 24 05:04:44 PM PDT 24
Peak memory 204940 kb
Host smart-7870abe1-f7ee-477d-910e-b177fcae6083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834775126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1834775126
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.1109140160
Short name T21
Test name
Test status
Simulation time 2678471232 ps
CPU time 2.63 seconds
Started Jul 24 05:04:20 PM PDT 24
Finished Jul 24 05:04:23 PM PDT 24
Peak memory 205192 kb
Host smart-04ec2d12-ddec-4777-ac47-f9e9edb1df85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109140160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1109140160
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1833846509
Short name T223
Test name
Test status
Simulation time 62553520 ps
CPU time 0.75 seconds
Started Jul 24 05:04:44 PM PDT 24
Finished Jul 24 05:04:45 PM PDT 24
Peak memory 204944 kb
Host smart-d9da7f3f-4473-4d21-88f3-3d4226d7ac6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833846509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1833846509
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.93375205
Short name T265
Test name
Test status
Simulation time 136369886 ps
CPU time 0.86 seconds
Started Jul 24 05:04:32 PM PDT 24
Finished Jul 24 05:04:33 PM PDT 24
Peak memory 205040 kb
Host smart-38879864-bdfb-4cf9-9360-285d0b2408a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93375205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.93375205
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3505144519
Short name T199
Test name
Test status
Simulation time 49298406 ps
CPU time 0.79 seconds
Started Jul 24 05:04:30 PM PDT 24
Finished Jul 24 05:04:31 PM PDT 24
Peak memory 205196 kb
Host smart-05eb01d5-2eef-43b6-ab0c-e0f8c6661739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505144519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3505144519
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2413210196
Short name T200
Test name
Test status
Simulation time 72055936 ps
CPU time 0.76 seconds
Started Jul 24 05:04:43 PM PDT 24
Finished Jul 24 05:04:44 PM PDT 24
Peak memory 205044 kb
Host smart-12fcb89a-1c0d-4248-8e26-87a480ea9a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413210196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2413210196
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.3274467960
Short name T22
Test name
Test status
Simulation time 5214414694 ps
CPU time 15.42 seconds
Started Jul 24 05:04:41 PM PDT 24
Finished Jul 24 05:04:57 PM PDT 24
Peak memory 213164 kb
Host smart-ea7096e0-a164-446d-bf12-c58b382e1ce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274467960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3274467960
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3173937458
Short name T195
Test name
Test status
Simulation time 66695878 ps
CPU time 0.72 seconds
Started Jul 24 05:04:47 PM PDT 24
Finished Jul 24 05:04:53 PM PDT 24
Peak memory 204916 kb
Host smart-127394e5-440a-44e5-8ca8-a04ff0619a20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173937458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3173937458
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1094889141
Short name T171
Test name
Test status
Simulation time 81677649 ps
CPU time 0.88 seconds
Started Jul 24 05:04:45 PM PDT 24
Finished Jul 24 05:04:46 PM PDT 24
Peak memory 205056 kb
Host smart-c0e5f9eb-25b1-40c8-9027-9a041db41ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094889141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1094889141
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2739359019
Short name T210
Test name
Test status
Simulation time 55817599 ps
CPU time 0.8 seconds
Started Jul 24 05:04:13 PM PDT 24
Finished Jul 24 05:04:14 PM PDT 24
Peak memory 205044 kb
Host smart-1713cbd8-36b8-4316-a1ec-0c9891365d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739359019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2739359019
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1375793672
Short name T185
Test name
Test status
Simulation time 13709157557 ps
CPU time 36.88 seconds
Started Jul 24 05:04:05 PM PDT 24
Finished Jul 24 05:04:42 PM PDT 24
Peak memory 213556 kb
Host smart-40fec7ce-9aa7-4068-9881-4bd14b4baf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375793672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1375793672
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1401597880
Short name T285
Test name
Test status
Simulation time 3795447971 ps
CPU time 9.52 seconds
Started Jul 24 05:04:07 PM PDT 24
Finished Jul 24 05:04:17 PM PDT 24
Peak memory 213640 kb
Host smart-21b9343b-39b4-4bb5-8bcc-9b6765e7131d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401597880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1401597880
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3425323616
Short name T140
Test name
Test status
Simulation time 9269501805 ps
CPU time 16.5 seconds
Started Jul 24 05:04:06 PM PDT 24
Finished Jul 24 05:04:23 PM PDT 24
Peak memory 213484 kb
Host smart-73f644d4-a0a5-466f-ba4a-94cea4f91fb0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425323616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3425323616
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.237149093
Short name T249
Test name
Test status
Simulation time 93296283 ps
CPU time 0.93 seconds
Started Jul 24 05:04:10 PM PDT 24
Finished Jul 24 05:04:11 PM PDT 24
Peak memory 204932 kb
Host smart-9e069d76-24e1-429e-a978-69a5f2f07194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237149093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.237149093
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1738932152
Short name T201
Test name
Test status
Simulation time 2714216507 ps
CPU time 5.95 seconds
Started Jul 24 05:04:10 PM PDT 24
Finished Jul 24 05:04:16 PM PDT 24
Peak memory 205348 kb
Host smart-303e5ead-6dbf-498f-b989-52e7ea585ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738932152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1738932152
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3337350537
Short name T69
Test name
Test status
Simulation time 1658281696 ps
CPU time 1.5 seconds
Started Jul 24 05:04:04 PM PDT 24
Finished Jul 24 05:04:06 PM PDT 24
Peak memory 229640 kb
Host smart-680b7a04-e4f0-4283-86a4-73382a2c26e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337350537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3337350537
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.702107692
Short name T241
Test name
Test status
Simulation time 46937841 ps
CPU time 0.73 seconds
Started Jul 24 05:04:34 PM PDT 24
Finished Jul 24 05:04:35 PM PDT 24
Peak memory 205056 kb
Host smart-96fcb7c1-fccb-46c3-935d-d12d299d0753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702107692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.702107692
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.765036017
Short name T147
Test name
Test status
Simulation time 4069572108 ps
CPU time 6.27 seconds
Started Jul 24 05:04:34 PM PDT 24
Finished Jul 24 05:04:40 PM PDT 24
Peak memory 205088 kb
Host smart-ce75b484-6331-4f70-90e0-5bdfe56bfa57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765036017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.765036017
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3085102301
Short name T129
Test name
Test status
Simulation time 151236162 ps
CPU time 0.85 seconds
Started Jul 24 05:04:43 PM PDT 24
Finished Jul 24 05:04:44 PM PDT 24
Peak memory 204924 kb
Host smart-5c47b71b-6394-4c7a-942b-2d09f62b3f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085102301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3085102301
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.1939422108
Short name T34
Test name
Test status
Simulation time 2918158727 ps
CPU time 5.66 seconds
Started Jul 24 05:04:38 PM PDT 24
Finished Jul 24 05:04:43 PM PDT 24
Peak memory 213248 kb
Host smart-b52ab2a3-f0f9-4dac-9124-f14966e841cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939422108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1939422108
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3084906682
Short name T46
Test name
Test status
Simulation time 146666483 ps
CPU time 0.87 seconds
Started Jul 24 05:04:41 PM PDT 24
Finished Jul 24 05:04:43 PM PDT 24
Peak memory 204932 kb
Host smart-82c0ce31-f21a-4d13-8de9-3930686b305a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084906682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3084906682
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.939618928
Short name T176
Test name
Test status
Simulation time 88994167 ps
CPU time 0.76 seconds
Started Jul 24 05:04:44 PM PDT 24
Finished Jul 24 05:04:45 PM PDT 24
Peak memory 204984 kb
Host smart-b729c9a9-2e86-4cfc-93b3-0bea73f57afe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939618928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.939618928
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1347685968
Short name T236
Test name
Test status
Simulation time 46537225 ps
CPU time 0.73 seconds
Started Jul 24 05:04:29 PM PDT 24
Finished Jul 24 05:04:30 PM PDT 24
Peak memory 204908 kb
Host smart-0528c64a-0cf2-4396-8068-7f52917e8455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347685968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1347685968
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.138851057
Short name T149
Test name
Test status
Simulation time 2059977809 ps
CPU time 2.76 seconds
Started Jul 24 05:04:24 PM PDT 24
Finished Jul 24 05:04:26 PM PDT 24
Peak memory 204988 kb
Host smart-b4c75142-ce10-461d-b040-136a1386d42c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138851057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.138851057
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2014880726
Short name T213
Test name
Test status
Simulation time 117995453 ps
CPU time 0.77 seconds
Started Jul 24 05:04:39 PM PDT 24
Finished Jul 24 05:04:40 PM PDT 24
Peak memory 204980 kb
Host smart-2bb76bae-51ed-4463-a641-901e6a595b3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014880726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2014880726
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1840504880
Short name T32
Test name
Test status
Simulation time 2457904646 ps
CPU time 8.15 seconds
Started Jul 24 05:04:30 PM PDT 24
Finished Jul 24 05:04:39 PM PDT 24
Peak memory 205164 kb
Host smart-3711c4b6-bab0-4f70-9fcc-51074ff63ba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840504880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1840504880
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.392336084
Short name T209
Test name
Test status
Simulation time 38375758 ps
CPU time 0.79 seconds
Started Jul 24 05:04:34 PM PDT 24
Finished Jul 24 05:04:35 PM PDT 24
Peak memory 204880 kb
Host smart-404dcd42-5511-4ccf-8338-e7c2a8e8cb9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392336084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.392336084
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.3780277930
Short name T33
Test name
Test status
Simulation time 2772466725 ps
CPU time 5.58 seconds
Started Jul 24 05:04:24 PM PDT 24
Finished Jul 24 05:04:30 PM PDT 24
Peak memory 205092 kb
Host smart-48464fd4-6a61-469b-b318-f48c22302f07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780277930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3780277930
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3318551798
Short name T169
Test name
Test status
Simulation time 72438182 ps
CPU time 0.76 seconds
Started Jul 24 05:04:42 PM PDT 24
Finished Jul 24 05:04:43 PM PDT 24
Peak memory 205056 kb
Host smart-e37f9a60-3a32-4532-a934-74cc63f548d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318551798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3318551798
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3626261845
Short name T173
Test name
Test status
Simulation time 65089573 ps
CPU time 0.85 seconds
Started Jul 24 05:04:21 PM PDT 24
Finished Jul 24 05:04:22 PM PDT 24
Peak memory 204988 kb
Host smart-dcfb6903-6ad0-4987-ad4f-ad336c08dbbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626261845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3626261845
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3634584676
Short name T50
Test name
Test status
Simulation time 71105047 ps
CPU time 0.75 seconds
Started Jul 24 05:04:47 PM PDT 24
Finished Jul 24 05:04:48 PM PDT 24
Peak memory 205080 kb
Host smart-db6ef54b-3479-4d1f-81c8-423cf6c2a6c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634584676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3634584676
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2901921864
Short name T208
Test name
Test status
Simulation time 119631546 ps
CPU time 0.93 seconds
Started Jul 24 05:04:06 PM PDT 24
Finished Jul 24 05:04:07 PM PDT 24
Peak memory 204932 kb
Host smart-63351064-a313-4ca9-9165-07d54612d63a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901921864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2901921864
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1129210156
Short name T56
Test name
Test status
Simulation time 6729623146 ps
CPU time 16.32 seconds
Started Jul 24 05:04:09 PM PDT 24
Finished Jul 24 05:04:26 PM PDT 24
Peak memory 214352 kb
Host smart-0c465666-8d8e-470e-9fe1-fad212005b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129210156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1129210156
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1817489430
Short name T180
Test name
Test status
Simulation time 4182056662 ps
CPU time 9.01 seconds
Started Jul 24 05:04:18 PM PDT 24
Finished Jul 24 05:04:27 PM PDT 24
Peak memory 213584 kb
Host smart-199dbab9-bea9-4668-bfbd-0c13b27f0ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817489430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1817489430
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.774706128
Short name T256
Test name
Test status
Simulation time 4067647648 ps
CPU time 9.09 seconds
Started Jul 24 05:04:11 PM PDT 24
Finished Jul 24 05:04:20 PM PDT 24
Peak memory 205460 kb
Host smart-4119bf99-3150-4f7b-9317-d4aee1b9bf79
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=774706128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.774706128
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2088082294
Short name T266
Test name
Test status
Simulation time 3235199027 ps
CPU time 3.07 seconds
Started Jul 24 05:04:07 PM PDT 24
Finished Jul 24 05:04:10 PM PDT 24
Peak memory 205240 kb
Host smart-5f130295-d746-4467-9007-ea908e9f084c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088082294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2088082294
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.2004698103
Short name T59
Test name
Test status
Simulation time 7668779547 ps
CPU time 11.27 seconds
Started Jul 24 05:04:14 PM PDT 24
Finished Jul 24 05:04:26 PM PDT 24
Peak memory 212660 kb
Host smart-06bf1607-ec2a-48bd-bb63-346bdb521e26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004698103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2004698103
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1001463575
Short name T240
Test name
Test status
Simulation time 84065646 ps
CPU time 0.73 seconds
Started Jul 24 05:04:19 PM PDT 24
Finished Jul 24 05:04:19 PM PDT 24
Peak memory 204804 kb
Host smart-366064f3-8965-4a05-9e15-75c2b8ca6392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001463575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1001463575
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.691873509
Short name T137
Test name
Test status
Simulation time 2298919417 ps
CPU time 2.37 seconds
Started Jul 24 05:04:12 PM PDT 24
Finished Jul 24 05:04:15 PM PDT 24
Peak memory 213564 kb
Host smart-5b7c626b-faec-48d7-8b41-37e5de9edebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691873509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.691873509
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2069465066
Short name T13
Test name
Test status
Simulation time 2987582946 ps
CPU time 3.33 seconds
Started Jul 24 05:04:12 PM PDT 24
Finished Jul 24 05:04:15 PM PDT 24
Peak memory 213448 kb
Host smart-33f86419-7626-4373-bb1f-7fc68c8d9447
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2069465066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2069465066
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2262412318
Short name T133
Test name
Test status
Simulation time 4273463702 ps
CPU time 11.41 seconds
Started Jul 24 05:04:06 PM PDT 24
Finished Jul 24 05:04:18 PM PDT 24
Peak memory 213544 kb
Host smart-0ad56a53-c012-42e9-973f-c3b55790b82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262412318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2262412318
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1456689328
Short name T248
Test name
Test status
Simulation time 140316498 ps
CPU time 0.76 seconds
Started Jul 24 05:04:24 PM PDT 24
Finished Jul 24 05:04:25 PM PDT 24
Peak memory 204968 kb
Host smart-be454ee7-89c3-49c2-b129-48f73d4513db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456689328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1456689328
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.4287645820
Short name T187
Test name
Test status
Simulation time 15577487391 ps
CPU time 40.3 seconds
Started Jul 24 05:04:18 PM PDT 24
Finished Jul 24 05:05:03 PM PDT 24
Peak memory 213580 kb
Host smart-df3d79ab-126e-4aed-8fa8-24627d222ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287645820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.4287645820
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2024996104
Short name T238
Test name
Test status
Simulation time 6508951331 ps
CPU time 3.59 seconds
Started Jul 24 05:04:11 PM PDT 24
Finished Jul 24 05:04:14 PM PDT 24
Peak memory 213628 kb
Host smart-405a678a-53d6-4d55-8662-cde904e76134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024996104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2024996104
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3007883524
Short name T283
Test name
Test status
Simulation time 3525102787 ps
CPU time 10.46 seconds
Started Jul 24 05:04:29 PM PDT 24
Finished Jul 24 05:04:40 PM PDT 24
Peak memory 205288 kb
Host smart-79ba1061-77a2-4564-a65f-3e3e4e67ce49
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3007883524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3007883524
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3386649173
Short name T233
Test name
Test status
Simulation time 2684911885 ps
CPU time 2.49 seconds
Started Jul 24 05:04:32 PM PDT 24
Finished Jul 24 05:04:35 PM PDT 24
Peak memory 213460 kb
Host smart-19f9896a-72db-427a-8b9d-7a69f324ef2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386649173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3386649173
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2742009523
Short name T193
Test name
Test status
Simulation time 168212310 ps
CPU time 0.75 seconds
Started Jul 24 05:04:17 PM PDT 24
Finished Jul 24 05:04:18 PM PDT 24
Peak memory 205032 kb
Host smart-c08e57ab-d39f-4b91-a056-69deb033e34c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742009523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2742009523
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2050734176
Short name T282
Test name
Test status
Simulation time 2117380500 ps
CPU time 3.92 seconds
Started Jul 24 05:04:18 PM PDT 24
Finished Jul 24 05:04:22 PM PDT 24
Peak memory 213560 kb
Host smart-f4b3c0c3-f496-4def-bfcc-997f2dd57e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050734176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2050734176
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2829897681
Short name T260
Test name
Test status
Simulation time 962613669 ps
CPU time 3.56 seconds
Started Jul 24 05:04:24 PM PDT 24
Finished Jul 24 05:04:27 PM PDT 24
Peak memory 205244 kb
Host smart-7d56dfbe-5e02-421c-b807-68897cd185ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829897681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2829897681
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1787764075
Short name T261
Test name
Test status
Simulation time 5654557844 ps
CPU time 16.82 seconds
Started Jul 24 05:04:21 PM PDT 24
Finished Jul 24 05:04:38 PM PDT 24
Peak memory 205220 kb
Host smart-c026a5f1-33c2-44ec-84ce-b317b4df7c68
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787764075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.1787764075
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.4098059809
Short name T277
Test name
Test status
Simulation time 6704968862 ps
CPU time 10.82 seconds
Started Jul 24 05:04:21 PM PDT 24
Finished Jul 24 05:04:32 PM PDT 24
Peak memory 205324 kb
Host smart-3189beb3-480d-4872-870a-26cfa103eda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098059809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.4098059809
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1815064680
Short name T12
Test name
Test status
Simulation time 57425997417 ps
CPU time 61.98 seconds
Started Jul 24 05:04:25 PM PDT 24
Finished Jul 24 05:05:27 PM PDT 24
Peak memory 213496 kb
Host smart-637089be-15ab-4770-933d-8009d7409fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815064680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1815064680
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3798432298
Short name T232
Test name
Test status
Simulation time 4196939410 ps
CPU time 7.52 seconds
Started Jul 24 05:04:44 PM PDT 24
Finished Jul 24 05:04:51 PM PDT 24
Peak memory 214684 kb
Host smart-b413272e-e101-4a63-8205-5327b0b2b0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798432298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3798432298
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1106426539
Short name T258
Test name
Test status
Simulation time 1772251710 ps
CPU time 3.44 seconds
Started Jul 24 05:04:28 PM PDT 24
Finished Jul 24 05:04:32 PM PDT 24
Peak memory 205184 kb
Host smart-491af5e4-9390-42f1-a1a9-dd733d8fa405
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106426539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1106426539
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3311942652
Short name T267
Test name
Test status
Simulation time 3686251695 ps
CPU time 6.04 seconds
Started Jul 24 05:04:11 PM PDT 24
Finished Jul 24 05:04:17 PM PDT 24
Peak memory 213440 kb
Host smart-42713806-4b5a-493a-8f01-0fe963662f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311942652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3311942652
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.2452902707
Short name T148
Test name
Test status
Simulation time 5239738423 ps
CPU time 4.16 seconds
Started Jul 24 05:04:27 PM PDT 24
Finished Jul 24 05:04:31 PM PDT 24
Peak memory 214052 kb
Host smart-f189fa24-f2dc-4ae2-b0fe-7c22b5e3cc80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452902707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.2452902707
Directory /workspace/9.rv_dm_stress_all/latest
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