Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	507772	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	871472	1		T7	2		T8	3		T4	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	581275	1		T7	1		T32	80		T5	13082
values[0x0]	280024	1		T7	3		T8	3		T4	3
values[0x1]	517945	1		T7	2		T8	7		T4	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	271420	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	1107824	1		T7	4		T8	5		T4	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5148	1		T5	289		T24	395		T14	578
valid_sources[0x01]	5361	1		T5	335		T24	392		T14	648
valid_sources[0x02]	5249	1		T5	293		T24	333		T14	721
valid_sources[0x03]	4878	1		T5	382		T24	344		T14	614
valid_sources[0x04]	5597	1		T5	407		T24	343		T14	603
valid_sources[0x05]	5472	1		T5	299		T24	361		T21	1
valid_sources[0x06]	5483	1		T5	386		T24	283		T14	629
valid_sources[0x07]	5597	1		T5	411		T24	351		T14	669
valid_sources[0x08]	5378	1		T5	331		T30	2		T24	356
valid_sources[0x09]	5659	1		T5	273		T24	370		T14	600
valid_sources[0x0a]	5235	1		T4	1		T5	281		T24	372
valid_sources[0x0b]	5018	1		T5	313		T24	363		T14	666
valid_sources[0x0c]	4713	1		T5	321		T24	343		T14	621
valid_sources[0x0d]	5046	1		T5	323		T24	329		T14	630
valid_sources[0x0e]	5736	1		T5	405		T24	355		T14	618
valid_sources[0x0f]	5509	1		T5	436		T24	331		T14	596
valid_sources[0x10]	5361	1		T5	324		T24	361		T14	607
valid_sources[0x11]	5768	1		T5	464		T24	324		T14	700
valid_sources[0x12]	8414	1		T5	345		T24	318		T14	736
valid_sources[0x13]	6259	1		T5	354		T24	347		T14	600
valid_sources[0x14]	5119	1		T5	239		T24	340		T14	650
valid_sources[0x15]	5360	1		T5	288		T24	334		T13	2
valid_sources[0x16]	5366	1		T5	323		T24	368		T155	1
valid_sources[0x17]	5455	1		T5	384		T24	390		T14	610
valid_sources[0x18]	5274	1		T5	384		T24	307		T14	609
valid_sources[0x19]	5379	1		T5	335		T24	334		T14	617
valid_sources[0x1a]	5076	1		T5	351		T30	1		T24	326
valid_sources[0x1b]	5675	1		T5	384		T24	361		T14	601
valid_sources[0x1c]	5552	1		T5	436		T24	358		T14	584
valid_sources[0x1d]	5289	1		T5	434		T24	367		T14	667
valid_sources[0x1e]	4726	1		T5	318		T24	370		T14	688
valid_sources[0x1f]	5426	1		T5	414		T24	379		T14	648
valid_sources[0x20]	4778	1		T5	356		T17	2		T24	361
valid_sources[0x21]	5208	1		T4	2		T5	434		T24	312
valid_sources[0x22]	5181	1		T5	255		T24	376		T14	640
valid_sources[0x23]	5061	1		T5	383		T24	381		T14	596
valid_sources[0x24]	5349	1		T5	512		T24	374		T54	2
valid_sources[0x25]	4909	1		T5	251		T30	1		T24	343
valid_sources[0x26]	4993	1		T5	208		T30	1		T24	372
valid_sources[0x27]	5478	1		T5	331		T30	1		T24	329
valid_sources[0x28]	5428	1		T5	318		T24	351		T14	653
valid_sources[0x29]	5126	1		T5	295		T24	421		T14	628
valid_sources[0x2a]	5802	1		T5	296		T24	377		T14	679
valid_sources[0x2b]	5577	1		T5	323		T24	381		T14	665
valid_sources[0x2c]	4981	1		T5	510		T6	2		T24	345
valid_sources[0x2d]	5208	1		T5	336		T24	330		T14	611
valid_sources[0x2e]	4784	1		T5	279		T24	347		T14	623
valid_sources[0x2f]	5481	1		T5	257		T24	335		T14	663
valid_sources[0x30]	4907	1		T5	319		T24	351		T14	648
valid_sources[0x31]	5504	1		T5	387		T24	326		T21	1
valid_sources[0x32]	5295	1		T5	495		T24	387		T14	661
valid_sources[0x33]	5516	1		T5	408		T24	320		T13	1
valid_sources[0x34]	5586	1		T5	279		T24	331		T14	689
valid_sources[0x35]	5334	1		T5	390		T30	1		T24	354
valid_sources[0x36]	4966	1		T7	6		T5	362		T24	333
valid_sources[0x37]	5952	1		T5	363		T24	349		T14	674
valid_sources[0x38]	5338	1		T5	382		T24	343		T14	661
valid_sources[0x39]	11081	1		T5	287		T30	1		T24	390
valid_sources[0x3a]	5531	1		T5	377		T24	327		T14	681
valid_sources[0x3b]	5733	1		T5	428		T24	399		T14	619
valid_sources[0x3c]	4701	1		T5	387		T24	353		T14	610
valid_sources[0x3d]	5399	1		T5	405		T24	355		T14	737
valid_sources[0x3e]	5615	1		T5	328		T24	352		T14	678
valid_sources[0x3f]	5012	1		T5	275		T24	339		T14	630
valid_sources[0x40]	5649	1		T5	335		T24	345		T14	625
valid_sources[0x41]	5646	1		T5	311		T24	334		T14	636
valid_sources[0x42]	5231	1		T5	330		T24	357		T13	1
valid_sources[0x43]	5424	1		T5	245		T24	368		T14	697
valid_sources[0x44]	5688	1		T5	235		T24	356		T14	686
valid_sources[0x45]	6116	1		T32	80		T5	389		T24	369
valid_sources[0x46]	5143	1		T5	281		T24	339		T14	631
valid_sources[0x47]	5969	1		T5	339		T24	345		T14	645
valid_sources[0x48]	5166	1		T5	396		T24	317		T14	629
valid_sources[0x49]	5226	1		T5	373		T24	326		T14	672
valid_sources[0x4a]	5441	1		T5	478		T24	380		T14	627
valid_sources[0x4b]	5562	1		T5	385		T24	357		T14	615
valid_sources[0x4c]	5027	1		T5	349		T24	344		T14	597
valid_sources[0x4d]	5849	1		T5	326		T24	390		T14	613
valid_sources[0x4e]	5028	1		T5	328		T24	356		T14	653
valid_sources[0x4f]	5416	1		T5	280		T24	314		T14	624
valid_sources[0x50]	5385	1		T5	259		T24	336		T13	4
valid_sources[0x51]	5492	1		T5	469		T24	317		T14	664
valid_sources[0x52]	4858	1		T5	383		T24	371		T14	669
valid_sources[0x53]	5386	1		T8	2		T5	342		T24	351
valid_sources[0x54]	5325	1		T5	366		T24	383		T14	645
valid_sources[0x55]	5072	1		T5	338		T24	360		T14	659
valid_sources[0x56]	5676	1		T5	285		T24	338		T14	638
valid_sources[0x57]	5420	1		T5	382		T24	334		T14	682
valid_sources[0x58]	5585	1		T5	308		T24	349		T14	676
valid_sources[0x59]	5930	1		T8	2		T5	288		T30	1
valid_sources[0x5a]	4448	1		T5	268		T24	375		T14	566
valid_sources[0x5b]	7502	1		T5	325		T24	350		T14	605
valid_sources[0x5c]	5592	1		T5	347		T24	372		T14	609
valid_sources[0x5d]	5084	1		T5	355		T24	368		T14	711
valid_sources[0x5e]	4885	1		T5	196		T24	340		T14	672
valid_sources[0x5f]	5287	1		T5	402		T24	357		T14	657
valid_sources[0x60]	5170	1		T5	307		T24	356		T14	676
valid_sources[0x61]	5482	1		T5	302		T24	330		T14	601
valid_sources[0x62]	5295	1		T5	317		T24	342		T14	694
valid_sources[0x63]	4951	1		T5	300		T24	366		T14	629
valid_sources[0x64]	5363	1		T5	400		T24	346		T14	588
valid_sources[0x65]	4583	1		T5	244		T24	352		T14	618
valid_sources[0x66]	4862	1		T5	272		T24	359		T13	1
valid_sources[0x67]	4922	1		T5	336		T24	375		T14	641
valid_sources[0x68]	5145	1		T5	317		T24	368		T14	623
valid_sources[0x69]	5624	1		T5	323		T24	356		T14	649
valid_sources[0x6a]	5857	1		T5	293		T24	320		T14	664
valid_sources[0x6b]	4810	1		T5	227		T24	368		T14	660
valid_sources[0x6c]	5378	1		T5	286		T24	353		T14	612
valid_sources[0x6d]	5691	1		T5	348		T24	377		T14	604
valid_sources[0x6e]	4799	1		T5	407		T24	373		T14	588
valid_sources[0x6f]	5143	1		T5	350		T24	378		T14	658
valid_sources[0x70]	5260	1		T5	461		T24	378		T14	660
valid_sources[0x71]	4884	1		T5	337		T24	318		T14	615
valid_sources[0x72]	4994	1		T5	357		T30	1		T24	363
valid_sources[0x73]	6632	1		T4	2		T5	305		T24	364
valid_sources[0x74]	5322	1		T5	352		T24	345		T14	684
valid_sources[0x75]	5296	1		T5	423		T24	382		T14	636
valid_sources[0x76]	4665	1		T5	240		T24	359		T14	625
valid_sources[0x77]	6644	1		T5	327		T24	327		T14	651
valid_sources[0x78]	4958	1		T5	390		T24	306		T14	655
valid_sources[0x79]	4775	1		T5	264		T24	343		T14	641
valid_sources[0x7a]	5711	1		T5	347		T30	1		T24	371
valid_sources[0x7b]	5012	1		T5	375		T24	304		T13	1
valid_sources[0x7c]	5359	1		T5	300		T24	371		T14	628
valid_sources[0x7d]	5550	1		T5	302		T24	340		T14	654
valid_sources[0x7e]	4563	1		T5	315		T24	324		T14	649
valid_sources[0x7f]	5556	1		T5	337		T24	378		T14	661
valid_sources[0x80]	5641	1		T5	420		T24	355		T14	623

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

367827

1

T32

80

T5

11253

T30

3

values[0x0]

all_enables

biggest_size

252071

1

T7

2

T8

1

T4

2

values[0x1]

all_enables

biggest_size

251574

1

T8

2

T5

14927

T6

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	20715	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	409530	1		T1	1		T2	1		T3	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	112474	1		T5	15789		T24	16891		T14	30731
values[0x0]	154848	1		T2	8		T3	2		T7	5
values[0x1]	162923	1		T1	1		T2	5		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11797	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	418448	1		T1	1		T2	2		T3	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1675	1		T5	387		T24	209		T14	447
valid_sources[0x01]	1480	1		T5	38		T24	255		T14	475
valid_sources[0x02]	1573	1		T2	4		T5	167		T24	298
valid_sources[0x03]	1385	1		T2	1		T5	70		T24	315
valid_sources[0x04]	1688	1		T5	103		T24	290		T14	501
valid_sources[0x05]	1364	1		T5	50		T30	1		T46	1
valid_sources[0x06]	1502	1		T5	152		T24	257		T14	481
valid_sources[0x07]	1450	1		T5	197		T24	202		T14	482
valid_sources[0x08]	2001	1		T5	147		T6	5		T24	286
valid_sources[0x09]	1559	1		T5	249		T24	240		T14	425
valid_sources[0x0a]	1505	1		T5	132		T24	228		T14	470
valid_sources[0x0b]	1743	1		T48	1		T5	264		T24	273
valid_sources[0x0c]	1820	1		T48	1		T5	554		T24	260
valid_sources[0x0d]	1553	1		T10	1		T5	173		T24	227
valid_sources[0x0e]	1480	1		T5	207		T24	253		T14	475
valid_sources[0x0f]	1590	1		T7	1		T5	132		T24	245
valid_sources[0x10]	1675	1		T5	309		T24	199		T14	459
valid_sources[0x11]	1513	1		T5	261		T24	251		T14	443
valid_sources[0x12]	1512	1		T5	159		T24	256		T14	514
valid_sources[0x13]	1793	1		T5	119		T24	246		T14	449
valid_sources[0x14]	1738	1		T5	306		T24	260		T14	468
valid_sources[0x15]	1405	1		T5	63		T24	309		T14	475
valid_sources[0x16]	1712	1		T5	329		T24	296		T14	462
valid_sources[0x17]	1646	1		T5	26		T49	1		T24	273
valid_sources[0x18]	1535	1		T5	99		T24	247		T14	458
valid_sources[0x19]	1564	1		T5	245		T24	241		T14	491
valid_sources[0x1a]	1825	1		T5	343		T27	1		T24	326
valid_sources[0x1b]	1548	1		T5	242		T24	253		T14	470
valid_sources[0x1c]	1587	1		T5	227		T59	1		T24	267
valid_sources[0x1d]	2159	1		T9	1		T5	474		T24	244
valid_sources[0x1e]	2246	1		T5	217		T24	252		T14	480
valid_sources[0x1f]	1469	1		T5	87		T24	240		T13	1
valid_sources[0x20]	1735	1		T5	107		T24	236		T14	506
valid_sources[0x21]	1690	1		T5	269		T24	257		T14	515
valid_sources[0x22]	2134	1		T39	4		T5	437		T24	301
valid_sources[0x23]	2148	1		T5	236		T24	293		T14	462
valid_sources[0x24]	1686	1		T3	1		T5	223		T59	2
valid_sources[0x25]	1707	1		T5	192		T24	257		T14	428
valid_sources[0x26]	1744	1		T5	110		T24	214		T14	455
valid_sources[0x27]	1632	1		T5	69		T24	262		T14	478
valid_sources[0x28]	1544	1		T48	1		T5	99		T24	244
valid_sources[0x29]	1568	1		T5	260		T24	300		T14	481
valid_sources[0x2a]	1695	1		T5	79		T24	312		T14	457
valid_sources[0x2b]	2056	1		T5	465		T59	1		T24	302
valid_sources[0x2c]	1704	1		T5	210		T24	267		T14	464
valid_sources[0x2d]	1594	1		T5	239		T24	256		T14	457
valid_sources[0x2e]	1680	1		T5	454		T24	228		T13	1
valid_sources[0x2f]	1503	1		T5	235		T24	287		T14	470
valid_sources[0x30]	1536	1		T5	96		T24	260		T14	458
valid_sources[0x31]	1540	1		T40	1		T5	110		T59	1
valid_sources[0x32]	1530	1		T5	226		T24	286		T14	454
valid_sources[0x33]	1653	1		T5	138		T24	284		T171	1
valid_sources[0x34]	2014	1		T5	497		T24	294		T14	462
valid_sources[0x35]	1451	1		T5	133		T24	213		T14	438
valid_sources[0x36]	1805	1		T5	577		T24	241		T14	469
valid_sources[0x37]	1684	1		T5	372		T24	229		T14	503
valid_sources[0x38]	1564	1		T5	349		T24	206		T14	440
valid_sources[0x39]	1667	1		T5	130		T59	1		T47	8
valid_sources[0x3a]	1816	1		T5	413		T24	292		T14	494
valid_sources[0x3b]	1640	1		T5	354		T24	258		T14	493
valid_sources[0x3c]	1701	1		T5	168		T24	264		T14	429
valid_sources[0x3d]	1620	1		T5	316		T24	287		T14	425
valid_sources[0x3e]	1738	1		T5	328		T27	1		T24	244
valid_sources[0x3f]	1334	1		T5	137		T24	225		T14	428
valid_sources[0x40]	1827	1		T5	194		T24	220		T14	467
valid_sources[0x41]	1695	1		T8	1		T5	334		T24	287
valid_sources[0x42]	1641	1		T5	323		T24	269		T14	474
valid_sources[0x43]	1819	1		T5	435		T24	253		T14	520
valid_sources[0x44]	1766	1		T5	246		T24	281		T14	471
valid_sources[0x45]	1519	1		T5	155		T24	260		T14	504
valid_sources[0x46]	1605	1		T5	96		T24	257		T171	1
valid_sources[0x47]	1706	1		T5	241		T24	253		T14	457
valid_sources[0x48]	1335	1		T5	35		T24	251		T14	491
valid_sources[0x49]	1425	1		T5	144		T24	245		T14	462
valid_sources[0x4a]	1488	1		T5	204		T24	209		T14	488
valid_sources[0x4b]	1589	1		T56	1		T5	216		T24	283
valid_sources[0x4c]	1787	1		T5	357		T59	1		T24	260
valid_sources[0x4d]	1843	1		T5	418		T24	266		T14	444
valid_sources[0x4e]	1623	1		T5	267		T24	217		T14	460
valid_sources[0x4f]	1949	1		T5	460		T24	265		T14	499
valid_sources[0x50]	1996	1		T5	234		T24	251		T14	494
valid_sources[0x51]	1352	1		T5	135		T24	259		T14	425
valid_sources[0x52]	1620	1		T5	48		T24	256		T14	482
valid_sources[0x53]	1411	1		T7	6		T5	46		T24	281
valid_sources[0x54]	1503	1		T5	221		T30	1		T24	258
valid_sources[0x55]	1363	1		T5	63		T24	240		T14	462
valid_sources[0x56]	1575	1		T5	159		T46	1		T24	255
valid_sources[0x57]	2032	1		T5	113		T17	1		T24	299
valid_sources[0x58]	1935	1		T5	316		T24	225		T14	485
valid_sources[0x59]	1624	1		T5	345		T24	247		T14	482
valid_sources[0x5a]	1422	1		T5	98		T24	292		T14	453
valid_sources[0x5b]	1737	1		T5	218		T24	208		T14	537
valid_sources[0x5c]	1950	1		T5	342		T24	261		T14	478
valid_sources[0x5d]	1630	1		T7	1		T5	118		T24	253
valid_sources[0x5e]	1403	1		T5	161		T24	259		T14	477
valid_sources[0x5f]	1888	1		T5	502		T24	225		T14	483
valid_sources[0x60]	1709	1		T5	405		T24	277		T14	486
valid_sources[0x61]	1603	1		T5	239		T24	252		T14	474
valid_sources[0x62]	1852	1		T5	499		T24	223		T14	452
valid_sources[0x63]	1675	1		T5	333		T24	296		T14	451
valid_sources[0x64]	1672	1		T39	1		T5	245		T24	243
valid_sources[0x65]	2002	1		T5	207		T24	270		T14	497
valid_sources[0x66]	1723	1		T5	402		T24	283		T14	479
valid_sources[0x67]	1520	1		T5	170		T24	257		T54	6
valid_sources[0x68]	1757	1		T5	233		T24	258		T14	448
valid_sources[0x69]	2078	1		T5	473		T24	288		T14	469
valid_sources[0x6a]	1960	1		T5	299		T24	296		T14	474
valid_sources[0x6b]	1782	1		T5	109		T24	255		T14	503
valid_sources[0x6c]	1413	1		T5	41		T24	251		T14	481
valid_sources[0x6d]	1650	1		T5	69		T24	299		T14	447
valid_sources[0x6e]	1439	1		T5	92		T24	235		T14	480
valid_sources[0x6f]	1708	1		T56	1		T5	122		T24	245
valid_sources[0x70]	1526	1		T5	195		T24	251		T14	438
valid_sources[0x71]	1757	1		T5	129		T24	261		T14	456
valid_sources[0x72]	1462	1		T5	120		T24	240		T14	447
valid_sources[0x73]	1740	1		T5	196		T24	283		T14	444
valid_sources[0x74]	1376	1		T5	67		T27	1		T24	247
valid_sources[0x75]	1459	1		T5	186		T24	286		T14	457
valid_sources[0x76]	1392	1		T5	109		T24	254		T14	475
valid_sources[0x77]	2930	1		T5	138		T24	215		T14	491
valid_sources[0x78]	1503	1		T5	53		T24	260		T14	483
valid_sources[0x79]	1991	1		T39	3		T5	445		T24	211
valid_sources[0x7a]	1732	1		T56	1		T5	431		T24	252
valid_sources[0x7b]	1687	1		T5	203		T24	257		T13	1
valid_sources[0x7c]	1889	1		T5	483		T24	243		T14	476
valid_sources[0x7d]	1492	1		T5	181		T24	256		T14	475
valid_sources[0x7e]	1808	1		T5	222		T24	225		T14	433
valid_sources[0x7f]	1751	1		T5	363		T24	247		T14	498
valid_sources[0x80]	2097	1		T5	493		T30	1		T24	266

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

103993

1

T5

14897

T24

16014

T14

29059

values[0x0]

all_enables

biggest_size

152769

1

T3

2

T7

5

T16

1

values[0x1]

all_enables

biggest_size

152768

1

T1

1

T2

1

T3

3