SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 2549288 | 1 | T7 | 6 | T8 | 10 | T4 | 5 | |||
auto[1] | 746977 | 1 | T32 | 80 | T5 | 110059 | T24 | 117410 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3296040 | 1 | T7 | 6 | T8 | 10 | T4 | 5 | |||
values[1] | 17 | 1 | T159 | 1 | T160 | 2 | T161 | 2 | |||
values[2] | 1 | 1 | T161 | 1 | - | - | - | - | |||
values[3] | 129 | 1 | T118 | 5 | T120 | 6 | T121 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3296046 | 1 | T7 | 6 | T8 | 10 | T4 | 5 | |||
values[1] | 26 | 1 | T121 | 2 | T159 | 3 | T160 | 1 | |||
values[2] | 7 | 1 | T118 | 1 | T120 | 1 | T159 | 1 | |||
values[3] | 110 | 1 | T118 | 1 | T120 | 2 | T121 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3295935 | 1 | T7 | 6 | T8 | 10 | T4 | 5 | |||
auto[TlIntgErrCmd] | 111 | 1 | T118 | 7 | T120 | 2 | T121 | 10 | |||
auto[TlIntgErrData] | 105 | 1 | T118 | 2 | T120 | 3 | T121 | 7 | |||
auto[TlIntgErrBoth] | 114 | 1 | T118 | 1 | T120 | 5 | T121 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 1183245 | 0 | T1 | 1 | T2 | 13 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1183027 | 1 | T1 | 1 | T2 | 13 | T3 | 5 | |||
values[1] | 22 | 1 | T118 | 3 | T121 | 1 | T159 | 1 | |||
values[2] | 4 | 1 | T118 | 1 | T160 | 1 | T162 | 1 | |||
values[3] | 115 | 1 | T118 | 2 | T120 | 4 | T121 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1183029 | 1 | T1 | 1 | T2 | 13 | T3 | 5 | |||
values[1] | 22 | 1 | T118 | 1 | T120 | 1 | T121 | 2 | |||
values[2] | 10 | 1 | T121 | 1 | T159 | 1 | T161 | 2 | |||
values[3] | 114 | 1 | T118 | 1 | T120 | 6 | T121 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1182915 | 1 | T1 | 1 | T2 | 13 | T3 | 5 | |||
auto[TlIntgErrCmd] | 114 | 1 | T118 | 6 | T120 | 2 | T121 | 8 | |||
auto[TlIntgErrData] | 112 | 1 | T118 | 2 | T120 | 4 | T121 | 6 | |||
auto[TlIntgErrBoth] | 104 | 1 | T118 | 2 | T120 | 4 | T121 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |