Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	2360738	1		T7	4		T8	7		T4	3
full_word	935527	1		T7	2		T8	3		T4	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3295935	1		T7	6		T8	10		T4	5
auto[TlIntgErrCmd]	111	1		T118	7		T120	2		T121	10
auto[TlIntgErrData]	105	1		T118	2		T120	3		T121	7
auto[TlIntgErrBoth]	114	1		T118	1		T120	5		T121	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	658037	1		T7	1		T32	80		T5	23817
auto[1]	2638228	1		T7	5		T8	10		T4	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	282538	1		T7	1		T5	11502		T30	4
auto[TlIntgErrNone]	partial	auto[1]	2077896	1		T7	3		T8	7		T4	3
auto[TlIntgErrNone]	full_word	auto[0]	375361	1		T32	80		T5	12315		T30	3
auto[TlIntgErrNone]	full_word	auto[1]	560140	1		T7	2		T8	3		T4	2
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T118	2		T121	3		T159	1
auto[TlIntgErrCmd]	partial	auto[1]	62	1		T118	4		T120	1		T121	6
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T121	1		T163	1		T164	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T118	1		T120	1		T162	1
auto[TlIntgErrData]	partial	auto[0]	37	1		T120	1		T121	2		T159	1
auto[TlIntgErrData]	partial	auto[1]	60	1		T118	2		T120	1		T121	4
auto[TlIntgErrData]	full_word	auto[0]	3	1		T121	1		T161	1		T165	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T120	1		T159	1		T166	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1		T120	2		T121	2		T159	3
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T118	1		T121	1		T159	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T120	1		T159	1		T167	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T120	2		T168	2		-	-