Assert Coverage for Module :
rv_dm_regs_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145340706 |
553536 |
0 |
0 |
T5 |
459108 |
84788 |
0 |
0 |
T6 |
187924 |
0 |
0 |
0 |
T14 |
0 |
161453 |
0 |
0 |
T24 |
0 |
90896 |
0 |
0 |
T25 |
274642 |
0 |
0 |
0 |
T26 |
678912 |
0 |
0 |
0 |
T27 |
203332 |
0 |
0 |
0 |
T30 |
71271 |
0 |
0 |
0 |
T41 |
62236 |
0 |
0 |
0 |
T49 |
23432 |
0 |
0 |
0 |
T59 |
1379 |
0 |
0 |
0 |
T60 |
252527 |
0 |
0 |
0 |
T61 |
0 |
38609 |
0 |
0 |
T67 |
0 |
39731 |
0 |
0 |
T68 |
0 |
88872 |
0 |
0 |
T69 |
0 |
19073 |
0 |
0 |
T70 |
0 |
268 |
0 |
0 |
T71 |
0 |
26 |
0 |
0 |
T72 |
0 |
15 |
0 |
0 |
late_debug_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145340706 |
70880 |
0 |
0 |
T5 |
459108 |
28438 |
0 |
0 |
T6 |
187924 |
0 |
0 |
0 |
T25 |
274642 |
0 |
0 |
0 |
T26 |
678912 |
0 |
0 |
0 |
T27 |
203332 |
0 |
0 |
0 |
T30 |
71271 |
0 |
0 |
0 |
T41 |
62236 |
0 |
0 |
0 |
T49 |
23432 |
0 |
0 |
0 |
T59 |
1379 |
0 |
0 |
0 |
T60 |
252527 |
0 |
0 |
0 |
T62 |
0 |
1766 |
0 |
0 |
T68 |
0 |
29520 |
0 |
0 |
T69 |
0 |
6338 |
0 |
0 |
T71 |
0 |
10 |
0 |
0 |
T72 |
0 |
26 |
0 |
0 |
T78 |
0 |
20 |
0 |
0 |
T80 |
0 |
4 |
0 |
0 |
T118 |
0 |
20 |
0 |
0 |
T119 |
0 |
9 |
0 |
0 |
late_debug_enable_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
145340706 |
61126 |
0 |
0 |
T5 |
459108 |
24778 |
0 |
0 |
T6 |
187924 |
0 |
0 |
0 |
T25 |
274642 |
0 |
0 |
0 |
T26 |
678912 |
0 |
0 |
0 |
T27 |
203332 |
0 |
0 |
0 |
T30 |
71271 |
0 |
0 |
0 |
T41 |
62236 |
0 |
0 |
0 |
T49 |
23432 |
0 |
0 |
0 |
T59 |
1379 |
0 |
0 |
0 |
T60 |
252527 |
0 |
0 |
0 |
T62 |
0 |
1361 |
0 |
0 |
T68 |
0 |
26276 |
0 |
0 |
T69 |
0 |
5441 |
0 |
0 |
T71 |
0 |
12 |
0 |
0 |
T72 |
0 |
11 |
0 |
0 |
T78 |
0 |
15 |
0 |
0 |
T80 |
0 |
4 |
0 |
0 |
T118 |
0 |
30 |
0 |
0 |
T119 |
0 |
35 |
0 |
0 |