Unified Coverage Report :: Module :: prim_mubi8_sync

Module : prim_mubi8_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[4].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[5].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[6].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[7].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[4].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[5].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[6].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[7].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[4].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[5].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[6].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[7].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[4].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[5].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[6].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[7].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_mubi8_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	4	4

---

Assert Coverage for Module : prim_mubi8_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	225	225	0	0
OutputsKnown_A	69972062	69928342	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	69972062	69926572	0	675

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225	225	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T16	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69972062	69928342	0	0
T1	141975	141887	0	0
T2	1978	1891	0	0
T3	270421	270099	0	0
T7	89827	89541	0	0
T8	122130	122066	0	0
T9	11363	11312	0	0
T10	545277	545205	0	0
T16	252689	252637	0	0
T39	2746	2674	0	0
T40	2639	2583	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69972062	69926572	0	675
T1	141975	141884	0	3
T2	1978	1888	0	3
T3	270421	270084	0	3
T7	89827	89529	0	3
T8	122130	122063	0	3
T9	11363	11309	0	3
T10	545277	545202	0	3
T16	252689	252634	0	3
T39	2746	2671	0	3
T40	2639	2580	0	3