Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
69972062 |
69928342 |
0 |
0 |
T1 |
141975 |
141887 |
0 |
0 |
T2 |
1978 |
1891 |
0 |
0 |
T3 |
270421 |
270099 |
0 |
0 |
T7 |
89827 |
89541 |
0 |
0 |
T8 |
122130 |
122066 |
0 |
0 |
T9 |
11363 |
11312 |
0 |
0 |
T10 |
545277 |
545205 |
0 |
0 |
T16 |
252689 |
252637 |
0 |
0 |
T39 |
2746 |
2674 |
0 |
0 |
T40 |
2639 |
2583 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
69972062 |
69928342 |
0 |
0 |
T1 |
141975 |
141887 |
0 |
0 |
T2 |
1978 |
1891 |
0 |
0 |
T3 |
270421 |
270099 |
0 |
0 |
T7 |
89827 |
89541 |
0 |
0 |
T8 |
122130 |
122066 |
0 |
0 |
T9 |
11363 |
11312 |
0 |
0 |
T10 |
545277 |
545205 |
0 |
0 |
T16 |
252689 |
252637 |
0 |
0 |
T39 |
2746 |
2674 |
0 |
0 |
T40 |
2639 |
2583 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
69972062 |
69928342 |
0 |
0 |
T1 |
141975 |
141887 |
0 |
0 |
T2 |
1978 |
1891 |
0 |
0 |
T3 |
270421 |
270099 |
0 |
0 |
T7 |
89827 |
89541 |
0 |
0 |
T8 |
122130 |
122066 |
0 |
0 |
T9 |
11363 |
11312 |
0 |
0 |
T10 |
545277 |
545205 |
0 |
0 |
T16 |
252689 |
252637 |
0 |
0 |
T39 |
2746 |
2674 |
0 |
0 |
T40 |
2639 |
2583 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
69972062 |
69928342 |
0 |
0 |
T1 |
141975 |
141887 |
0 |
0 |
T2 |
1978 |
1891 |
0 |
0 |
T3 |
270421 |
270099 |
0 |
0 |
T7 |
89827 |
89541 |
0 |
0 |
T8 |
122130 |
122066 |
0 |
0 |
T9 |
11363 |
11312 |
0 |
0 |
T10 |
545277 |
545205 |
0 |
0 |
T16 |
252689 |
252637 |
0 |
0 |
T39 |
2746 |
2674 |
0 |
0 |
T40 |
2639 |
2583 |
0 |
0 |