Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 13950440 13949102 0 0
selKnown1 78977692 78976354 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 13950440 13949102 0 0
T1 36924 36922 0 0
T2 604 602 0 0
T3 38413 38409 0 0
T5 0 67 0 0
T6 0 6 0 0
T7 26747 26743 0 0
T8 7457 7453 0 0
T9 7268 7264 0 0
T10 35832 35828 0 0
T16 30486 30482 0 0
T26 0 6 0 0
T27 0 8 0 0
T30 0 11 0 0
T34 2 0 0 0
T39 612 608 0 0
T40 496 492 0 0
T41 0 20 0 0
T46 0 8 0 0
T47 0 14 0 0
T48 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 78977692 78976354 0 0
T1 160437 160435 0 0
T2 2280 2278 0 0
T3 289631 289627 0 0
T5 0 20 0 0
T6 0 4 0 0
T7 103203 103199 0 0
T8 125859 125855 0 0
T9 14998 14994 0 0
T10 563194 563190 0 0
T16 267933 267929 0 0
T26 0 6 0 0
T27 0 8 0 0
T30 0 8 0 0
T34 2 0 0 0
T39 3053 3049 0 0
T40 2888 2884 0 0
T41 0 20 0 0
T46 0 8 0 0
T47 0 14 0 0
T48 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 4944282 4944057 0 0
selKnown1 69972062 69971837 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 4944282 4944057 0 0
T1 18462 18461 0 0
T2 302 301 0 0
T3 19200 19199 0 0
T7 13368 13367 0 0
T8 3727 3726 0 0
T9 3633 3632 0 0
T10 17915 17914 0 0
T16 15242 15241 0 0
T39 305 304 0 0
T40 247 246 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 69972062 69971837 0 0
T1 141975 141974 0 0
T2 1978 1977 0 0
T3 270421 270420 0 0
T7 89827 89826 0 0
T8 122130 122129 0 0
T9 11363 11362 0 0
T10 545277 545276 0 0
T16 252689 252688 0 0
T39 2746 2745 0 0
T40 2639 2638 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 620 395 0 0
selKnown1 590 365 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 620 395 0 0
T3 5 4 0 0
T5 0 16 0 0
T6 0 3 0 0
T7 5 4 0 0
T8 1 0 0 0
T9 1 0 0 0
T10 1 0 0 0
T16 1 0 0 0
T26 0 3 0 0
T27 0 4 0 0
T30 0 4 0 0
T34 1 0 0 0
T39 1 0 0 0
T40 1 0 0 0
T41 0 10 0 0
T46 0 4 0 0
T47 0 7 0 0
T48 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 590 365 0 0
T3 5 4 0 0
T5 0 10 0 0
T6 0 2 0 0
T7 4 3 0 0
T8 1 0 0 0
T9 1 0 0 0
T10 1 0 0 0
T16 1 0 0 0
T26 0 3 0 0
T27 0 4 0 0
T30 0 4 0 0
T34 1 0 0 0
T39 1 0 0 0
T40 1 0 0 0
T41 0 10 0 0
T46 0 4 0 0
T47 0 7 0 0
T48 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9003462 9003018 0 0
selKnown1 9003268 9002824 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9003462 9003018 0 0
T1 18462 18461 0 0
T2 302 301 0 0
T3 19201 19200 0 0
T7 13369 13368 0 0
T8 3728 3727 0 0
T9 3633 3632 0 0
T10 17915 17914 0 0
T16 15242 15241 0 0
T39 305 304 0 0
T40 247 246 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 9003268 9002824 0 0
T1 18462 18461 0 0
T2 302 301 0 0
T3 19200 19199 0 0
T7 13368 13367 0 0
T8 3727 3726 0 0
T9 3633 3632 0 0
T10 17915 17914 0 0
T16 15242 15241 0 0
T39 305 304 0 0
T40 247 246 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2076 1632 0 0
selKnown1 1772 1328 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2076 1632 0 0
T3 7 6 0 0
T5 0 51 0 0
T6 0 3 0 0
T7 5 4 0 0
T8 1 0 0 0
T9 1 0 0 0
T10 1 0 0 0
T16 1 0 0 0
T26 0 3 0 0
T27 0 4 0 0
T30 0 7 0 0
T34 1 0 0 0
T39 1 0 0 0
T40 1 0 0 0
T41 0 10 0 0
T46 0 4 0 0
T47 0 7 0 0
T48 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1772 1328 0 0
T3 5 4 0 0
T5 0 10 0 0
T6 0 2 0 0
T7 4 3 0 0
T8 1 0 0 0
T9 1 0 0 0
T10 1 0 0 0
T16 1 0 0 0
T26 0 3 0 0
T27 0 4 0 0
T30 0 4 0 0
T34 1 0 0 0
T39 1 0 0 0
T40 1 0 0 0
T41 0 10 0 0
T46 0 4 0 0
T47 0 7 0 0
T48 1 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%